1 /* 2 * skl_topology.h - Intel HDA Platform topology header file 3 * 4 * Copyright (C) 2014-15 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SKL_TOPOLOGY_H__ 22 #define __SKL_TOPOLOGY_H__ 23 24 #include <linux/types.h> 25 26 #include <sound/hdaudio_ext.h> 27 #include <sound/soc.h> 28 #include "skl.h" 29 #include "skl-tplg-interface.h" 30 31 #define BITS_PER_BYTE 8 32 #define MAX_TS_GROUPS 8 33 #define MAX_DMIC_TS_GROUPS 4 34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 35 36 /* Maximum number of coefficients up down mixer module */ 37 #define UP_DOWN_MIXER_MAX_COEFF 6 38 39 #define MODULE_MAX_IN_PINS 8 40 #define MODULE_MAX_OUT_PINS 8 41 42 enum skl_channel_index { 43 SKL_CHANNEL_LEFT = 0, 44 SKL_CHANNEL_RIGHT = 1, 45 SKL_CHANNEL_CENTER = 2, 46 SKL_CHANNEL_LEFT_SURROUND = 3, 47 SKL_CHANNEL_CENTER_SURROUND = 3, 48 SKL_CHANNEL_RIGHT_SURROUND = 4, 49 SKL_CHANNEL_LFE = 7, 50 SKL_CHANNEL_INVALID = 0xF, 51 }; 52 53 enum skl_bitdepth { 54 SKL_DEPTH_8BIT = 8, 55 SKL_DEPTH_16BIT = 16, 56 SKL_DEPTH_24BIT = 24, 57 SKL_DEPTH_32BIT = 32, 58 SKL_DEPTH_INVALID 59 }; 60 61 62 enum skl_s_freq { 63 SKL_FS_8000 = 8000, 64 SKL_FS_11025 = 11025, 65 SKL_FS_12000 = 12000, 66 SKL_FS_16000 = 16000, 67 SKL_FS_22050 = 22050, 68 SKL_FS_24000 = 24000, 69 SKL_FS_32000 = 32000, 70 SKL_FS_44100 = 44100, 71 SKL_FS_48000 = 48000, 72 SKL_FS_64000 = 64000, 73 SKL_FS_88200 = 88200, 74 SKL_FS_96000 = 96000, 75 SKL_FS_128000 = 128000, 76 SKL_FS_176400 = 176400, 77 SKL_FS_192000 = 192000, 78 SKL_FS_INVALID 79 }; 80 81 enum skl_widget_type { 82 SKL_WIDGET_VMIXER = 1, 83 SKL_WIDGET_MIXER = 2, 84 SKL_WIDGET_PGA = 3, 85 SKL_WIDGET_MUX = 4 86 }; 87 88 struct skl_audio_data_format { 89 enum skl_s_freq s_freq; 90 enum skl_bitdepth bit_depth; 91 u32 channel_map; 92 enum skl_ch_cfg ch_cfg; 93 enum skl_interleaving interleaving; 94 u8 number_of_channels; 95 u8 valid_bit_depth; 96 u8 sample_type; 97 u8 reserved[1]; 98 } __packed; 99 100 struct skl_base_cfg { 101 u32 cps; 102 u32 ibs; 103 u32 obs; 104 u32 is_pages; 105 struct skl_audio_data_format audio_fmt; 106 }; 107 108 struct skl_cpr_gtw_cfg { 109 u32 node_id; 110 u32 dma_buffer_size; 111 u32 config_length; 112 /* not mandatory; required only for DMIC/I2S */ 113 u32 config_data[1]; 114 } __packed; 115 116 struct skl_cpr_cfg { 117 struct skl_base_cfg base_cfg; 118 struct skl_audio_data_format out_fmt; 119 u32 cpr_feature_mask; 120 struct skl_cpr_gtw_cfg gtw_cfg; 121 } __packed; 122 123 124 struct skl_src_module_cfg { 125 struct skl_base_cfg base_cfg; 126 enum skl_s_freq src_cfg; 127 } __packed; 128 129 struct notification_mask { 130 u32 notify; 131 u32 enable; 132 } __packed; 133 134 struct skl_up_down_mixer_cfg { 135 struct skl_base_cfg base_cfg; 136 enum skl_ch_cfg out_ch_cfg; 137 /* This should be set to 1 if user coefficients are required */ 138 u32 coeff_sel; 139 /* Pass the user coeff in this array */ 140 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 141 } __packed; 142 143 struct skl_algo_cfg { 144 struct skl_base_cfg base_cfg; 145 char params[0]; 146 } __packed; 147 148 struct skl_base_outfmt_cfg { 149 struct skl_base_cfg base_cfg; 150 struct skl_audio_data_format out_fmt; 151 } __packed; 152 153 enum skl_dma_type { 154 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 155 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 156 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 157 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 158 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 159 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 160 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 161 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 162 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 163 }; 164 165 union skl_ssp_dma_node { 166 u8 val; 167 struct { 168 u8 time_slot_index:4; 169 u8 i2s_instance:4; 170 } dma_node; 171 }; 172 173 union skl_connector_node_id { 174 u32 val; 175 struct { 176 u32 vindex:8; 177 u32 dma_type:4; 178 u32 rsvd:20; 179 } node; 180 }; 181 182 struct skl_module_fmt { 183 u32 channels; 184 u32 s_freq; 185 u32 bit_depth; 186 u32 valid_bit_depth; 187 u32 ch_cfg; 188 u32 interleaving_style; 189 u32 sample_type; 190 u32 ch_map; 191 }; 192 193 struct skl_module_cfg; 194 195 struct skl_module_inst_id { 196 u32 module_id; 197 u32 instance_id; 198 }; 199 200 enum skl_module_pin_state { 201 SKL_PIN_UNBIND = 0, 202 SKL_PIN_BIND_DONE = 1, 203 }; 204 205 struct skl_module_pin { 206 struct skl_module_inst_id id; 207 bool is_dynamic; 208 bool in_use; 209 enum skl_module_pin_state pin_state; 210 struct skl_module_cfg *tgt_mcfg; 211 }; 212 213 struct skl_specific_cfg { 214 u32 set_params; 215 u32 param_id; 216 u32 caps_size; 217 u32 *caps; 218 }; 219 220 enum skl_pipe_state { 221 SKL_PIPE_INVALID = 0, 222 SKL_PIPE_CREATED = 1, 223 SKL_PIPE_PAUSED = 2, 224 SKL_PIPE_STARTED = 3 225 }; 226 227 struct skl_pipe_module { 228 struct snd_soc_dapm_widget *w; 229 struct list_head node; 230 }; 231 232 struct skl_pipe_params { 233 u8 host_dma_id; 234 u8 link_dma_id; 235 u32 ch; 236 u32 s_freq; 237 u32 s_fmt; 238 u8 linktype; 239 int stream; 240 }; 241 242 struct skl_pipe { 243 u8 ppl_id; 244 u8 pipe_priority; 245 u16 conn_type; 246 u32 memory_pages; 247 struct skl_pipe_params *p_params; 248 enum skl_pipe_state state; 249 struct list_head w_list; 250 }; 251 252 enum skl_module_state { 253 SKL_MODULE_UNINIT = 0, 254 SKL_MODULE_INIT_DONE = 1, 255 SKL_MODULE_LOADED = 2, 256 SKL_MODULE_UNLOADED = 3, 257 SKL_MODULE_BIND_DONE = 4 258 }; 259 260 struct skl_module_cfg { 261 char guid[SKL_UUID_STR_SZ]; 262 struct skl_module_inst_id id; 263 u8 domain; 264 bool homogenous_inputs; 265 bool homogenous_outputs; 266 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 267 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 268 u8 max_in_queue; 269 u8 max_out_queue; 270 u8 in_queue_mask; 271 u8 out_queue_mask; 272 u8 in_queue; 273 u8 out_queue; 274 u32 mcps; 275 u32 ibs; 276 u32 obs; 277 u8 is_loadable; 278 u8 core_id; 279 u8 dev_type; 280 u8 dma_id; 281 u8 time_slot; 282 u32 params_fixup; 283 u32 converter; 284 u32 vbus_id; 285 u32 mem_pages; 286 struct skl_module_pin *m_in_pin; 287 struct skl_module_pin *m_out_pin; 288 enum skl_module_type m_type; 289 enum skl_hw_conn_type hw_conn_type; 290 enum skl_module_state m_state; 291 struct skl_pipe *pipe; 292 struct skl_specific_cfg formats_config; 293 }; 294 295 struct skl_algo_data { 296 u32 param_id; 297 u32 set_params; 298 u32 max; 299 char *params; 300 }; 301 302 struct skl_pipeline { 303 struct skl_pipe *pipe; 304 struct list_head node; 305 }; 306 307 static inline struct skl *get_skl_ctx(struct device *dev) 308 { 309 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 310 311 return ebus_to_skl(ebus); 312 } 313 314 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 315 struct skl_pipe_params *params); 316 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 317 struct skl_pipe_params *params, int stream); 318 int skl_tplg_init(struct snd_soc_platform *platform, 319 struct hdac_ext_bus *ebus); 320 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 321 struct snd_soc_dai *dai, int stream); 322 int skl_tplg_update_pipe_params(struct device *dev, 323 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 324 325 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 326 327 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 328 329 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 330 331 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 332 333 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 334 335 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 336 337 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 338 *src_module, struct skl_module_cfg *dst_module); 339 340 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 341 *src_module, struct skl_module_cfg *dst_module); 342 343 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 344 u32 param_id, struct skl_module_cfg *mcfg); 345 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 346 u32 param_id, struct skl_module_cfg *mcfg); 347 348 enum skl_bitdepth skl_get_bit_depth(int params); 349 #endif 350