1 /* 2 * skl_topology.h - Intel HDA Platform topology header file 3 * 4 * Copyright (C) 2014-15 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SKL_TOPOLOGY_H__ 22 #define __SKL_TOPOLOGY_H__ 23 24 #include <linux/types.h> 25 26 #include <sound/hdaudio_ext.h> 27 #include <sound/soc.h> 28 #include "skl.h" 29 #include "skl-tplg-interface.h" 30 31 #define BITS_PER_BYTE 8 32 #define MAX_TS_GROUPS 8 33 #define MAX_DMIC_TS_GROUPS 4 34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 35 36 /* Maximum number of coefficients up down mixer module */ 37 #define UP_DOWN_MIXER_MAX_COEFF 6 38 39 enum skl_channel_index { 40 SKL_CHANNEL_LEFT = 0, 41 SKL_CHANNEL_RIGHT = 1, 42 SKL_CHANNEL_CENTER = 2, 43 SKL_CHANNEL_LEFT_SURROUND = 3, 44 SKL_CHANNEL_CENTER_SURROUND = 3, 45 SKL_CHANNEL_RIGHT_SURROUND = 4, 46 SKL_CHANNEL_LFE = 7, 47 SKL_CHANNEL_INVALID = 0xF, 48 }; 49 50 enum skl_bitdepth { 51 SKL_DEPTH_8BIT = 8, 52 SKL_DEPTH_16BIT = 16, 53 SKL_DEPTH_24BIT = 24, 54 SKL_DEPTH_32BIT = 32, 55 SKL_DEPTH_INVALID 56 }; 57 58 enum skl_interleaving { 59 /* [s1_ch1...s1_chN,...,sM_ch1...sM_chN] */ 60 SKL_INTERLEAVING_PER_CHANNEL = 0, 61 /* [s1_ch1...sM_ch1,...,s1_chN...sM_chN] */ 62 SKL_INTERLEAVING_PER_SAMPLE = 1, 63 }; 64 65 enum skl_s_freq { 66 SKL_FS_8000 = 8000, 67 SKL_FS_11025 = 11025, 68 SKL_FS_12000 = 12000, 69 SKL_FS_16000 = 16000, 70 SKL_FS_22050 = 22050, 71 SKL_FS_24000 = 24000, 72 SKL_FS_32000 = 32000, 73 SKL_FS_44100 = 44100, 74 SKL_FS_48000 = 48000, 75 SKL_FS_64000 = 64000, 76 SKL_FS_88200 = 88200, 77 SKL_FS_96000 = 96000, 78 SKL_FS_128000 = 128000, 79 SKL_FS_176400 = 176400, 80 SKL_FS_192000 = 192000, 81 SKL_FS_INVALID 82 }; 83 84 enum skl_widget_type { 85 SKL_WIDGET_VMIXER = 1, 86 SKL_WIDGET_MIXER = 2, 87 SKL_WIDGET_PGA = 3, 88 SKL_WIDGET_MUX = 4 89 }; 90 91 struct skl_audio_data_format { 92 enum skl_s_freq s_freq; 93 enum skl_bitdepth bit_depth; 94 u32 channel_map; 95 enum skl_ch_cfg ch_cfg; 96 enum skl_interleaving interleaving; 97 u8 number_of_channels; 98 u8 valid_bit_depth; 99 u8 sample_type; 100 u8 reserved[1]; 101 } __packed; 102 103 struct skl_base_cfg { 104 u32 cps; 105 u32 ibs; 106 u32 obs; 107 u32 is_pages; 108 struct skl_audio_data_format audio_fmt; 109 }; 110 111 struct skl_cpr_gtw_cfg { 112 u32 node_id; 113 u32 dma_buffer_size; 114 u32 config_length; 115 /* not mandatory; required only for DMIC/I2S */ 116 u32 config_data[1]; 117 } __packed; 118 119 struct skl_cpr_cfg { 120 struct skl_base_cfg base_cfg; 121 struct skl_audio_data_format out_fmt; 122 u32 cpr_feature_mask; 123 struct skl_cpr_gtw_cfg gtw_cfg; 124 } __packed; 125 126 127 struct skl_src_module_cfg { 128 struct skl_base_cfg base_cfg; 129 enum skl_s_freq src_cfg; 130 } __packed; 131 132 struct notification_mask { 133 u32 notify; 134 u32 enable; 135 } __packed; 136 137 struct skl_up_down_mixer_cfg { 138 struct skl_base_cfg base_cfg; 139 enum skl_ch_cfg out_ch_cfg; 140 /* This should be set to 1 if user coefficients are required */ 141 u32 coeff_sel; 142 /* Pass the user coeff in this array */ 143 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 144 } __packed; 145 146 enum skl_dma_type { 147 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 148 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 149 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 150 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 151 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 152 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 153 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 154 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 155 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 156 }; 157 158 union skl_ssp_dma_node { 159 u8 val; 160 struct { 161 u8 time_slot_index:4; 162 u8 i2s_instance:4; 163 } dma_node; 164 }; 165 166 union skl_connector_node_id { 167 u32 val; 168 struct { 169 u32 vindex:8; 170 u32 dma_type:4; 171 u32 rsvd:20; 172 } node; 173 }; 174 175 struct skl_module_fmt { 176 u32 channels; 177 u32 s_freq; 178 u32 bit_depth; 179 u32 valid_bit_depth; 180 u32 ch_cfg; 181 }; 182 183 struct skl_module_inst_id { 184 u32 module_id; 185 u32 instance_id; 186 }; 187 188 struct skl_module_pin { 189 struct skl_module_inst_id id; 190 u8 pin_index; 191 bool is_dynamic; 192 bool in_use; 193 }; 194 195 struct skl_specific_cfg { 196 u32 caps_size; 197 u32 *caps; 198 }; 199 200 enum skl_pipe_state { 201 SKL_PIPE_INVALID = 0, 202 SKL_PIPE_CREATED = 1, 203 SKL_PIPE_PAUSED = 2, 204 SKL_PIPE_STARTED = 3 205 }; 206 207 struct skl_pipe_module { 208 struct snd_soc_dapm_widget *w; 209 struct list_head node; 210 }; 211 212 struct skl_pipe_params { 213 u8 host_dma_id; 214 u8 link_dma_id; 215 u32 ch; 216 u32 s_freq; 217 u32 s_fmt; 218 u8 linktype; 219 int stream; 220 }; 221 222 struct skl_pipe { 223 u8 ppl_id; 224 u8 pipe_priority; 225 u16 conn_type; 226 u32 memory_pages; 227 struct skl_pipe_params *p_params; 228 enum skl_pipe_state state; 229 struct list_head w_list; 230 }; 231 232 enum skl_module_state { 233 SKL_MODULE_UNINIT = 0, 234 SKL_MODULE_INIT_DONE = 1, 235 SKL_MODULE_LOADED = 2, 236 SKL_MODULE_UNLOADED = 3, 237 SKL_MODULE_BIND_DONE = 4 238 }; 239 240 struct skl_module_cfg { 241 struct skl_module_inst_id id; 242 struct skl_module_fmt in_fmt; 243 struct skl_module_fmt out_fmt; 244 u8 max_in_queue; 245 u8 max_out_queue; 246 u8 in_queue_mask; 247 u8 out_queue_mask; 248 u8 in_queue; 249 u8 out_queue; 250 u32 mcps; 251 u32 ibs; 252 u32 obs; 253 u8 is_loadable; 254 u8 core_id; 255 u8 dev_type; 256 u8 dma_id; 257 u8 time_slot; 258 u32 params_fixup; 259 u32 converter; 260 u32 vbus_id; 261 struct skl_module_pin *m_in_pin; 262 struct skl_module_pin *m_out_pin; 263 enum skl_module_type m_type; 264 enum skl_hw_conn_type hw_conn_type; 265 enum skl_module_state m_state; 266 struct skl_pipe *pipe; 267 struct skl_specific_cfg formats_config; 268 }; 269 270 struct skl_pipeline { 271 struct skl_pipe *pipe; 272 struct list_head node; 273 }; 274 275 struct skl_dapm_path_list { 276 struct snd_soc_dapm_path *dapm_path; 277 struct list_head node; 278 }; 279 280 static inline struct skl *get_skl_ctx(struct device *dev) 281 { 282 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 283 284 return ebus_to_skl(ebus); 285 } 286 287 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 288 struct skl_pipe_params *params); 289 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 290 struct skl_pipe_params *params, int stream); 291 int skl_tplg_init(struct snd_soc_platform *platform, 292 struct hdac_ext_bus *ebus); 293 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 294 struct snd_soc_dai *dai, int stream); 295 int skl_tplg_update_pipe_params(struct device *dev, 296 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 297 298 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 299 300 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 301 302 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 303 304 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 305 306 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 307 308 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config, 309 char *param); 310 311 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 312 *src_module, struct skl_module_cfg *dst_module); 313 314 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 315 *src_module, struct skl_module_cfg *dst_module); 316 317 enum skl_bitdepth skl_get_bit_depth(int params); 318 #endif 319