1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * skl_topology.h - Intel HDA Platform topology header file 4 * 5 * Copyright (C) 2014-15 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 */ 11 12 #ifndef __SKL_TOPOLOGY_H__ 13 #define __SKL_TOPOLOGY_H__ 14 15 #include <linux/types.h> 16 17 #include <sound/hdaudio_ext.h> 18 #include <sound/soc.h> 19 #include <uapi/sound/skl-tplg-interface.h> 20 #include "skl.h" 21 22 #define BITS_PER_BYTE 8 23 #define MAX_TS_GROUPS 8 24 #define MAX_DMIC_TS_GROUPS 4 25 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 26 27 /* Maximum number of coefficients up down mixer module */ 28 #define UP_DOWN_MIXER_MAX_COEFF 8 29 30 #define MODULE_MAX_IN_PINS 8 31 #define MODULE_MAX_OUT_PINS 8 32 33 #define SKL_MIC_CH_SUPPORT 4 34 #define SKL_MIC_MAX_CH_SUPPORT 8 35 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 36 #define SKL_MIC_SEL_SWITCH 0x3 37 38 #define SKL_OUTPUT_PIN 0 39 #define SKL_INPUT_PIN 1 40 #define SKL_MAX_PATH_CONFIGS 8 41 #define SKL_MAX_MODULES_IN_PIPE 8 42 #define SKL_MAX_MODULE_FORMATS 32 43 #define SKL_MAX_MODULE_RESOURCES 32 44 45 enum skl_channel_index { 46 SKL_CHANNEL_LEFT = 0, 47 SKL_CHANNEL_RIGHT = 1, 48 SKL_CHANNEL_CENTER = 2, 49 SKL_CHANNEL_LEFT_SURROUND = 3, 50 SKL_CHANNEL_CENTER_SURROUND = 3, 51 SKL_CHANNEL_RIGHT_SURROUND = 4, 52 SKL_CHANNEL_LFE = 7, 53 SKL_CHANNEL_INVALID = 0xF, 54 }; 55 56 enum skl_bitdepth { 57 SKL_DEPTH_8BIT = 8, 58 SKL_DEPTH_16BIT = 16, 59 SKL_DEPTH_24BIT = 24, 60 SKL_DEPTH_32BIT = 32, 61 SKL_DEPTH_INVALID 62 }; 63 64 65 enum skl_s_freq { 66 SKL_FS_8000 = 8000, 67 SKL_FS_11025 = 11025, 68 SKL_FS_12000 = 12000, 69 SKL_FS_16000 = 16000, 70 SKL_FS_22050 = 22050, 71 SKL_FS_24000 = 24000, 72 SKL_FS_32000 = 32000, 73 SKL_FS_44100 = 44100, 74 SKL_FS_48000 = 48000, 75 SKL_FS_64000 = 64000, 76 SKL_FS_88200 = 88200, 77 SKL_FS_96000 = 96000, 78 SKL_FS_128000 = 128000, 79 SKL_FS_176400 = 176400, 80 SKL_FS_192000 = 192000, 81 SKL_FS_INVALID 82 }; 83 84 enum skl_widget_type { 85 SKL_WIDGET_VMIXER = 1, 86 SKL_WIDGET_MIXER = 2, 87 SKL_WIDGET_PGA = 3, 88 SKL_WIDGET_MUX = 4 89 }; 90 91 struct skl_audio_data_format { 92 enum skl_s_freq s_freq; 93 enum skl_bitdepth bit_depth; 94 u32 channel_map; 95 enum skl_ch_cfg ch_cfg; 96 enum skl_interleaving interleaving; 97 u8 number_of_channels; 98 u8 valid_bit_depth; 99 u8 sample_type; 100 u8 reserved[1]; 101 } __packed; 102 103 struct skl_base_cfg { 104 u32 cps; 105 u32 ibs; 106 u32 obs; 107 u32 is_pages; 108 struct skl_audio_data_format audio_fmt; 109 }; 110 111 struct skl_cpr_gtw_cfg { 112 u32 node_id; 113 u32 dma_buffer_size; 114 u32 config_length; 115 /* not mandatory; required only for DMIC/I2S */ 116 u32 config_data[1]; 117 } __packed; 118 119 struct skl_dma_control { 120 u32 node_id; 121 u32 config_length; 122 u32 config_data[0]; 123 } __packed; 124 125 struct skl_cpr_cfg { 126 struct skl_base_cfg base_cfg; 127 struct skl_audio_data_format out_fmt; 128 u32 cpr_feature_mask; 129 struct skl_cpr_gtw_cfg gtw_cfg; 130 } __packed; 131 132 struct skl_cpr_pin_fmt { 133 u32 sink_id; 134 struct skl_audio_data_format src_fmt; 135 struct skl_audio_data_format dst_fmt; 136 } __packed; 137 138 struct skl_src_module_cfg { 139 struct skl_base_cfg base_cfg; 140 enum skl_s_freq src_cfg; 141 } __packed; 142 143 struct notification_mask { 144 u32 notify; 145 u32 enable; 146 } __packed; 147 148 struct skl_up_down_mixer_cfg { 149 struct skl_base_cfg base_cfg; 150 enum skl_ch_cfg out_ch_cfg; 151 /* This should be set to 1 if user coefficients are required */ 152 u32 coeff_sel; 153 /* Pass the user coeff in this array */ 154 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 155 u32 ch_map; 156 } __packed; 157 158 struct skl_algo_cfg { 159 struct skl_base_cfg base_cfg; 160 char params[0]; 161 } __packed; 162 163 struct skl_base_outfmt_cfg { 164 struct skl_base_cfg base_cfg; 165 struct skl_audio_data_format out_fmt; 166 } __packed; 167 168 enum skl_dma_type { 169 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 170 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 171 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 172 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 173 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 174 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 175 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 176 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 177 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 178 }; 179 180 union skl_ssp_dma_node { 181 u8 val; 182 struct { 183 u8 time_slot_index:4; 184 u8 i2s_instance:4; 185 } dma_node; 186 }; 187 188 union skl_connector_node_id { 189 u32 val; 190 struct { 191 u32 vindex:8; 192 u32 dma_type:4; 193 u32 rsvd:20; 194 } node; 195 }; 196 197 struct skl_module_fmt { 198 u32 channels; 199 u32 s_freq; 200 u32 bit_depth; 201 u32 valid_bit_depth; 202 u32 ch_cfg; 203 u32 interleaving_style; 204 u32 sample_type; 205 u32 ch_map; 206 }; 207 208 struct skl_module_cfg; 209 210 struct skl_mod_inst_map { 211 u16 mod_id; 212 u16 inst_id; 213 }; 214 215 struct skl_uuid_inst_map { 216 u16 inst_id; 217 u16 reserved; 218 uuid_le mod_uuid; 219 } __packed; 220 221 struct skl_kpb_params { 222 u32 num_modules; 223 union { 224 struct skl_mod_inst_map map[0]; 225 struct skl_uuid_inst_map map_uuid[0]; 226 } u; 227 }; 228 229 struct skl_module_inst_id { 230 uuid_le mod_uuid; 231 int module_id; 232 u32 instance_id; 233 int pvt_id; 234 }; 235 236 enum skl_module_pin_state { 237 SKL_PIN_UNBIND = 0, 238 SKL_PIN_BIND_DONE = 1, 239 }; 240 241 struct skl_module_pin { 242 struct skl_module_inst_id id; 243 bool is_dynamic; 244 bool in_use; 245 enum skl_module_pin_state pin_state; 246 struct skl_module_cfg *tgt_mcfg; 247 }; 248 249 struct skl_specific_cfg { 250 u32 set_params; 251 u32 param_id; 252 u32 caps_size; 253 u32 *caps; 254 }; 255 256 enum skl_pipe_state { 257 SKL_PIPE_INVALID = 0, 258 SKL_PIPE_CREATED = 1, 259 SKL_PIPE_PAUSED = 2, 260 SKL_PIPE_STARTED = 3, 261 SKL_PIPE_RESET = 4 262 }; 263 264 struct skl_pipe_module { 265 struct snd_soc_dapm_widget *w; 266 struct list_head node; 267 }; 268 269 struct skl_pipe_params { 270 u8 host_dma_id; 271 u8 link_dma_id; 272 u32 ch; 273 u32 s_freq; 274 u32 s_fmt; 275 u8 linktype; 276 snd_pcm_format_t format; 277 int link_index; 278 int stream; 279 unsigned int host_bps; 280 unsigned int link_bps; 281 }; 282 283 struct skl_pipe_fmt { 284 u32 freq; 285 u8 channels; 286 u8 bps; 287 }; 288 289 struct skl_pipe_mcfg { 290 u8 res_idx; 291 u8 fmt_idx; 292 }; 293 294 struct skl_path_config { 295 u8 mem_pages; 296 struct skl_pipe_fmt in_fmt; 297 struct skl_pipe_fmt out_fmt; 298 }; 299 300 struct skl_pipe { 301 u8 ppl_id; 302 u8 pipe_priority; 303 u16 conn_type; 304 u32 memory_pages; 305 u8 lp_mode; 306 struct skl_pipe_params *p_params; 307 enum skl_pipe_state state; 308 u8 direction; 309 u8 cur_config_idx; 310 u8 nr_cfgs; 311 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS]; 312 struct list_head w_list; 313 bool passthru; 314 }; 315 316 enum skl_module_state { 317 SKL_MODULE_UNINIT = 0, 318 SKL_MODULE_LOADED = 1, 319 SKL_MODULE_INIT_DONE = 2, 320 SKL_MODULE_BIND_DONE = 3, 321 SKL_MODULE_UNLOADED = 4, 322 }; 323 324 enum d0i3_capability { 325 SKL_D0I3_NONE = 0, 326 SKL_D0I3_STREAMING = 1, 327 SKL_D0I3_NON_STREAMING = 2, 328 }; 329 330 struct skl_module_pin_fmt { 331 u8 id; 332 struct skl_module_fmt fmt; 333 }; 334 335 struct skl_module_iface { 336 u8 fmt_idx; 337 u8 nr_in_fmt; 338 u8 nr_out_fmt; 339 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE]; 340 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE]; 341 }; 342 343 struct skl_module_pin_resources { 344 u8 pin_index; 345 u32 buf_size; 346 }; 347 348 struct skl_module_res { 349 u8 id; 350 u32 is_pages; 351 u32 cps; 352 u32 ibs; 353 u32 obs; 354 u32 dma_buffer_size; 355 u32 cpc; 356 u8 nr_input_pins; 357 u8 nr_output_pins; 358 struct skl_module_pin_resources input[MAX_IN_QUEUE]; 359 struct skl_module_pin_resources output[MAX_OUT_QUEUE]; 360 }; 361 362 struct skl_module { 363 uuid_le uuid; 364 u8 loadable; 365 u8 input_pin_type; 366 u8 output_pin_type; 367 u8 max_input_pins; 368 u8 max_output_pins; 369 u8 nr_resources; 370 u8 nr_interfaces; 371 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES]; 372 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS]; 373 }; 374 375 struct skl_module_cfg { 376 u8 guid[16]; 377 struct skl_module_inst_id id; 378 struct skl_module *module; 379 int res_idx; 380 int fmt_idx; 381 u8 domain; 382 bool homogenous_inputs; 383 bool homogenous_outputs; 384 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 385 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 386 u8 max_in_queue; 387 u8 max_out_queue; 388 u8 in_queue_mask; 389 u8 out_queue_mask; 390 u8 in_queue; 391 u8 out_queue; 392 u32 mcps; 393 u32 ibs; 394 u32 obs; 395 u8 is_loadable; 396 u8 core_id; 397 u8 dev_type; 398 u8 dma_id; 399 u8 time_slot; 400 u8 dmic_ch_combo_index; 401 u32 dmic_ch_type; 402 u32 params_fixup; 403 u32 converter; 404 u32 vbus_id; 405 u32 mem_pages; 406 enum d0i3_capability d0i3_caps; 407 u32 dma_buffer_size; /* in milli seconds */ 408 struct skl_module_pin *m_in_pin; 409 struct skl_module_pin *m_out_pin; 410 enum skl_module_type m_type; 411 enum skl_hw_conn_type hw_conn_type; 412 enum skl_module_state m_state; 413 struct skl_pipe *pipe; 414 struct skl_specific_cfg formats_config; 415 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE]; 416 }; 417 418 struct skl_algo_data { 419 u32 param_id; 420 u32 set_params; 421 u32 max; 422 u32 size; 423 char *params; 424 }; 425 426 struct skl_pipeline { 427 struct skl_pipe *pipe; 428 struct list_head node; 429 }; 430 431 struct skl_module_deferred_bind { 432 struct skl_module_cfg *src; 433 struct skl_module_cfg *dst; 434 struct list_head node; 435 }; 436 437 struct skl_mic_sel_config { 438 u16 mic_switch; 439 u16 flags; 440 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 441 } __packed; 442 443 enum skl_channel { 444 SKL_CH_MONO = 1, 445 SKL_CH_STEREO = 2, 446 SKL_CH_TRIO = 3, 447 SKL_CH_QUATRO = 4, 448 }; 449 450 static inline struct skl *get_skl_ctx(struct device *dev) 451 { 452 struct hdac_bus *bus = dev_get_drvdata(dev); 453 454 return bus_to_skl(bus); 455 } 456 457 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 458 struct skl_pipe_params *params); 459 int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps, 460 u32 caps_size, u32 node_id); 461 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 462 struct skl_pipe_params *params, int stream); 463 int skl_tplg_init(struct snd_soc_component *component, 464 struct hdac_bus *ebus); 465 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 466 struct snd_soc_dai *dai, int stream); 467 int skl_tplg_update_pipe_params(struct device *dev, 468 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 469 470 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps); 471 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps); 472 473 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 474 475 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 476 477 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 478 479 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 480 481 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 482 483 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 484 485 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 486 487 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 488 *src_module, struct skl_module_cfg *dst_module); 489 490 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 491 *src_module, struct skl_module_cfg *dst_module); 492 493 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 494 u32 param_id, struct skl_module_cfg *mcfg); 495 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 496 u32 param_id, struct skl_module_cfg *mcfg); 497 498 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 499 int stream); 500 enum skl_bitdepth skl_get_bit_depth(int params); 501 int skl_pcm_host_dma_prepare(struct device *dev, 502 struct skl_pipe_params *params); 503 int skl_pcm_link_dma_prepare(struct device *dev, 504 struct skl_pipe_params *params); 505 506 int skl_dai_load(struct snd_soc_component *cmp, int index, 507 struct snd_soc_dai_driver *dai_drv, 508 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); 509 void skl_tplg_add_moduleid_in_bind_params(struct skl *skl, 510 struct snd_soc_dapm_widget *w); 511 #endif 512