1 /* 2 * skl_topology.h - Intel HDA Platform topology header file 3 * 4 * Copyright (C) 2014-15 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SKL_TOPOLOGY_H__ 22 #define __SKL_TOPOLOGY_H__ 23 24 #include <linux/types.h> 25 26 #include <sound/hdaudio_ext.h> 27 #include <sound/soc.h> 28 #include "skl.h" 29 #include "skl-tplg-interface.h" 30 31 #define BITS_PER_BYTE 8 32 #define MAX_TS_GROUPS 8 33 #define MAX_DMIC_TS_GROUPS 4 34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 35 36 /* Maximum number of coefficients up down mixer module */ 37 #define UP_DOWN_MIXER_MAX_COEFF 6 38 39 #define MODULE_MAX_IN_PINS 8 40 #define MODULE_MAX_OUT_PINS 8 41 42 #define SKL_MIC_CH_SUPPORT 4 43 #define SKL_MIC_MAX_CH_SUPPORT 8 44 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 45 #define SKL_MIC_SEL_SWITCH 0x3 46 47 #define SKL_OUTPUT_PIN 0 48 #define SKL_INPUT_PIN 1 49 #define SKL_MAX_PATH_CONFIGS 8 50 #define SKL_MAX_MODULES_IN_PIPE 8 51 #define SKL_MAX_MODULE_FORMATS 32 52 #define SKL_MAX_MODULE_RESOURCES 32 53 54 enum skl_channel_index { 55 SKL_CHANNEL_LEFT = 0, 56 SKL_CHANNEL_RIGHT = 1, 57 SKL_CHANNEL_CENTER = 2, 58 SKL_CHANNEL_LEFT_SURROUND = 3, 59 SKL_CHANNEL_CENTER_SURROUND = 3, 60 SKL_CHANNEL_RIGHT_SURROUND = 4, 61 SKL_CHANNEL_LFE = 7, 62 SKL_CHANNEL_INVALID = 0xF, 63 }; 64 65 enum skl_bitdepth { 66 SKL_DEPTH_8BIT = 8, 67 SKL_DEPTH_16BIT = 16, 68 SKL_DEPTH_24BIT = 24, 69 SKL_DEPTH_32BIT = 32, 70 SKL_DEPTH_INVALID 71 }; 72 73 74 enum skl_s_freq { 75 SKL_FS_8000 = 8000, 76 SKL_FS_11025 = 11025, 77 SKL_FS_12000 = 12000, 78 SKL_FS_16000 = 16000, 79 SKL_FS_22050 = 22050, 80 SKL_FS_24000 = 24000, 81 SKL_FS_32000 = 32000, 82 SKL_FS_44100 = 44100, 83 SKL_FS_48000 = 48000, 84 SKL_FS_64000 = 64000, 85 SKL_FS_88200 = 88200, 86 SKL_FS_96000 = 96000, 87 SKL_FS_128000 = 128000, 88 SKL_FS_176400 = 176400, 89 SKL_FS_192000 = 192000, 90 SKL_FS_INVALID 91 }; 92 93 enum skl_widget_type { 94 SKL_WIDGET_VMIXER = 1, 95 SKL_WIDGET_MIXER = 2, 96 SKL_WIDGET_PGA = 3, 97 SKL_WIDGET_MUX = 4 98 }; 99 100 struct skl_audio_data_format { 101 enum skl_s_freq s_freq; 102 enum skl_bitdepth bit_depth; 103 u32 channel_map; 104 enum skl_ch_cfg ch_cfg; 105 enum skl_interleaving interleaving; 106 u8 number_of_channels; 107 u8 valid_bit_depth; 108 u8 sample_type; 109 u8 reserved[1]; 110 } __packed; 111 112 struct skl_base_cfg { 113 u32 cps; 114 u32 ibs; 115 u32 obs; 116 u32 is_pages; 117 struct skl_audio_data_format audio_fmt; 118 }; 119 120 struct skl_cpr_gtw_cfg { 121 u32 node_id; 122 u32 dma_buffer_size; 123 u32 config_length; 124 /* not mandatory; required only for DMIC/I2S */ 125 u32 config_data[1]; 126 } __packed; 127 128 struct skl_dma_control { 129 u32 node_id; 130 u32 config_length; 131 u32 config_data[0]; 132 } __packed; 133 134 struct skl_cpr_cfg { 135 struct skl_base_cfg base_cfg; 136 struct skl_audio_data_format out_fmt; 137 u32 cpr_feature_mask; 138 struct skl_cpr_gtw_cfg gtw_cfg; 139 } __packed; 140 141 struct skl_cpr_pin_fmt { 142 u32 sink_id; 143 struct skl_audio_data_format src_fmt; 144 struct skl_audio_data_format dst_fmt; 145 } __packed; 146 147 struct skl_src_module_cfg { 148 struct skl_base_cfg base_cfg; 149 enum skl_s_freq src_cfg; 150 } __packed; 151 152 struct notification_mask { 153 u32 notify; 154 u32 enable; 155 } __packed; 156 157 struct skl_up_down_mixer_cfg { 158 struct skl_base_cfg base_cfg; 159 enum skl_ch_cfg out_ch_cfg; 160 /* This should be set to 1 if user coefficients are required */ 161 u32 coeff_sel; 162 /* Pass the user coeff in this array */ 163 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 164 } __packed; 165 166 struct skl_algo_cfg { 167 struct skl_base_cfg base_cfg; 168 char params[0]; 169 } __packed; 170 171 struct skl_base_outfmt_cfg { 172 struct skl_base_cfg base_cfg; 173 struct skl_audio_data_format out_fmt; 174 } __packed; 175 176 enum skl_dma_type { 177 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 178 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 179 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 180 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 181 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 182 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 183 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 184 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 185 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 186 }; 187 188 union skl_ssp_dma_node { 189 u8 val; 190 struct { 191 u8 time_slot_index:4; 192 u8 i2s_instance:4; 193 } dma_node; 194 }; 195 196 union skl_connector_node_id { 197 u32 val; 198 struct { 199 u32 vindex:8; 200 u32 dma_type:4; 201 u32 rsvd:20; 202 } node; 203 }; 204 205 struct skl_module_fmt { 206 u32 channels; 207 u32 s_freq; 208 u32 bit_depth; 209 u32 valid_bit_depth; 210 u32 ch_cfg; 211 u32 interleaving_style; 212 u32 sample_type; 213 u32 ch_map; 214 }; 215 216 struct skl_module_cfg; 217 218 struct skl_mod_inst_map { 219 u16 mod_id; 220 u16 inst_id; 221 }; 222 223 struct skl_kpb_params { 224 u32 num_modules; 225 struct skl_mod_inst_map map[0]; 226 }; 227 228 struct skl_module_inst_id { 229 uuid_le mod_uuid; 230 int module_id; 231 u32 instance_id; 232 int pvt_id; 233 }; 234 235 enum skl_module_pin_state { 236 SKL_PIN_UNBIND = 0, 237 SKL_PIN_BIND_DONE = 1, 238 }; 239 240 struct skl_module_pin { 241 struct skl_module_inst_id id; 242 bool is_dynamic; 243 bool in_use; 244 enum skl_module_pin_state pin_state; 245 struct skl_module_cfg *tgt_mcfg; 246 }; 247 248 struct skl_specific_cfg { 249 u32 set_params; 250 u32 param_id; 251 u32 caps_size; 252 u32 *caps; 253 }; 254 255 enum skl_pipe_state { 256 SKL_PIPE_INVALID = 0, 257 SKL_PIPE_CREATED = 1, 258 SKL_PIPE_PAUSED = 2, 259 SKL_PIPE_STARTED = 3, 260 SKL_PIPE_RESET = 4 261 }; 262 263 struct skl_pipe_module { 264 struct snd_soc_dapm_widget *w; 265 struct list_head node; 266 }; 267 268 struct skl_pipe_params { 269 u8 host_dma_id; 270 u8 link_dma_id; 271 u32 ch; 272 u32 s_freq; 273 u32 s_fmt; 274 u8 linktype; 275 snd_pcm_format_t format; 276 int link_index; 277 int stream; 278 unsigned int host_bps; 279 unsigned int link_bps; 280 }; 281 282 struct skl_pipe_fmt { 283 u32 freq; 284 u8 channels; 285 u8 bps; 286 }; 287 288 struct skl_pipe_mcfg { 289 u8 res_idx; 290 u8 fmt_idx; 291 }; 292 293 struct skl_path_config { 294 u8 mem_pages; 295 struct skl_pipe_fmt in_fmt; 296 struct skl_pipe_fmt out_fmt; 297 }; 298 299 struct skl_pipe { 300 u8 ppl_id; 301 u8 pipe_priority; 302 u16 conn_type; 303 u32 memory_pages; 304 u8 lp_mode; 305 struct skl_pipe_params *p_params; 306 enum skl_pipe_state state; 307 u8 direction; 308 u8 cur_config_idx; 309 u8 nr_cfgs; 310 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS]; 311 struct list_head w_list; 312 bool passthru; 313 }; 314 315 enum skl_module_state { 316 SKL_MODULE_UNINIT = 0, 317 SKL_MODULE_LOADED = 1, 318 SKL_MODULE_INIT_DONE = 2, 319 SKL_MODULE_BIND_DONE = 3, 320 SKL_MODULE_UNLOADED = 4, 321 }; 322 323 enum d0i3_capability { 324 SKL_D0I3_NONE = 0, 325 SKL_D0I3_STREAMING = 1, 326 SKL_D0I3_NON_STREAMING = 2, 327 }; 328 329 struct skl_module_pin_fmt { 330 u8 id; 331 struct skl_module_fmt fmt; 332 }; 333 334 struct skl_module_iface { 335 u8 fmt_idx; 336 u8 nr_in_fmt; 337 u8 nr_out_fmt; 338 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE]; 339 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE]; 340 }; 341 342 struct skl_module_pin_resources { 343 u8 pin_index; 344 u32 buf_size; 345 }; 346 347 struct skl_module_res { 348 u8 id; 349 u32 is_pages; 350 u32 cps; 351 u32 ibs; 352 u32 obs; 353 u32 dma_buffer_size; 354 u32 cpc; 355 u8 nr_input_pins; 356 u8 nr_output_pins; 357 struct skl_module_pin_resources input[MAX_IN_QUEUE]; 358 struct skl_module_pin_resources output[MAX_OUT_QUEUE]; 359 }; 360 361 struct skl_module { 362 uuid_le uuid; 363 u8 loadable; 364 u8 input_pin_type; 365 u8 output_pin_type; 366 u8 max_input_pins; 367 u8 max_output_pins; 368 u8 nr_resources; 369 u8 nr_interfaces; 370 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES]; 371 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS]; 372 }; 373 374 struct skl_module_cfg { 375 u8 guid[16]; 376 struct skl_module_inst_id id; 377 struct skl_module *module; 378 int res_idx; 379 int fmt_idx; 380 u8 domain; 381 bool homogenous_inputs; 382 bool homogenous_outputs; 383 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 384 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 385 u8 max_in_queue; 386 u8 max_out_queue; 387 u8 in_queue_mask; 388 u8 out_queue_mask; 389 u8 in_queue; 390 u8 out_queue; 391 u32 mcps; 392 u32 ibs; 393 u32 obs; 394 u8 is_loadable; 395 u8 core_id; 396 u8 dev_type; 397 u8 dma_id; 398 u8 time_slot; 399 u8 dmic_ch_combo_index; 400 u32 dmic_ch_type; 401 u32 params_fixup; 402 u32 converter; 403 u32 vbus_id; 404 u32 mem_pages; 405 enum d0i3_capability d0i3_caps; 406 u32 dma_buffer_size; /* in milli seconds */ 407 struct skl_module_pin *m_in_pin; 408 struct skl_module_pin *m_out_pin; 409 enum skl_module_type m_type; 410 enum skl_hw_conn_type hw_conn_type; 411 enum skl_module_state m_state; 412 struct skl_pipe *pipe; 413 struct skl_specific_cfg formats_config; 414 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE]; 415 }; 416 417 struct skl_algo_data { 418 u32 param_id; 419 u32 set_params; 420 u32 max; 421 u32 size; 422 char *params; 423 }; 424 425 struct skl_pipeline { 426 struct skl_pipe *pipe; 427 struct list_head node; 428 }; 429 430 struct skl_module_deferred_bind { 431 struct skl_module_cfg *src; 432 struct skl_module_cfg *dst; 433 struct list_head node; 434 }; 435 436 struct skl_mic_sel_config { 437 u16 mic_switch; 438 u16 flags; 439 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 440 } __packed; 441 442 enum skl_channel { 443 SKL_CH_MONO = 1, 444 SKL_CH_STEREO = 2, 445 SKL_CH_TRIO = 3, 446 SKL_CH_QUATRO = 4, 447 }; 448 449 static inline struct skl *get_skl_ctx(struct device *dev) 450 { 451 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 452 453 return ebus_to_skl(ebus); 454 } 455 456 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 457 struct skl_pipe_params *params); 458 int skl_dsp_set_dma_control(struct skl_sst *ctx, 459 struct skl_module_cfg *mconfig); 460 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 461 struct skl_pipe_params *params, int stream); 462 int skl_tplg_init(struct snd_soc_platform *platform, 463 struct hdac_ext_bus *ebus); 464 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 465 struct snd_soc_dai *dai, int stream); 466 int skl_tplg_update_pipe_params(struct device *dev, 467 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 468 469 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps); 470 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps); 471 472 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 473 474 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 475 476 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 477 478 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 479 480 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 481 482 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 483 484 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 485 486 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 487 *src_module, struct skl_module_cfg *dst_module); 488 489 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 490 *src_module, struct skl_module_cfg *dst_module); 491 492 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 493 u32 param_id, struct skl_module_cfg *mcfg); 494 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 495 u32 param_id, struct skl_module_cfg *mcfg); 496 497 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 498 int stream); 499 enum skl_bitdepth skl_get_bit_depth(int params); 500 int skl_pcm_host_dma_prepare(struct device *dev, 501 struct skl_pipe_params *params); 502 int skl_pcm_link_dma_prepare(struct device *dev, 503 struct skl_pipe_params *params); 504 #endif 505