1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  skl_topology.h - Intel HDA Platform topology header file
4  *
5  *  Copyright (C) 2014-15 Intel Corp
6  *  Author: Jeeja KP <jeeja.kp@intel.com>
7  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8  *
9  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10  */
11 
12 #ifndef __SKL_TOPOLOGY_H__
13 #define __SKL_TOPOLOGY_H__
14 
15 #include <linux/types.h>
16 
17 #include <sound/hdaudio_ext.h>
18 #include <sound/soc.h>
19 #include <uapi/sound/skl-tplg-interface.h>
20 #include "skl.h"
21 
22 #define BITS_PER_BYTE 8
23 #define MAX_TS_GROUPS 8
24 #define MAX_DMIC_TS_GROUPS 4
25 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
26 
27 /* Maximum number of coefficients up down mixer module */
28 #define UP_DOWN_MIXER_MAX_COEFF		8
29 
30 #define MODULE_MAX_IN_PINS	8
31 #define MODULE_MAX_OUT_PINS	8
32 
33 #define SKL_MIC_CH_SUPPORT	4
34 #define SKL_MIC_MAX_CH_SUPPORT	8
35 #define SKL_DEFAULT_MIC_SEL_GAIN	0x3FF
36 #define SKL_MIC_SEL_SWITCH	0x3
37 
38 #define SKL_OUTPUT_PIN		0
39 #define SKL_INPUT_PIN		1
40 #define SKL_MAX_PATH_CONFIGS	8
41 #define SKL_MAX_MODULES_IN_PIPE	8
42 #define SKL_MAX_MODULE_FORMATS		32
43 #define SKL_MAX_MODULE_RESOURCES	32
44 
45 enum skl_channel_index {
46 	SKL_CHANNEL_LEFT = 0,
47 	SKL_CHANNEL_RIGHT = 1,
48 	SKL_CHANNEL_CENTER = 2,
49 	SKL_CHANNEL_LEFT_SURROUND = 3,
50 	SKL_CHANNEL_CENTER_SURROUND = 3,
51 	SKL_CHANNEL_RIGHT_SURROUND = 4,
52 	SKL_CHANNEL_LFE = 7,
53 	SKL_CHANNEL_INVALID = 0xF,
54 };
55 
56 enum skl_bitdepth {
57 	SKL_DEPTH_8BIT = 8,
58 	SKL_DEPTH_16BIT = 16,
59 	SKL_DEPTH_24BIT = 24,
60 	SKL_DEPTH_32BIT = 32,
61 	SKL_DEPTH_INVALID
62 };
63 
64 
65 enum skl_s_freq {
66 	SKL_FS_8000 = 8000,
67 	SKL_FS_11025 = 11025,
68 	SKL_FS_12000 = 12000,
69 	SKL_FS_16000 = 16000,
70 	SKL_FS_22050 = 22050,
71 	SKL_FS_24000 = 24000,
72 	SKL_FS_32000 = 32000,
73 	SKL_FS_44100 = 44100,
74 	SKL_FS_48000 = 48000,
75 	SKL_FS_64000 = 64000,
76 	SKL_FS_88200 = 88200,
77 	SKL_FS_96000 = 96000,
78 	SKL_FS_128000 = 128000,
79 	SKL_FS_176400 = 176400,
80 	SKL_FS_192000 = 192000,
81 	SKL_FS_INVALID
82 };
83 
84 #define SKL_MAX_PARAMS_TYPES	4
85 
86 enum skl_widget_type {
87 	SKL_WIDGET_VMIXER = 1,
88 	SKL_WIDGET_MIXER = 2,
89 	SKL_WIDGET_PGA = 3,
90 	SKL_WIDGET_MUX = 4
91 };
92 
93 struct skl_audio_data_format {
94 	enum skl_s_freq s_freq;
95 	enum skl_bitdepth bit_depth;
96 	u32 channel_map;
97 	enum skl_ch_cfg ch_cfg;
98 	enum skl_interleaving interleaving;
99 	u8 number_of_channels;
100 	u8 valid_bit_depth;
101 	u8 sample_type;
102 	u8 reserved;
103 } __packed;
104 
105 struct skl_base_cfg {
106 	u32 cpc;
107 	u32 ibs;
108 	u32 obs;
109 	u32 is_pages;
110 	struct skl_audio_data_format audio_fmt;
111 };
112 
113 struct skl_cpr_gtw_cfg {
114 	u32 node_id;
115 	u32 dma_buffer_size;
116 	u32 config_length;
117 	/* not mandatory; required only for DMIC/I2S */
118 	u32 config_data[1];
119 } __packed;
120 
121 struct skl_dma_control {
122 	u32 node_id;
123 	u32 config_length;
124 	u32 config_data[];
125 } __packed;
126 
127 struct skl_cpr_cfg {
128 	struct skl_base_cfg base_cfg;
129 	struct skl_audio_data_format out_fmt;
130 	u32 cpr_feature_mask;
131 	struct skl_cpr_gtw_cfg gtw_cfg;
132 } __packed;
133 
134 struct skl_cpr_pin_fmt {
135 	u32 sink_id;
136 	struct skl_audio_data_format src_fmt;
137 	struct skl_audio_data_format dst_fmt;
138 } __packed;
139 
140 struct skl_src_module_cfg {
141 	struct skl_base_cfg base_cfg;
142 	enum skl_s_freq src_cfg;
143 } __packed;
144 
145 struct skl_up_down_mixer_cfg {
146 	struct skl_base_cfg base_cfg;
147 	enum skl_ch_cfg out_ch_cfg;
148 	/* This should be set to 1 if user coefficients are required */
149 	u32 coeff_sel;
150 	/* Pass the user coeff in this array */
151 	s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
152 	u32 ch_map;
153 } __packed;
154 
155 struct skl_pin_format {
156 	u32 pin_idx;
157 	u32 buf_size;
158 	struct skl_audio_data_format audio_fmt;
159 } __packed;
160 
161 struct skl_base_cfg_ext {
162 	u16 nr_input_pins;
163 	u16 nr_output_pins;
164 	u8 reserved[8];
165 	u32 priv_param_length;
166 	/* Input pin formats followed by output ones. */
167 	struct skl_pin_format pins_fmt[];
168 } __packed;
169 
170 struct skl_algo_cfg {
171 	struct skl_base_cfg  base_cfg;
172 	char params[];
173 } __packed;
174 
175 struct skl_base_outfmt_cfg {
176 	struct skl_base_cfg base_cfg;
177 	struct skl_audio_data_format out_fmt;
178 } __packed;
179 
180 enum skl_dma_type {
181 	SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
182 	SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
183 	SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
184 	SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
185 	SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
186 	SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
187 	SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
188 	SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
189 	SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
190 };
191 
192 union skl_ssp_dma_node {
193 	u8 val;
194 	struct {
195 		u8 time_slot_index:4;
196 		u8 i2s_instance:4;
197 	} dma_node;
198 };
199 
200 union skl_connector_node_id {
201 	u32 val;
202 	struct {
203 		u32 vindex:8;
204 		u32 dma_type:4;
205 		u32 rsvd:20;
206 	} node;
207 };
208 
209 struct skl_module_fmt {
210 	u32 channels;
211 	u32 s_freq;
212 	u32 bit_depth;
213 	u32 valid_bit_depth;
214 	u32 ch_cfg;
215 	u32 interleaving_style;
216 	u32 sample_type;
217 	u32 ch_map;
218 };
219 
220 struct skl_module_cfg;
221 
222 struct skl_mod_inst_map {
223 	u16 mod_id;
224 	u16 inst_id;
225 };
226 
227 struct skl_uuid_inst_map {
228 	u16 inst_id;
229 	u16 reserved;
230 	guid_t mod_uuid;
231 } __packed;
232 
233 struct skl_kpb_params {
234 	u32 num_modules;
235 	union {
236 		DECLARE_FLEX_ARRAY(struct skl_mod_inst_map, map);
237 		DECLARE_FLEX_ARRAY(struct skl_uuid_inst_map, map_uuid);
238 	} u;
239 };
240 
241 struct skl_module_inst_id {
242 	guid_t mod_uuid;
243 	int module_id;
244 	u32 instance_id;
245 	int pvt_id;
246 };
247 
248 enum skl_module_pin_state {
249 	SKL_PIN_UNBIND = 0,
250 	SKL_PIN_BIND_DONE = 1,
251 };
252 
253 struct skl_module_pin {
254 	struct skl_module_inst_id id;
255 	bool is_dynamic;
256 	bool in_use;
257 	enum skl_module_pin_state pin_state;
258 	struct skl_module_cfg *tgt_mcfg;
259 };
260 
261 struct skl_specific_cfg {
262 	u32 set_params;
263 	u32 param_id;
264 	u32 caps_size;
265 	u32 *caps;
266 };
267 
268 enum skl_pipe_state {
269 	SKL_PIPE_INVALID = 0,
270 	SKL_PIPE_CREATED = 1,
271 	SKL_PIPE_PAUSED = 2,
272 	SKL_PIPE_STARTED = 3,
273 	SKL_PIPE_RESET = 4
274 };
275 
276 struct skl_pipe_module {
277 	struct snd_soc_dapm_widget *w;
278 	struct list_head node;
279 };
280 
281 struct skl_pipe_params {
282 	u8 host_dma_id;
283 	u8 link_dma_id;
284 	u32 ch;
285 	u32 s_freq;
286 	u32 s_fmt;
287 	u32 s_cont;
288 	u8 linktype;
289 	snd_pcm_format_t format;
290 	int link_index;
291 	int stream;
292 	unsigned int host_bps;
293 	unsigned int link_bps;
294 };
295 
296 struct skl_pipe_fmt {
297 	u32 freq;
298 	u8 channels;
299 	u8 bps;
300 };
301 
302 struct skl_pipe_mcfg {
303 	u8 res_idx;
304 	u8 fmt_idx;
305 };
306 
307 struct skl_path_config {
308 	u8 mem_pages;
309 	struct skl_pipe_fmt in_fmt;
310 	struct skl_pipe_fmt out_fmt;
311 };
312 
313 struct skl_pipe {
314 	u8 ppl_id;
315 	u8 pipe_priority;
316 	u16 conn_type;
317 	u32 memory_pages;
318 	u8 lp_mode;
319 	struct skl_pipe_params *p_params;
320 	enum skl_pipe_state state;
321 	u8 direction;
322 	u8 cur_config_idx;
323 	u8 nr_cfgs;
324 	struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
325 	struct list_head w_list;
326 	bool passthru;
327 };
328 
329 enum skl_module_state {
330 	SKL_MODULE_UNINIT = 0,
331 	SKL_MODULE_INIT_DONE = 1,
332 	SKL_MODULE_BIND_DONE = 2,
333 };
334 
335 enum d0i3_capability {
336 	SKL_D0I3_NONE = 0,
337 	SKL_D0I3_STREAMING = 1,
338 	SKL_D0I3_NON_STREAMING = 2,
339 };
340 
341 struct skl_module_pin_fmt {
342 	u8 id;
343 	struct skl_module_fmt fmt;
344 };
345 
346 struct skl_module_iface {
347 	u8 fmt_idx;
348 	u8 nr_in_fmt;
349 	u8 nr_out_fmt;
350 	struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
351 	struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
352 };
353 
354 struct skl_module_pin_resources {
355 	u8 pin_index;
356 	u32 buf_size;
357 };
358 
359 struct skl_module_res {
360 	u8 id;
361 	u32 is_pages;
362 	u32 ibs;
363 	u32 obs;
364 	u32 dma_buffer_size;
365 	u32 cpc;
366 	u8 nr_input_pins;
367 	u8 nr_output_pins;
368 	struct skl_module_pin_resources input[MAX_IN_QUEUE];
369 	struct skl_module_pin_resources output[MAX_OUT_QUEUE];
370 };
371 
372 struct skl_module {
373 	guid_t uuid;
374 	u8 loadable;
375 	u8 input_pin_type;
376 	u8 output_pin_type;
377 	u8 max_input_pins;
378 	u8 max_output_pins;
379 	u8 nr_resources;
380 	u8 nr_interfaces;
381 	struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
382 	struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
383 };
384 
385 struct skl_module_cfg {
386 	u8 guid[16];
387 	struct skl_module_inst_id id;
388 	struct skl_module *module;
389 	int res_idx;
390 	int fmt_idx;
391 	int fmt_cfg_idx;
392 	u8 domain;
393 	bool homogenous_inputs;
394 	bool homogenous_outputs;
395 	struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
396 	struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
397 	u8 max_in_queue;
398 	u8 max_out_queue;
399 	u8 in_queue_mask;
400 	u8 out_queue_mask;
401 	u8 in_queue;
402 	u8 out_queue;
403 	u8 is_loadable;
404 	u8 core_id;
405 	u8 dev_type;
406 	u8 dma_id;
407 	u8 time_slot;
408 	u8 dmic_ch_combo_index;
409 	u32 dmic_ch_type;
410 	u32 params_fixup;
411 	u32 converter;
412 	u32 vbus_id;
413 	u32 mem_pages;
414 	enum d0i3_capability d0i3_caps;
415 	u32 dma_buffer_size; /* in milli seconds */
416 	struct skl_module_pin *m_in_pin;
417 	struct skl_module_pin *m_out_pin;
418 	enum skl_module_type m_type;
419 	enum skl_hw_conn_type  hw_conn_type;
420 	enum skl_module_state m_state;
421 	struct skl_pipe *pipe;
422 	struct skl_specific_cfg formats_config[SKL_MAX_PARAMS_TYPES];
423 	struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
424 };
425 
426 struct skl_algo_data {
427 	u32 param_id;
428 	u32 set_params;
429 	u32 max;
430 	u32 size;
431 	char *params;
432 };
433 
434 struct skl_pipeline {
435 	struct skl_pipe *pipe;
436 	struct list_head node;
437 };
438 
439 struct skl_module_deferred_bind {
440 	struct skl_module_cfg *src;
441 	struct skl_module_cfg *dst;
442 	struct list_head node;
443 };
444 
445 struct skl_mic_sel_config {
446 	u16 mic_switch;
447 	u16 flags;
448 	u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
449 } __packed;
450 
451 enum skl_channel {
452 	SKL_CH_MONO = 1,
453 	SKL_CH_STEREO = 2,
454 	SKL_CH_TRIO = 3,
455 	SKL_CH_QUATRO = 4,
456 };
457 
458 static inline struct skl_dev *get_skl_ctx(struct device *dev)
459 {
460 	struct hdac_bus *bus = dev_get_drvdata(dev);
461 
462 	return bus_to_skl(bus);
463 }
464 
465 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
466 	struct skl_pipe_params *params);
467 int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
468 			u32 caps_size, u32 node_id);
469 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
470 	struct skl_pipe_params *params, int stream);
471 int skl_tplg_init(struct snd_soc_component *component,
472 				struct hdac_bus *bus);
473 void skl_tplg_exit(struct snd_soc_component *component,
474 				struct hdac_bus *bus);
475 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
476 		struct snd_soc_dai *dai, int stream);
477 int skl_tplg_update_pipe_params(struct device *dev,
478 		struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
479 
480 void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps);
481 void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps);
482 
483 int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe);
484 
485 int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
486 
487 int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
488 
489 int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
490 
491 int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
492 
493 int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
494 
495 int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig);
496 
497 int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg
498 	*src_mcfg, struct skl_module_cfg *dst_mcfg);
499 
500 int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg
501 	*src_mcfg, struct skl_module_cfg *dst_mcfg);
502 
503 int skl_set_module_params(struct skl_dev *skl, u32 *params, int size,
504 			u32 param_id, struct skl_module_cfg *mcfg);
505 int skl_get_module_params(struct skl_dev *skl, u32 *params, int size,
506 			  u32 param_id, struct skl_module_cfg *mcfg);
507 
508 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
509 								int stream);
510 enum skl_bitdepth skl_get_bit_depth(int params);
511 int skl_pcm_host_dma_prepare(struct device *dev,
512 			struct skl_pipe_params *params);
513 int skl_pcm_link_dma_prepare(struct device *dev,
514 			struct skl_pipe_params *params);
515 
516 int skl_dai_load(struct snd_soc_component *cmp, int index,
517 		struct snd_soc_dai_driver *dai_drv,
518 		struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
519 void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl,
520 				struct snd_soc_dapm_widget *w);
521 #endif
522