1 /* 2 * skl_topology.h - Intel HDA Platform topology header file 3 * 4 * Copyright (C) 2014-15 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SKL_TOPOLOGY_H__ 22 #define __SKL_TOPOLOGY_H__ 23 24 #include <linux/types.h> 25 26 #include <sound/hdaudio_ext.h> 27 #include <sound/soc.h> 28 #include "skl.h" 29 #include "skl-tplg-interface.h" 30 31 #define BITS_PER_BYTE 8 32 #define MAX_TS_GROUPS 8 33 #define MAX_DMIC_TS_GROUPS 4 34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 35 36 /* Maximum number of coefficients up down mixer module */ 37 #define UP_DOWN_MIXER_MAX_COEFF 6 38 39 #define MODULE_MAX_IN_PINS 8 40 #define MODULE_MAX_OUT_PINS 8 41 42 #define SKL_MIC_CH_SUPPORT 4 43 #define SKL_MIC_MAX_CH_SUPPORT 8 44 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 45 #define SKL_MIC_SEL_SWITCH 0x3 46 47 enum skl_channel_index { 48 SKL_CHANNEL_LEFT = 0, 49 SKL_CHANNEL_RIGHT = 1, 50 SKL_CHANNEL_CENTER = 2, 51 SKL_CHANNEL_LEFT_SURROUND = 3, 52 SKL_CHANNEL_CENTER_SURROUND = 3, 53 SKL_CHANNEL_RIGHT_SURROUND = 4, 54 SKL_CHANNEL_LFE = 7, 55 SKL_CHANNEL_INVALID = 0xF, 56 }; 57 58 enum skl_bitdepth { 59 SKL_DEPTH_8BIT = 8, 60 SKL_DEPTH_16BIT = 16, 61 SKL_DEPTH_24BIT = 24, 62 SKL_DEPTH_32BIT = 32, 63 SKL_DEPTH_INVALID 64 }; 65 66 67 enum skl_s_freq { 68 SKL_FS_8000 = 8000, 69 SKL_FS_11025 = 11025, 70 SKL_FS_12000 = 12000, 71 SKL_FS_16000 = 16000, 72 SKL_FS_22050 = 22050, 73 SKL_FS_24000 = 24000, 74 SKL_FS_32000 = 32000, 75 SKL_FS_44100 = 44100, 76 SKL_FS_48000 = 48000, 77 SKL_FS_64000 = 64000, 78 SKL_FS_88200 = 88200, 79 SKL_FS_96000 = 96000, 80 SKL_FS_128000 = 128000, 81 SKL_FS_176400 = 176400, 82 SKL_FS_192000 = 192000, 83 SKL_FS_INVALID 84 }; 85 86 enum skl_widget_type { 87 SKL_WIDGET_VMIXER = 1, 88 SKL_WIDGET_MIXER = 2, 89 SKL_WIDGET_PGA = 3, 90 SKL_WIDGET_MUX = 4 91 }; 92 93 struct skl_audio_data_format { 94 enum skl_s_freq s_freq; 95 enum skl_bitdepth bit_depth; 96 u32 channel_map; 97 enum skl_ch_cfg ch_cfg; 98 enum skl_interleaving interleaving; 99 u8 number_of_channels; 100 u8 valid_bit_depth; 101 u8 sample_type; 102 u8 reserved[1]; 103 } __packed; 104 105 struct skl_base_cfg { 106 u32 cps; 107 u32 ibs; 108 u32 obs; 109 u32 is_pages; 110 struct skl_audio_data_format audio_fmt; 111 }; 112 113 struct skl_cpr_gtw_cfg { 114 u32 node_id; 115 u32 dma_buffer_size; 116 u32 config_length; 117 /* not mandatory; required only for DMIC/I2S */ 118 u32 config_data[1]; 119 } __packed; 120 121 struct skl_dma_control { 122 u32 node_id; 123 u32 config_length; 124 u32 config_data[0]; 125 } __packed; 126 127 struct skl_cpr_cfg { 128 struct skl_base_cfg base_cfg; 129 struct skl_audio_data_format out_fmt; 130 u32 cpr_feature_mask; 131 struct skl_cpr_gtw_cfg gtw_cfg; 132 } __packed; 133 134 135 struct skl_src_module_cfg { 136 struct skl_base_cfg base_cfg; 137 enum skl_s_freq src_cfg; 138 } __packed; 139 140 struct notification_mask { 141 u32 notify; 142 u32 enable; 143 } __packed; 144 145 struct skl_up_down_mixer_cfg { 146 struct skl_base_cfg base_cfg; 147 enum skl_ch_cfg out_ch_cfg; 148 /* This should be set to 1 if user coefficients are required */ 149 u32 coeff_sel; 150 /* Pass the user coeff in this array */ 151 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 152 } __packed; 153 154 struct skl_algo_cfg { 155 struct skl_base_cfg base_cfg; 156 char params[0]; 157 } __packed; 158 159 struct skl_base_outfmt_cfg { 160 struct skl_base_cfg base_cfg; 161 struct skl_audio_data_format out_fmt; 162 } __packed; 163 164 enum skl_dma_type { 165 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 166 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 167 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 168 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 169 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 170 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 171 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 172 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 173 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 174 }; 175 176 union skl_ssp_dma_node { 177 u8 val; 178 struct { 179 u8 time_slot_index:4; 180 u8 i2s_instance:4; 181 } dma_node; 182 }; 183 184 union skl_connector_node_id { 185 u32 val; 186 struct { 187 u32 vindex:8; 188 u32 dma_type:4; 189 u32 rsvd:20; 190 } node; 191 }; 192 193 struct skl_module_fmt { 194 u32 channels; 195 u32 s_freq; 196 u32 bit_depth; 197 u32 valid_bit_depth; 198 u32 ch_cfg; 199 u32 interleaving_style; 200 u32 sample_type; 201 u32 ch_map; 202 }; 203 204 struct skl_module_cfg; 205 206 struct skl_mod_inst_map { 207 u16 mod_id; 208 u16 inst_id; 209 }; 210 211 struct skl_kpb_params { 212 u32 num_modules; 213 struct skl_mod_inst_map map[0]; 214 }; 215 216 struct skl_module_inst_id { 217 int module_id; 218 u32 instance_id; 219 int pvt_id; 220 }; 221 222 enum skl_module_pin_state { 223 SKL_PIN_UNBIND = 0, 224 SKL_PIN_BIND_DONE = 1, 225 }; 226 227 struct skl_module_pin { 228 struct skl_module_inst_id id; 229 bool is_dynamic; 230 bool in_use; 231 enum skl_module_pin_state pin_state; 232 struct skl_module_cfg *tgt_mcfg; 233 }; 234 235 struct skl_specific_cfg { 236 u32 set_params; 237 u32 param_id; 238 u32 caps_size; 239 u32 *caps; 240 }; 241 242 enum skl_pipe_state { 243 SKL_PIPE_INVALID = 0, 244 SKL_PIPE_CREATED = 1, 245 SKL_PIPE_PAUSED = 2, 246 SKL_PIPE_STARTED = 3, 247 SKL_PIPE_RESET = 4 248 }; 249 250 struct skl_pipe_module { 251 struct snd_soc_dapm_widget *w; 252 struct list_head node; 253 }; 254 255 struct skl_pipe_params { 256 u8 host_dma_id; 257 u8 link_dma_id; 258 u32 ch; 259 u32 s_freq; 260 u32 s_fmt; 261 u8 linktype; 262 snd_pcm_format_t format; 263 int link_index; 264 int stream; 265 unsigned int host_bps; 266 unsigned int link_bps; 267 }; 268 269 struct skl_pipe { 270 u8 ppl_id; 271 u8 pipe_priority; 272 u16 conn_type; 273 u32 memory_pages; 274 u8 lp_mode; 275 struct skl_pipe_params *p_params; 276 enum skl_pipe_state state; 277 struct list_head w_list; 278 bool passthru; 279 }; 280 281 enum skl_module_state { 282 SKL_MODULE_UNINIT = 0, 283 SKL_MODULE_LOADED = 1, 284 SKL_MODULE_INIT_DONE = 2, 285 SKL_MODULE_BIND_DONE = 3, 286 SKL_MODULE_UNLOADED = 4, 287 }; 288 289 enum d0i3_capability { 290 SKL_D0I3_NONE = 0, 291 SKL_D0I3_STREAMING = 1, 292 SKL_D0I3_NON_STREAMING = 2, 293 }; 294 295 struct skl_module_cfg { 296 u8 guid[16]; 297 struct skl_module_inst_id id; 298 u8 domain; 299 bool homogenous_inputs; 300 bool homogenous_outputs; 301 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 302 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 303 u8 max_in_queue; 304 u8 max_out_queue; 305 u8 in_queue_mask; 306 u8 out_queue_mask; 307 u8 in_queue; 308 u8 out_queue; 309 u32 mcps; 310 u32 ibs; 311 u32 obs; 312 u8 is_loadable; 313 u8 core_id; 314 u8 dev_type; 315 u8 dma_id; 316 u8 time_slot; 317 u8 dmic_ch_combo_index; 318 u32 dmic_ch_type; 319 u32 params_fixup; 320 u32 converter; 321 u32 vbus_id; 322 u32 mem_pages; 323 enum d0i3_capability d0i3_caps; 324 u32 dma_buffer_size; /* in milli seconds */ 325 struct skl_module_pin *m_in_pin; 326 struct skl_module_pin *m_out_pin; 327 enum skl_module_type m_type; 328 enum skl_hw_conn_type hw_conn_type; 329 enum skl_module_state m_state; 330 struct skl_pipe *pipe; 331 struct skl_specific_cfg formats_config; 332 }; 333 334 struct skl_algo_data { 335 u32 param_id; 336 u32 set_params; 337 u32 max; 338 u32 size; 339 char *params; 340 }; 341 342 struct skl_pipeline { 343 struct skl_pipe *pipe; 344 struct list_head node; 345 }; 346 347 struct skl_module_deferred_bind { 348 struct skl_module_cfg *src; 349 struct skl_module_cfg *dst; 350 struct list_head node; 351 }; 352 353 struct skl_mic_sel_config { 354 u16 mic_switch; 355 u16 flags; 356 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 357 } __packed; 358 359 enum skl_channel { 360 SKL_CH_MONO = 1, 361 SKL_CH_STEREO = 2, 362 SKL_CH_TRIO = 3, 363 SKL_CH_QUATRO = 4, 364 }; 365 366 static inline struct skl *get_skl_ctx(struct device *dev) 367 { 368 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 369 370 return ebus_to_skl(ebus); 371 } 372 373 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 374 struct skl_pipe_params *params); 375 int skl_dsp_set_dma_control(struct skl_sst *ctx, 376 struct skl_module_cfg *mconfig); 377 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 378 struct skl_pipe_params *params, int stream); 379 int skl_tplg_init(struct snd_soc_platform *platform, 380 struct hdac_ext_bus *ebus); 381 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 382 struct snd_soc_dai *dai, int stream); 383 int skl_tplg_update_pipe_params(struct device *dev, 384 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 385 386 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps); 387 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps); 388 389 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 390 391 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 392 393 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 394 395 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 396 397 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 398 399 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 400 401 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 402 403 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 404 *src_module, struct skl_module_cfg *dst_module); 405 406 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 407 *src_module, struct skl_module_cfg *dst_module); 408 409 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 410 u32 param_id, struct skl_module_cfg *mcfg); 411 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 412 u32 param_id, struct skl_module_cfg *mcfg); 413 414 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 415 int stream); 416 enum skl_bitdepth skl_get_bit_depth(int params); 417 int skl_pcm_host_dma_prepare(struct device *dev, 418 struct skl_pipe_params *params); 419 int skl_pcm_link_dma_prepare(struct device *dev, 420 struct skl_pipe_params *params); 421 #endif 422