1 /* 2 * skl_topology.h - Intel HDA Platform topology header file 3 * 4 * Copyright (C) 2014-15 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SKL_TOPOLOGY_H__ 22 #define __SKL_TOPOLOGY_H__ 23 24 #include <linux/types.h> 25 26 #include <sound/hdaudio_ext.h> 27 #include <sound/soc.h> 28 #include "skl.h" 29 #include "skl-tplg-interface.h" 30 31 #define BITS_PER_BYTE 8 32 #define MAX_TS_GROUPS 8 33 #define MAX_DMIC_TS_GROUPS 4 34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727 35 36 /* Maximum number of coefficients up down mixer module */ 37 #define UP_DOWN_MIXER_MAX_COEFF 6 38 39 #define MODULE_MAX_IN_PINS 8 40 #define MODULE_MAX_OUT_PINS 8 41 42 enum skl_channel_index { 43 SKL_CHANNEL_LEFT = 0, 44 SKL_CHANNEL_RIGHT = 1, 45 SKL_CHANNEL_CENTER = 2, 46 SKL_CHANNEL_LEFT_SURROUND = 3, 47 SKL_CHANNEL_CENTER_SURROUND = 3, 48 SKL_CHANNEL_RIGHT_SURROUND = 4, 49 SKL_CHANNEL_LFE = 7, 50 SKL_CHANNEL_INVALID = 0xF, 51 }; 52 53 enum skl_bitdepth { 54 SKL_DEPTH_8BIT = 8, 55 SKL_DEPTH_16BIT = 16, 56 SKL_DEPTH_24BIT = 24, 57 SKL_DEPTH_32BIT = 32, 58 SKL_DEPTH_INVALID 59 }; 60 61 62 enum skl_s_freq { 63 SKL_FS_8000 = 8000, 64 SKL_FS_11025 = 11025, 65 SKL_FS_12000 = 12000, 66 SKL_FS_16000 = 16000, 67 SKL_FS_22050 = 22050, 68 SKL_FS_24000 = 24000, 69 SKL_FS_32000 = 32000, 70 SKL_FS_44100 = 44100, 71 SKL_FS_48000 = 48000, 72 SKL_FS_64000 = 64000, 73 SKL_FS_88200 = 88200, 74 SKL_FS_96000 = 96000, 75 SKL_FS_128000 = 128000, 76 SKL_FS_176400 = 176400, 77 SKL_FS_192000 = 192000, 78 SKL_FS_INVALID 79 }; 80 81 enum skl_widget_type { 82 SKL_WIDGET_VMIXER = 1, 83 SKL_WIDGET_MIXER = 2, 84 SKL_WIDGET_PGA = 3, 85 SKL_WIDGET_MUX = 4 86 }; 87 88 struct skl_audio_data_format { 89 enum skl_s_freq s_freq; 90 enum skl_bitdepth bit_depth; 91 u32 channel_map; 92 enum skl_ch_cfg ch_cfg; 93 enum skl_interleaving interleaving; 94 u8 number_of_channels; 95 u8 valid_bit_depth; 96 u8 sample_type; 97 u8 reserved[1]; 98 } __packed; 99 100 struct skl_base_cfg { 101 u32 cps; 102 u32 ibs; 103 u32 obs; 104 u32 is_pages; 105 struct skl_audio_data_format audio_fmt; 106 }; 107 108 struct skl_cpr_gtw_cfg { 109 u32 node_id; 110 u32 dma_buffer_size; 111 u32 config_length; 112 /* not mandatory; required only for DMIC/I2S */ 113 u32 config_data[1]; 114 } __packed; 115 116 struct skl_i2s_config_blob { 117 u32 gateway_attrib; 118 u32 tdm_ts_group[8]; 119 u32 ssc0; 120 u32 ssc1; 121 u32 sscto; 122 u32 sspsp; 123 u32 sstsa; 124 u32 ssrsa; 125 u32 ssc2; 126 u32 sspsp2; 127 u32 ssc3; 128 u32 ssioc; 129 u32 mdivc; 130 u32 mdivr; 131 } __packed; 132 133 struct skl_dma_control { 134 u32 node_id; 135 u32 config_length; 136 u32 config_data[1]; 137 } __packed; 138 139 struct skl_cpr_cfg { 140 struct skl_base_cfg base_cfg; 141 struct skl_audio_data_format out_fmt; 142 u32 cpr_feature_mask; 143 struct skl_cpr_gtw_cfg gtw_cfg; 144 } __packed; 145 146 147 struct skl_src_module_cfg { 148 struct skl_base_cfg base_cfg; 149 enum skl_s_freq src_cfg; 150 } __packed; 151 152 struct notification_mask { 153 u32 notify; 154 u32 enable; 155 } __packed; 156 157 struct skl_up_down_mixer_cfg { 158 struct skl_base_cfg base_cfg; 159 enum skl_ch_cfg out_ch_cfg; 160 /* This should be set to 1 if user coefficients are required */ 161 u32 coeff_sel; 162 /* Pass the user coeff in this array */ 163 s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 164 } __packed; 165 166 struct skl_algo_cfg { 167 struct skl_base_cfg base_cfg; 168 char params[0]; 169 } __packed; 170 171 struct skl_base_outfmt_cfg { 172 struct skl_base_cfg base_cfg; 173 struct skl_audio_data_format out_fmt; 174 } __packed; 175 176 enum skl_dma_type { 177 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 178 SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 179 SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 180 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 181 SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 182 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 183 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 184 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 185 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 186 }; 187 188 union skl_ssp_dma_node { 189 u8 val; 190 struct { 191 u8 time_slot_index:4; 192 u8 i2s_instance:4; 193 } dma_node; 194 }; 195 196 union skl_connector_node_id { 197 u32 val; 198 struct { 199 u32 vindex:8; 200 u32 dma_type:4; 201 u32 rsvd:20; 202 } node; 203 }; 204 205 struct skl_module_fmt { 206 u32 channels; 207 u32 s_freq; 208 u32 bit_depth; 209 u32 valid_bit_depth; 210 u32 ch_cfg; 211 u32 interleaving_style; 212 u32 sample_type; 213 u32 ch_map; 214 }; 215 216 struct skl_module_cfg; 217 218 struct skl_module_inst_id { 219 u32 module_id; 220 u32 instance_id; 221 }; 222 223 enum skl_module_pin_state { 224 SKL_PIN_UNBIND = 0, 225 SKL_PIN_BIND_DONE = 1, 226 }; 227 228 struct skl_module_pin { 229 struct skl_module_inst_id id; 230 bool is_dynamic; 231 bool in_use; 232 enum skl_module_pin_state pin_state; 233 struct skl_module_cfg *tgt_mcfg; 234 }; 235 236 struct skl_specific_cfg { 237 u32 set_params; 238 u32 param_id; 239 u32 caps_size; 240 u32 *caps; 241 }; 242 243 enum skl_pipe_state { 244 SKL_PIPE_INVALID = 0, 245 SKL_PIPE_CREATED = 1, 246 SKL_PIPE_PAUSED = 2, 247 SKL_PIPE_STARTED = 3, 248 SKL_PIPE_RESET = 4 249 }; 250 251 struct skl_pipe_module { 252 struct snd_soc_dapm_widget *w; 253 struct list_head node; 254 }; 255 256 struct skl_pipe_params { 257 u8 host_dma_id; 258 u8 link_dma_id; 259 u32 ch; 260 u32 s_freq; 261 u32 s_fmt; 262 u8 linktype; 263 int stream; 264 }; 265 266 struct skl_pipe { 267 u8 ppl_id; 268 u8 pipe_priority; 269 u16 conn_type; 270 u32 memory_pages; 271 struct skl_pipe_params *p_params; 272 enum skl_pipe_state state; 273 struct list_head w_list; 274 }; 275 276 enum skl_module_state { 277 SKL_MODULE_UNINIT = 0, 278 SKL_MODULE_LOADED = 1, 279 SKL_MODULE_INIT_DONE = 2, 280 SKL_MODULE_BIND_DONE = 3, 281 SKL_MODULE_UNLOADED = 4, 282 }; 283 284 struct skl_module_cfg { 285 u8 guid[16]; 286 struct skl_module_inst_id id; 287 u8 domain; 288 bool homogenous_inputs; 289 bool homogenous_outputs; 290 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 291 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 292 u8 max_in_queue; 293 u8 max_out_queue; 294 u8 in_queue_mask; 295 u8 out_queue_mask; 296 u8 in_queue; 297 u8 out_queue; 298 u32 mcps; 299 u32 ibs; 300 u32 obs; 301 u8 is_loadable; 302 u8 core_id; 303 u8 dev_type; 304 u8 dma_id; 305 u8 time_slot; 306 u32 params_fixup; 307 u32 converter; 308 u32 vbus_id; 309 u32 mem_pages; 310 struct skl_module_pin *m_in_pin; 311 struct skl_module_pin *m_out_pin; 312 enum skl_module_type m_type; 313 enum skl_hw_conn_type hw_conn_type; 314 enum skl_module_state m_state; 315 struct skl_pipe *pipe; 316 struct skl_specific_cfg formats_config; 317 }; 318 319 struct skl_algo_data { 320 u32 param_id; 321 u32 set_params; 322 u32 max; 323 char *params; 324 }; 325 326 struct skl_pipeline { 327 struct skl_pipe *pipe; 328 struct list_head node; 329 }; 330 331 static inline struct skl *get_skl_ctx(struct device *dev) 332 { 333 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 334 335 return ebus_to_skl(ebus); 336 } 337 338 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 339 struct skl_pipe_params *params); 340 int skl_dsp_set_dma_control(struct skl_sst *ctx, 341 struct skl_module_cfg *mconfig); 342 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 343 struct skl_pipe_params *params, int stream); 344 int skl_tplg_init(struct snd_soc_platform *platform, 345 struct hdac_ext_bus *ebus); 346 struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 347 struct snd_soc_dai *dai, int stream); 348 int skl_tplg_update_pipe_params(struct device *dev, 349 struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 350 351 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 352 353 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 354 355 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 356 357 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 358 359 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 360 361 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 362 363 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 364 365 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 366 *src_module, struct skl_module_cfg *dst_module); 367 368 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 369 *src_module, struct skl_module_cfg *dst_module); 370 371 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 372 u32 param_id, struct skl_module_cfg *mcfg); 373 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 374 u32 param_id, struct skl_module_cfg *mcfg); 375 376 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 377 int stream); 378 enum skl_bitdepth skl_get_bit_depth(int params); 379 #endif 380