18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 223db472bSJeeja KP /* 323db472bSJeeja KP * skl_topology.h - Intel HDA Platform topology header file 423db472bSJeeja KP * 523db472bSJeeja KP * Copyright (C) 2014-15 Intel Corp 623db472bSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com> 723db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 823db472bSJeeja KP * 923db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1023db472bSJeeja KP */ 1123db472bSJeeja KP 1223db472bSJeeja KP #ifndef __SKL_TOPOLOGY_H__ 1323db472bSJeeja KP #define __SKL_TOPOLOGY_H__ 1423db472bSJeeja KP 1523db472bSJeeja KP #include <linux/types.h> 1623db472bSJeeja KP 1723db472bSJeeja KP #include <sound/hdaudio_ext.h> 1823db472bSJeeja KP #include <sound/soc.h> 190c24fdc0SGuenter Roeck #include <uapi/sound/skl-tplg-interface.h> 2023db472bSJeeja KP #include "skl.h" 2123db472bSJeeja KP 2223db472bSJeeja KP #define BITS_PER_BYTE 8 2323db472bSJeeja KP #define MAX_TS_GROUPS 8 2423db472bSJeeja KP #define MAX_DMIC_TS_GROUPS 4 2523db472bSJeeja KP #define MAX_FIXED_DMIC_PARAMS_SIZE 727 2623db472bSJeeja KP 2723db472bSJeeja KP /* Maximum number of coefficients up down mixer module */ 283e1b96c8SGuneshwor Singh #define UP_DOWN_MIXER_MAX_COEFF 8 2923db472bSJeeja KP 304cd9899fSHardik T Shah #define MODULE_MAX_IN_PINS 8 314cd9899fSHardik T Shah #define MODULE_MAX_OUT_PINS 8 324cd9899fSHardik T Shah 337a1b749bSDharageswari R #define SKL_MIC_CH_SUPPORT 4 347a1b749bSDharageswari R #define SKL_MIC_MAX_CH_SUPPORT 8 357a1b749bSDharageswari R #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 367a1b749bSDharageswari R #define SKL_MIC_SEL_SWITCH 0x3 377a1b749bSDharageswari R 38822c3b04SShreyas NC #define SKL_OUTPUT_PIN 0 39822c3b04SShreyas NC #define SKL_INPUT_PIN 1 40822c3b04SShreyas NC #define SKL_MAX_PATH_CONFIGS 8 41822c3b04SShreyas NC #define SKL_MAX_MODULES_IN_PIPE 8 42822c3b04SShreyas NC #define SKL_MAX_MODULE_FORMATS 32 43822c3b04SShreyas NC #define SKL_MAX_MODULE_RESOURCES 32 44822c3b04SShreyas NC 4523db472bSJeeja KP enum skl_channel_index { 4623db472bSJeeja KP SKL_CHANNEL_LEFT = 0, 4723db472bSJeeja KP SKL_CHANNEL_RIGHT = 1, 4823db472bSJeeja KP SKL_CHANNEL_CENTER = 2, 4923db472bSJeeja KP SKL_CHANNEL_LEFT_SURROUND = 3, 5023db472bSJeeja KP SKL_CHANNEL_CENTER_SURROUND = 3, 5123db472bSJeeja KP SKL_CHANNEL_RIGHT_SURROUND = 4, 5223db472bSJeeja KP SKL_CHANNEL_LFE = 7, 5323db472bSJeeja KP SKL_CHANNEL_INVALID = 0xF, 5423db472bSJeeja KP }; 5523db472bSJeeja KP 5623db472bSJeeja KP enum skl_bitdepth { 5723db472bSJeeja KP SKL_DEPTH_8BIT = 8, 5823db472bSJeeja KP SKL_DEPTH_16BIT = 16, 5923db472bSJeeja KP SKL_DEPTH_24BIT = 24, 6023db472bSJeeja KP SKL_DEPTH_32BIT = 32, 6123db472bSJeeja KP SKL_DEPTH_INVALID 6223db472bSJeeja KP }; 6323db472bSJeeja KP 6423db472bSJeeja KP 6523db472bSJeeja KP enum skl_s_freq { 6623db472bSJeeja KP SKL_FS_8000 = 8000, 6723db472bSJeeja KP SKL_FS_11025 = 11025, 6823db472bSJeeja KP SKL_FS_12000 = 12000, 6923db472bSJeeja KP SKL_FS_16000 = 16000, 7023db472bSJeeja KP SKL_FS_22050 = 22050, 7123db472bSJeeja KP SKL_FS_24000 = 24000, 7223db472bSJeeja KP SKL_FS_32000 = 32000, 7323db472bSJeeja KP SKL_FS_44100 = 44100, 7423db472bSJeeja KP SKL_FS_48000 = 48000, 7523db472bSJeeja KP SKL_FS_64000 = 64000, 7623db472bSJeeja KP SKL_FS_88200 = 88200, 7723db472bSJeeja KP SKL_FS_96000 = 96000, 7823db472bSJeeja KP SKL_FS_128000 = 128000, 7923db472bSJeeja KP SKL_FS_176400 = 176400, 8023db472bSJeeja KP SKL_FS_192000 = 192000, 8123db472bSJeeja KP SKL_FS_INVALID 8223db472bSJeeja KP }; 8323db472bSJeeja KP 8423db472bSJeeja KP enum skl_widget_type { 8523db472bSJeeja KP SKL_WIDGET_VMIXER = 1, 8623db472bSJeeja KP SKL_WIDGET_MIXER = 2, 8723db472bSJeeja KP SKL_WIDGET_PGA = 3, 8823db472bSJeeja KP SKL_WIDGET_MUX = 4 8923db472bSJeeja KP }; 9023db472bSJeeja KP 9123db472bSJeeja KP struct skl_audio_data_format { 9223db472bSJeeja KP enum skl_s_freq s_freq; 9323db472bSJeeja KP enum skl_bitdepth bit_depth; 9423db472bSJeeja KP u32 channel_map; 9523db472bSJeeja KP enum skl_ch_cfg ch_cfg; 9623db472bSJeeja KP enum skl_interleaving interleaving; 9723db472bSJeeja KP u8 number_of_channels; 9823db472bSJeeja KP u8 valid_bit_depth; 9923db472bSJeeja KP u8 sample_type; 10023db472bSJeeja KP u8 reserved[1]; 10123db472bSJeeja KP } __packed; 10223db472bSJeeja KP 10323db472bSJeeja KP struct skl_base_cfg { 10423db472bSJeeja KP u32 cps; 10523db472bSJeeja KP u32 ibs; 10623db472bSJeeja KP u32 obs; 10723db472bSJeeja KP u32 is_pages; 10823db472bSJeeja KP struct skl_audio_data_format audio_fmt; 10923db472bSJeeja KP }; 11023db472bSJeeja KP 11123db472bSJeeja KP struct skl_cpr_gtw_cfg { 11223db472bSJeeja KP u32 node_id; 11323db472bSJeeja KP u32 dma_buffer_size; 11423db472bSJeeja KP u32 config_length; 11523db472bSJeeja KP /* not mandatory; required only for DMIC/I2S */ 11623db472bSJeeja KP u32 config_data[1]; 11723db472bSJeeja KP } __packed; 11823db472bSJeeja KP 119c115fa5eSDharageswari.R struct skl_dma_control { 120c115fa5eSDharageswari.R u32 node_id; 121c115fa5eSDharageswari.R u32 config_length; 1220b6d76bbSJeeja KP u32 config_data[0]; 123c115fa5eSDharageswari.R } __packed; 124c115fa5eSDharageswari.R 12523db472bSJeeja KP struct skl_cpr_cfg { 12623db472bSJeeja KP struct skl_base_cfg base_cfg; 12723db472bSJeeja KP struct skl_audio_data_format out_fmt; 12823db472bSJeeja KP u32 cpr_feature_mask; 12923db472bSJeeja KP struct skl_cpr_gtw_cfg gtw_cfg; 13023db472bSJeeja KP } __packed; 13123db472bSJeeja KP 13238a77085SPradeep Tewani struct skl_cpr_pin_fmt { 13338a77085SPradeep Tewani u32 sink_id; 13438a77085SPradeep Tewani struct skl_audio_data_format src_fmt; 13538a77085SPradeep Tewani struct skl_audio_data_format dst_fmt; 13638a77085SPradeep Tewani } __packed; 137a0ffe48bSHardik T Shah 138a0ffe48bSHardik T Shah struct skl_src_module_cfg { 139a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 140a0ffe48bSHardik T Shah enum skl_s_freq src_cfg; 141a0ffe48bSHardik T Shah } __packed; 142a0ffe48bSHardik T Shah 1434e10996bSJeeja KP struct notification_mask { 1444e10996bSJeeja KP u32 notify; 1454e10996bSJeeja KP u32 enable; 1464e10996bSJeeja KP } __packed; 1474e10996bSJeeja KP 148a0ffe48bSHardik T Shah struct skl_up_down_mixer_cfg { 149a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 150a0ffe48bSHardik T Shah enum skl_ch_cfg out_ch_cfg; 151a0ffe48bSHardik T Shah /* This should be set to 1 if user coefficients are required */ 152a0ffe48bSHardik T Shah u32 coeff_sel; 153a0ffe48bSHardik T Shah /* Pass the user coeff in this array */ 154a0ffe48bSHardik T Shah s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 155da3417feSGuneshwor Singh u32 ch_map; 156a0ffe48bSHardik T Shah } __packed; 157a0ffe48bSHardik T Shah 158399b210bSJeeja KP struct skl_algo_cfg { 159399b210bSJeeja KP struct skl_base_cfg base_cfg; 160399b210bSJeeja KP char params[0]; 161399b210bSJeeja KP } __packed; 162399b210bSJeeja KP 163fd18110fSDharageswari R struct skl_base_outfmt_cfg { 164fd18110fSDharageswari R struct skl_base_cfg base_cfg; 165fd18110fSDharageswari R struct skl_audio_data_format out_fmt; 166fd18110fSDharageswari R } __packed; 167fd18110fSDharageswari R 16823db472bSJeeja KP enum skl_dma_type { 16923db472bSJeeja KP SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 17023db472bSJeeja KP SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 17123db472bSJeeja KP SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 17223db472bSJeeja KP SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 17323db472bSJeeja KP SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 17423db472bSJeeja KP SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 17523db472bSJeeja KP SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 17623db472bSJeeja KP SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 17723db472bSJeeja KP SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 17823db472bSJeeja KP }; 17923db472bSJeeja KP 18023db472bSJeeja KP union skl_ssp_dma_node { 18123db472bSJeeja KP u8 val; 18223db472bSJeeja KP struct { 183d7b18813SJeeja KP u8 time_slot_index:4; 18423db472bSJeeja KP u8 i2s_instance:4; 18523db472bSJeeja KP } dma_node; 18623db472bSJeeja KP }; 18723db472bSJeeja KP 18823db472bSJeeja KP union skl_connector_node_id { 18923db472bSJeeja KP u32 val; 19023db472bSJeeja KP struct { 19123db472bSJeeja KP u32 vindex:8; 19223db472bSJeeja KP u32 dma_type:4; 19323db472bSJeeja KP u32 rsvd:20; 19423db472bSJeeja KP } node; 19523db472bSJeeja KP }; 19623db472bSJeeja KP 19723db472bSJeeja KP struct skl_module_fmt { 19823db472bSJeeja KP u32 channels; 19923db472bSJeeja KP u32 s_freq; 20023db472bSJeeja KP u32 bit_depth; 20123db472bSJeeja KP u32 valid_bit_depth; 20223db472bSJeeja KP u32 ch_cfg; 2034cd9899fSHardik T Shah u32 interleaving_style; 2044cd9899fSHardik T Shah u32 sample_type; 2054cd9899fSHardik T Shah u32 ch_map; 20623db472bSJeeja KP }; 20723db472bSJeeja KP 2084f745708SJeeja KP struct skl_module_cfg; 2094f745708SJeeja KP 2105e8f0ee4SDharageswari R struct skl_mod_inst_map { 2115e8f0ee4SDharageswari R u16 mod_id; 2125e8f0ee4SDharageswari R u16 inst_id; 2135e8f0ee4SDharageswari R }; 2145e8f0ee4SDharageswari R 21524ada035SMark Brown struct skl_uuid_inst_map { 21624ada035SMark Brown u16 inst_id; 21724ada035SMark Brown u16 reserved; 2189e0784d0SAndy Shevchenko guid_t mod_uuid; 21924ada035SMark Brown } __packed; 22024ada035SMark Brown 2215e8f0ee4SDharageswari R struct skl_kpb_params { 2225e8f0ee4SDharageswari R u32 num_modules; 22324ada035SMark Brown union { 2245e8f0ee4SDharageswari R struct skl_mod_inst_map map[0]; 22524ada035SMark Brown struct skl_uuid_inst_map map_uuid[0]; 22624ada035SMark Brown } u; 2275e8f0ee4SDharageswari R }; 2285e8f0ee4SDharageswari R 22923db472bSJeeja KP struct skl_module_inst_id { 2309e0784d0SAndy Shevchenko guid_t mod_uuid; 231b7c50555SVinod Koul int module_id; 23223db472bSJeeja KP u32 instance_id; 233700a9a63SDharageswari R int pvt_id; 23423db472bSJeeja KP }; 23523db472bSJeeja KP 2364f745708SJeeja KP enum skl_module_pin_state { 2374f745708SJeeja KP SKL_PIN_UNBIND = 0, 2384f745708SJeeja KP SKL_PIN_BIND_DONE = 1, 2394f745708SJeeja KP }; 2404f745708SJeeja KP 24123db472bSJeeja KP struct skl_module_pin { 24223db472bSJeeja KP struct skl_module_inst_id id; 24323db472bSJeeja KP bool is_dynamic; 24423db472bSJeeja KP bool in_use; 2454f745708SJeeja KP enum skl_module_pin_state pin_state; 2464f745708SJeeja KP struct skl_module_cfg *tgt_mcfg; 24723db472bSJeeja KP }; 24823db472bSJeeja KP 24923db472bSJeeja KP struct skl_specific_cfg { 2504ced1827SJeeja KP u32 set_params; 251abb74003SJeeja KP u32 param_id; 25223db472bSJeeja KP u32 caps_size; 25323db472bSJeeja KP u32 *caps; 25423db472bSJeeja KP }; 25523db472bSJeeja KP 25623db472bSJeeja KP enum skl_pipe_state { 25723db472bSJeeja KP SKL_PIPE_INVALID = 0, 25823db472bSJeeja KP SKL_PIPE_CREATED = 1, 25923db472bSJeeja KP SKL_PIPE_PAUSED = 2, 2602004432fSJeeja KP SKL_PIPE_STARTED = 3, 2612004432fSJeeja KP SKL_PIPE_RESET = 4 26223db472bSJeeja KP }; 26323db472bSJeeja KP 26423db472bSJeeja KP struct skl_pipe_module { 26523db472bSJeeja KP struct snd_soc_dapm_widget *w; 26623db472bSJeeja KP struct list_head node; 26723db472bSJeeja KP }; 26823db472bSJeeja KP 26923db472bSJeeja KP struct skl_pipe_params { 27023db472bSJeeja KP u8 host_dma_id; 27123db472bSJeeja KP u8 link_dma_id; 27223db472bSJeeja KP u32 ch; 27323db472bSJeeja KP u32 s_freq; 27423db472bSJeeja KP u32 s_fmt; 27523db472bSJeeja KP u8 linktype; 27612c3be0eSJeeja KP snd_pcm_format_t format; 27712c3be0eSJeeja KP int link_index; 27823db472bSJeeja KP int stream; 2797f975a38SJeeja KP unsigned int host_bps; 2807f975a38SJeeja KP unsigned int link_bps; 28123db472bSJeeja KP }; 28223db472bSJeeja KP 283f6fa56e2SRamesh Babu struct skl_pipe_fmt { 284f6fa56e2SRamesh Babu u32 freq; 285f6fa56e2SRamesh Babu u8 channels; 286f6fa56e2SRamesh Babu u8 bps; 287f6fa56e2SRamesh Babu }; 288f6fa56e2SRamesh Babu 289f6fa56e2SRamesh Babu struct skl_pipe_mcfg { 290f6fa56e2SRamesh Babu u8 res_idx; 291f6fa56e2SRamesh Babu u8 fmt_idx; 292f6fa56e2SRamesh Babu }; 293f6fa56e2SRamesh Babu 294f6fa56e2SRamesh Babu struct skl_path_config { 295f6fa56e2SRamesh Babu u8 mem_pages; 296f6fa56e2SRamesh Babu struct skl_pipe_fmt in_fmt; 297f6fa56e2SRamesh Babu struct skl_pipe_fmt out_fmt; 298f6fa56e2SRamesh Babu }; 299f6fa56e2SRamesh Babu 30023db472bSJeeja KP struct skl_pipe { 30123db472bSJeeja KP u8 ppl_id; 30223db472bSJeeja KP u8 pipe_priority; 30323db472bSJeeja KP u16 conn_type; 30423db472bSJeeja KP u32 memory_pages; 3058a0cb236SVinod Koul u8 lp_mode; 30623db472bSJeeja KP struct skl_pipe_params *p_params; 30723db472bSJeeja KP enum skl_pipe_state state; 308f6fa56e2SRamesh Babu u8 direction; 309f6fa56e2SRamesh Babu u8 cur_config_idx; 310f6fa56e2SRamesh Babu u8 nr_cfgs; 311f6fa56e2SRamesh Babu struct skl_path_config configs[SKL_MAX_PATH_CONFIGS]; 31223db472bSJeeja KP struct list_head w_list; 313f0aa94faSJeeja KP bool passthru; 31423db472bSJeeja KP }; 31523db472bSJeeja KP 31623db472bSJeeja KP enum skl_module_state { 31723db472bSJeeja KP SKL_MODULE_UNINIT = 0, 318d643678bSJeeja KP SKL_MODULE_LOADED = 1, 319d643678bSJeeja KP SKL_MODULE_INIT_DONE = 2, 320d643678bSJeeja KP SKL_MODULE_BIND_DONE = 3, 321d643678bSJeeja KP SKL_MODULE_UNLOADED = 4, 32223db472bSJeeja KP }; 32323db472bSJeeja KP 3246bd9dcf3SVinod Koul enum d0i3_capability { 3256bd9dcf3SVinod Koul SKL_D0I3_NONE = 0, 3266bd9dcf3SVinod Koul SKL_D0I3_STREAMING = 1, 3276bd9dcf3SVinod Koul SKL_D0I3_NON_STREAMING = 2, 3286bd9dcf3SVinod Koul }; 3296bd9dcf3SVinod Koul 330822c3b04SShreyas NC struct skl_module_pin_fmt { 331822c3b04SShreyas NC u8 id; 332822c3b04SShreyas NC struct skl_module_fmt fmt; 333822c3b04SShreyas NC }; 334822c3b04SShreyas NC 335822c3b04SShreyas NC struct skl_module_iface { 336822c3b04SShreyas NC u8 fmt_idx; 337822c3b04SShreyas NC u8 nr_in_fmt; 338822c3b04SShreyas NC u8 nr_out_fmt; 339822c3b04SShreyas NC struct skl_module_pin_fmt inputs[MAX_IN_QUEUE]; 340822c3b04SShreyas NC struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE]; 341822c3b04SShreyas NC }; 342822c3b04SShreyas NC 343822c3b04SShreyas NC struct skl_module_pin_resources { 344822c3b04SShreyas NC u8 pin_index; 345822c3b04SShreyas NC u32 buf_size; 346822c3b04SShreyas NC }; 347822c3b04SShreyas NC 348822c3b04SShreyas NC struct skl_module_res { 349822c3b04SShreyas NC u8 id; 350822c3b04SShreyas NC u32 is_pages; 351822c3b04SShreyas NC u32 cps; 352822c3b04SShreyas NC u32 ibs; 353822c3b04SShreyas NC u32 obs; 354822c3b04SShreyas NC u32 dma_buffer_size; 355822c3b04SShreyas NC u32 cpc; 356822c3b04SShreyas NC u8 nr_input_pins; 357822c3b04SShreyas NC u8 nr_output_pins; 358822c3b04SShreyas NC struct skl_module_pin_resources input[MAX_IN_QUEUE]; 359822c3b04SShreyas NC struct skl_module_pin_resources output[MAX_OUT_QUEUE]; 360822c3b04SShreyas NC }; 361822c3b04SShreyas NC 362822c3b04SShreyas NC struct skl_module { 3639e0784d0SAndy Shevchenko guid_t uuid; 364822c3b04SShreyas NC u8 loadable; 365822c3b04SShreyas NC u8 input_pin_type; 366822c3b04SShreyas NC u8 output_pin_type; 367822c3b04SShreyas NC u8 max_input_pins; 368822c3b04SShreyas NC u8 max_output_pins; 369822c3b04SShreyas NC u8 nr_resources; 370822c3b04SShreyas NC u8 nr_interfaces; 371822c3b04SShreyas NC struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES]; 372822c3b04SShreyas NC struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS]; 373822c3b04SShreyas NC }; 374822c3b04SShreyas NC 37523db472bSJeeja KP struct skl_module_cfg { 37609305da9SShreyas NC u8 guid[16]; 37723db472bSJeeja KP struct skl_module_inst_id id; 378f6fa56e2SRamesh Babu struct skl_module *module; 379f6fa56e2SRamesh Babu int res_idx; 380f6fa56e2SRamesh Babu int fmt_idx; 38104afbbbbSHardik T Shah u8 domain; 3824cd9899fSHardik T Shah bool homogenous_inputs; 3834cd9899fSHardik T Shah bool homogenous_outputs; 3844cd9899fSHardik T Shah struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 3854cd9899fSHardik T Shah struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 38623db472bSJeeja KP u8 max_in_queue; 38723db472bSJeeja KP u8 max_out_queue; 38823db472bSJeeja KP u8 in_queue_mask; 38923db472bSJeeja KP u8 out_queue_mask; 39023db472bSJeeja KP u8 in_queue; 39123db472bSJeeja KP u8 out_queue; 39223db472bSJeeja KP u32 mcps; 39323db472bSJeeja KP u32 ibs; 39423db472bSJeeja KP u32 obs; 39523db472bSJeeja KP u8 is_loadable; 39623db472bSJeeja KP u8 core_id; 39723db472bSJeeja KP u8 dev_type; 39823db472bSJeeja KP u8 dma_id; 39923db472bSJeeja KP u8 time_slot; 4007a1b749bSDharageswari R u8 dmic_ch_combo_index; 4017a1b749bSDharageswari R u32 dmic_ch_type; 40223db472bSJeeja KP u32 params_fixup; 40323db472bSJeeja KP u32 converter; 40423db472bSJeeja KP u32 vbus_id; 405b18c458dSJeeja KP u32 mem_pages; 4066bd9dcf3SVinod Koul enum d0i3_capability d0i3_caps; 407939df3adSRamesh Babu u32 dma_buffer_size; /* in milli seconds */ 40823db472bSJeeja KP struct skl_module_pin *m_in_pin; 40923db472bSJeeja KP struct skl_module_pin *m_out_pin; 41023db472bSJeeja KP enum skl_module_type m_type; 41123db472bSJeeja KP enum skl_hw_conn_type hw_conn_type; 41223db472bSJeeja KP enum skl_module_state m_state; 41323db472bSJeeja KP struct skl_pipe *pipe; 41423db472bSJeeja KP struct skl_specific_cfg formats_config; 415f6fa56e2SRamesh Babu struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE]; 41623db472bSJeeja KP }; 417a0ffe48bSHardik T Shah 418abb74003SJeeja KP struct skl_algo_data { 419abb74003SJeeja KP u32 param_id; 4204ced1827SJeeja KP u32 set_params; 421abb74003SJeeja KP u32 max; 4220d682104SDharageswari R u32 size; 423abb74003SJeeja KP char *params; 424abb74003SJeeja KP }; 425abb74003SJeeja KP 426e4e2d2f4SJeeja KP struct skl_pipeline { 427e4e2d2f4SJeeja KP struct skl_pipe *pipe; 428e4e2d2f4SJeeja KP struct list_head node; 429e4e2d2f4SJeeja KP }; 430e4e2d2f4SJeeja KP 431b8c722ddSJeeja KP struct skl_module_deferred_bind { 432b8c722ddSJeeja KP struct skl_module_cfg *src; 433b8c722ddSJeeja KP struct skl_module_cfg *dst; 434b8c722ddSJeeja KP struct list_head node; 435b8c722ddSJeeja KP }; 436b8c722ddSJeeja KP 4377a1b749bSDharageswari R struct skl_mic_sel_config { 4387a1b749bSDharageswari R u16 mic_switch; 4397a1b749bSDharageswari R u16 flags; 4407a1b749bSDharageswari R u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 4417a1b749bSDharageswari R } __packed; 4427a1b749bSDharageswari R 4437a1b749bSDharageswari R enum skl_channel { 4447a1b749bSDharageswari R SKL_CH_MONO = 1, 4457a1b749bSDharageswari R SKL_CH_STEREO = 2, 4467a1b749bSDharageswari R SKL_CH_TRIO = 3, 4477a1b749bSDharageswari R SKL_CH_QUATRO = 4, 4487a1b749bSDharageswari R }; 4497a1b749bSDharageswari R 450bcc2a2dcSCezary Rojewski static inline struct skl_dev *get_skl_ctx(struct device *dev) 451d93f8e55SVinod Koul { 45276f56faeSRakesh Ughreja struct hdac_bus *bus = dev_get_drvdata(dev); 453d93f8e55SVinod Koul 45476f56faeSRakesh Ughreja return bus_to_skl(bus); 455d93f8e55SVinod Koul } 456d93f8e55SVinod Koul 457cfb0a873SVinod Koul int skl_tplg_be_update_params(struct snd_soc_dai *dai, 458cfb0a873SVinod Koul struct skl_pipe_params *params); 459bcc2a2dcSCezary Rojewski int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps, 4605514830dSJaikrishna Nemallapudi u32 caps_size, u32 node_id); 461cfb0a873SVinod Koul void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 462cfb0a873SVinod Koul struct skl_pipe_params *params, int stream); 46324ada035SMark Brown int skl_tplg_init(struct snd_soc_component *component, 46476f56faeSRakesh Ughreja struct hdac_bus *ebus); 465e79986ceSAmadeusz Sławiński void skl_tplg_exit(struct snd_soc_component *component, 466e79986ceSAmadeusz Sławiński struct hdac_bus *bus); 467cfb0a873SVinod Koul struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 468cfb0a873SVinod Koul struct snd_soc_dai *dai, int stream); 469cfb0a873SVinod Koul int skl_tplg_update_pipe_params(struct device *dev, 470cfb0a873SVinod Koul struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 471cfb0a873SVinod Koul 472bcc2a2dcSCezary Rojewski void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps); 473bcc2a2dcSCezary Rojewski void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps); 474a83e3b4cSVinod Koul 475bcc2a2dcSCezary Rojewski int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe); 476c9b1e834SJeeja KP 477bcc2a2dcSCezary Rojewski int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 478c9b1e834SJeeja KP 479bcc2a2dcSCezary Rojewski int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 480c9b1e834SJeeja KP 481bcc2a2dcSCezary Rojewski int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 482c9b1e834SJeeja KP 483bcc2a2dcSCezary Rojewski int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 484c9b1e834SJeeja KP 485bcc2a2dcSCezary Rojewski int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 4862004432fSJeeja KP 487bcc2a2dcSCezary Rojewski int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *module_config); 488beb73b26SJeeja KP 489bcc2a2dcSCezary Rojewski int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg 490beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 491beb73b26SJeeja KP 492bcc2a2dcSCezary Rojewski int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg 493beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 494beb73b26SJeeja KP 495bcc2a2dcSCezary Rojewski int skl_set_module_params(struct skl_dev *skl, u32 *params, int size, 4969939a9c3SJeeja KP u32 param_id, struct skl_module_cfg *mcfg); 497bcc2a2dcSCezary Rojewski int skl_get_module_params(struct skl_dev *skl, u32 *params, int size, 4987d9f2911SOmair M Abdullah u32 param_id, struct skl_module_cfg *mcfg); 4999939a9c3SJeeja KP 500718a42b5SDharageswari.R struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 501718a42b5SDharageswari.R int stream); 50223db472bSJeeja KP enum skl_bitdepth skl_get_bit_depth(int params); 503ad036bdeSJeeja KP int skl_pcm_host_dma_prepare(struct device *dev, 504ad036bdeSJeeja KP struct skl_pipe_params *params); 505ad036bdeSJeeja KP int skl_pcm_link_dma_prepare(struct device *dev, 506ad036bdeSJeeja KP struct skl_pipe_params *params); 507606e21fdSGuneshwor Singh 508c60b613aSLiam Girdwood int skl_dai_load(struct snd_soc_component *cmp, int index, 509c60b613aSLiam Girdwood struct snd_soc_dai_driver *dai_drv, 510c60b613aSLiam Girdwood struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); 511bcc2a2dcSCezary Rojewski void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl, 51224ada035SMark Brown struct snd_soc_dapm_widget *w); 51323db472bSJeeja KP #endif 514