18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 223db472bSJeeja KP /* 323db472bSJeeja KP * skl_topology.h - Intel HDA Platform topology header file 423db472bSJeeja KP * 523db472bSJeeja KP * Copyright (C) 2014-15 Intel Corp 623db472bSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com> 723db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 823db472bSJeeja KP * 923db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1023db472bSJeeja KP */ 1123db472bSJeeja KP 1223db472bSJeeja KP #ifndef __SKL_TOPOLOGY_H__ 1323db472bSJeeja KP #define __SKL_TOPOLOGY_H__ 1423db472bSJeeja KP 1523db472bSJeeja KP #include <linux/types.h> 1623db472bSJeeja KP 1723db472bSJeeja KP #include <sound/hdaudio_ext.h> 1823db472bSJeeja KP #include <sound/soc.h> 190c24fdc0SGuenter Roeck #include <uapi/sound/skl-tplg-interface.h> 2023db472bSJeeja KP #include "skl.h" 2123db472bSJeeja KP 2223db472bSJeeja KP #define BITS_PER_BYTE 8 2323db472bSJeeja KP #define MAX_TS_GROUPS 8 2423db472bSJeeja KP #define MAX_DMIC_TS_GROUPS 4 2523db472bSJeeja KP #define MAX_FIXED_DMIC_PARAMS_SIZE 727 2623db472bSJeeja KP 2723db472bSJeeja KP /* Maximum number of coefficients up down mixer module */ 283e1b96c8SGuneshwor Singh #define UP_DOWN_MIXER_MAX_COEFF 8 2923db472bSJeeja KP 304cd9899fSHardik T Shah #define MODULE_MAX_IN_PINS 8 314cd9899fSHardik T Shah #define MODULE_MAX_OUT_PINS 8 324cd9899fSHardik T Shah 337a1b749bSDharageswari R #define SKL_MIC_CH_SUPPORT 4 347a1b749bSDharageswari R #define SKL_MIC_MAX_CH_SUPPORT 8 357a1b749bSDharageswari R #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 367a1b749bSDharageswari R #define SKL_MIC_SEL_SWITCH 0x3 377a1b749bSDharageswari R 38822c3b04SShreyas NC #define SKL_OUTPUT_PIN 0 39822c3b04SShreyas NC #define SKL_INPUT_PIN 1 40822c3b04SShreyas NC #define SKL_MAX_PATH_CONFIGS 8 41822c3b04SShreyas NC #define SKL_MAX_MODULES_IN_PIPE 8 42822c3b04SShreyas NC #define SKL_MAX_MODULE_FORMATS 32 43822c3b04SShreyas NC #define SKL_MAX_MODULE_RESOURCES 32 44822c3b04SShreyas NC 4523db472bSJeeja KP enum skl_channel_index { 4623db472bSJeeja KP SKL_CHANNEL_LEFT = 0, 4723db472bSJeeja KP SKL_CHANNEL_RIGHT = 1, 4823db472bSJeeja KP SKL_CHANNEL_CENTER = 2, 4923db472bSJeeja KP SKL_CHANNEL_LEFT_SURROUND = 3, 5023db472bSJeeja KP SKL_CHANNEL_CENTER_SURROUND = 3, 5123db472bSJeeja KP SKL_CHANNEL_RIGHT_SURROUND = 4, 5223db472bSJeeja KP SKL_CHANNEL_LFE = 7, 5323db472bSJeeja KP SKL_CHANNEL_INVALID = 0xF, 5423db472bSJeeja KP }; 5523db472bSJeeja KP 5623db472bSJeeja KP enum skl_bitdepth { 5723db472bSJeeja KP SKL_DEPTH_8BIT = 8, 5823db472bSJeeja KP SKL_DEPTH_16BIT = 16, 5923db472bSJeeja KP SKL_DEPTH_24BIT = 24, 6023db472bSJeeja KP SKL_DEPTH_32BIT = 32, 6123db472bSJeeja KP SKL_DEPTH_INVALID 6223db472bSJeeja KP }; 6323db472bSJeeja KP 6423db472bSJeeja KP 6523db472bSJeeja KP enum skl_s_freq { 6623db472bSJeeja KP SKL_FS_8000 = 8000, 6723db472bSJeeja KP SKL_FS_11025 = 11025, 6823db472bSJeeja KP SKL_FS_12000 = 12000, 6923db472bSJeeja KP SKL_FS_16000 = 16000, 7023db472bSJeeja KP SKL_FS_22050 = 22050, 7123db472bSJeeja KP SKL_FS_24000 = 24000, 7223db472bSJeeja KP SKL_FS_32000 = 32000, 7323db472bSJeeja KP SKL_FS_44100 = 44100, 7423db472bSJeeja KP SKL_FS_48000 = 48000, 7523db472bSJeeja KP SKL_FS_64000 = 64000, 7623db472bSJeeja KP SKL_FS_88200 = 88200, 7723db472bSJeeja KP SKL_FS_96000 = 96000, 7823db472bSJeeja KP SKL_FS_128000 = 128000, 7923db472bSJeeja KP SKL_FS_176400 = 176400, 8023db472bSJeeja KP SKL_FS_192000 = 192000, 8123db472bSJeeja KP SKL_FS_INVALID 8223db472bSJeeja KP }; 8323db472bSJeeja KP 8423db472bSJeeja KP enum skl_widget_type { 8523db472bSJeeja KP SKL_WIDGET_VMIXER = 1, 8623db472bSJeeja KP SKL_WIDGET_MIXER = 2, 8723db472bSJeeja KP SKL_WIDGET_PGA = 3, 8823db472bSJeeja KP SKL_WIDGET_MUX = 4 8923db472bSJeeja KP }; 9023db472bSJeeja KP 9123db472bSJeeja KP struct skl_audio_data_format { 9223db472bSJeeja KP enum skl_s_freq s_freq; 9323db472bSJeeja KP enum skl_bitdepth bit_depth; 9423db472bSJeeja KP u32 channel_map; 9523db472bSJeeja KP enum skl_ch_cfg ch_cfg; 9623db472bSJeeja KP enum skl_interleaving interleaving; 9723db472bSJeeja KP u8 number_of_channels; 9823db472bSJeeja KP u8 valid_bit_depth; 9923db472bSJeeja KP u8 sample_type; 10023db472bSJeeja KP u8 reserved[1]; 10123db472bSJeeja KP } __packed; 10223db472bSJeeja KP 10323db472bSJeeja KP struct skl_base_cfg { 10484b71067SCezary Rojewski u32 cpc; 10523db472bSJeeja KP u32 ibs; 10623db472bSJeeja KP u32 obs; 10723db472bSJeeja KP u32 is_pages; 10823db472bSJeeja KP struct skl_audio_data_format audio_fmt; 10923db472bSJeeja KP }; 11023db472bSJeeja KP 11123db472bSJeeja KP struct skl_cpr_gtw_cfg { 11223db472bSJeeja KP u32 node_id; 11323db472bSJeeja KP u32 dma_buffer_size; 11423db472bSJeeja KP u32 config_length; 11523db472bSJeeja KP /* not mandatory; required only for DMIC/I2S */ 11623db472bSJeeja KP u32 config_data[1]; 11723db472bSJeeja KP } __packed; 11823db472bSJeeja KP 119c115fa5eSDharageswari.R struct skl_dma_control { 120c115fa5eSDharageswari.R u32 node_id; 121c115fa5eSDharageswari.R u32 config_length; 122936b9df7SGustavo A. R. Silva u32 config_data[]; 123c115fa5eSDharageswari.R } __packed; 124c115fa5eSDharageswari.R 12523db472bSJeeja KP struct skl_cpr_cfg { 12623db472bSJeeja KP struct skl_base_cfg base_cfg; 12723db472bSJeeja KP struct skl_audio_data_format out_fmt; 12823db472bSJeeja KP u32 cpr_feature_mask; 12923db472bSJeeja KP struct skl_cpr_gtw_cfg gtw_cfg; 13023db472bSJeeja KP } __packed; 13123db472bSJeeja KP 13238a77085SPradeep Tewani struct skl_cpr_pin_fmt { 13338a77085SPradeep Tewani u32 sink_id; 13438a77085SPradeep Tewani struct skl_audio_data_format src_fmt; 13538a77085SPradeep Tewani struct skl_audio_data_format dst_fmt; 13638a77085SPradeep Tewani } __packed; 137a0ffe48bSHardik T Shah 138a0ffe48bSHardik T Shah struct skl_src_module_cfg { 139a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 140a0ffe48bSHardik T Shah enum skl_s_freq src_cfg; 141a0ffe48bSHardik T Shah } __packed; 142a0ffe48bSHardik T Shah 143a0ffe48bSHardik T Shah struct skl_up_down_mixer_cfg { 144a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 145a0ffe48bSHardik T Shah enum skl_ch_cfg out_ch_cfg; 146a0ffe48bSHardik T Shah /* This should be set to 1 if user coefficients are required */ 147a0ffe48bSHardik T Shah u32 coeff_sel; 148a0ffe48bSHardik T Shah /* Pass the user coeff in this array */ 149a0ffe48bSHardik T Shah s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 150da3417feSGuneshwor Singh u32 ch_map; 151a0ffe48bSHardik T Shah } __packed; 152a0ffe48bSHardik T Shah 153399b210bSJeeja KP struct skl_algo_cfg { 154399b210bSJeeja KP struct skl_base_cfg base_cfg; 155936b9df7SGustavo A. R. Silva char params[]; 156399b210bSJeeja KP } __packed; 157399b210bSJeeja KP 158fd18110fSDharageswari R struct skl_base_outfmt_cfg { 159fd18110fSDharageswari R struct skl_base_cfg base_cfg; 160fd18110fSDharageswari R struct skl_audio_data_format out_fmt; 161fd18110fSDharageswari R } __packed; 162fd18110fSDharageswari R 16323db472bSJeeja KP enum skl_dma_type { 16423db472bSJeeja KP SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 16523db472bSJeeja KP SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 16623db472bSJeeja KP SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 16723db472bSJeeja KP SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 16823db472bSJeeja KP SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 16923db472bSJeeja KP SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 17023db472bSJeeja KP SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 17123db472bSJeeja KP SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 17223db472bSJeeja KP SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 17323db472bSJeeja KP }; 17423db472bSJeeja KP 17523db472bSJeeja KP union skl_ssp_dma_node { 17623db472bSJeeja KP u8 val; 17723db472bSJeeja KP struct { 178d7b18813SJeeja KP u8 time_slot_index:4; 17923db472bSJeeja KP u8 i2s_instance:4; 18023db472bSJeeja KP } dma_node; 18123db472bSJeeja KP }; 18223db472bSJeeja KP 18323db472bSJeeja KP union skl_connector_node_id { 18423db472bSJeeja KP u32 val; 18523db472bSJeeja KP struct { 18623db472bSJeeja KP u32 vindex:8; 18723db472bSJeeja KP u32 dma_type:4; 18823db472bSJeeja KP u32 rsvd:20; 18923db472bSJeeja KP } node; 19023db472bSJeeja KP }; 19123db472bSJeeja KP 19223db472bSJeeja KP struct skl_module_fmt { 19323db472bSJeeja KP u32 channels; 19423db472bSJeeja KP u32 s_freq; 19523db472bSJeeja KP u32 bit_depth; 19623db472bSJeeja KP u32 valid_bit_depth; 19723db472bSJeeja KP u32 ch_cfg; 1984cd9899fSHardik T Shah u32 interleaving_style; 1994cd9899fSHardik T Shah u32 sample_type; 2004cd9899fSHardik T Shah u32 ch_map; 20123db472bSJeeja KP }; 20223db472bSJeeja KP 2034f745708SJeeja KP struct skl_module_cfg; 2044f745708SJeeja KP 2055e8f0ee4SDharageswari R struct skl_mod_inst_map { 2065e8f0ee4SDharageswari R u16 mod_id; 2075e8f0ee4SDharageswari R u16 inst_id; 2085e8f0ee4SDharageswari R }; 2095e8f0ee4SDharageswari R 21024ada035SMark Brown struct skl_uuid_inst_map { 21124ada035SMark Brown u16 inst_id; 21224ada035SMark Brown u16 reserved; 2139e0784d0SAndy Shevchenko guid_t mod_uuid; 21424ada035SMark Brown } __packed; 21524ada035SMark Brown 2165e8f0ee4SDharageswari R struct skl_kpb_params { 2175e8f0ee4SDharageswari R u32 num_modules; 21824ada035SMark Brown union { 2195e8f0ee4SDharageswari R struct skl_mod_inst_map map[0]; 22024ada035SMark Brown struct skl_uuid_inst_map map_uuid[0]; 22124ada035SMark Brown } u; 2225e8f0ee4SDharageswari R }; 2235e8f0ee4SDharageswari R 22423db472bSJeeja KP struct skl_module_inst_id { 2259e0784d0SAndy Shevchenko guid_t mod_uuid; 226b7c50555SVinod Koul int module_id; 22723db472bSJeeja KP u32 instance_id; 228700a9a63SDharageswari R int pvt_id; 22923db472bSJeeja KP }; 23023db472bSJeeja KP 2314f745708SJeeja KP enum skl_module_pin_state { 2324f745708SJeeja KP SKL_PIN_UNBIND = 0, 2334f745708SJeeja KP SKL_PIN_BIND_DONE = 1, 2344f745708SJeeja KP }; 2354f745708SJeeja KP 23623db472bSJeeja KP struct skl_module_pin { 23723db472bSJeeja KP struct skl_module_inst_id id; 23823db472bSJeeja KP bool is_dynamic; 23923db472bSJeeja KP bool in_use; 2404f745708SJeeja KP enum skl_module_pin_state pin_state; 2414f745708SJeeja KP struct skl_module_cfg *tgt_mcfg; 24223db472bSJeeja KP }; 24323db472bSJeeja KP 24423db472bSJeeja KP struct skl_specific_cfg { 2454ced1827SJeeja KP u32 set_params; 246abb74003SJeeja KP u32 param_id; 24723db472bSJeeja KP u32 caps_size; 24823db472bSJeeja KP u32 *caps; 24923db472bSJeeja KP }; 25023db472bSJeeja KP 25123db472bSJeeja KP enum skl_pipe_state { 25223db472bSJeeja KP SKL_PIPE_INVALID = 0, 25323db472bSJeeja KP SKL_PIPE_CREATED = 1, 25423db472bSJeeja KP SKL_PIPE_PAUSED = 2, 2552004432fSJeeja KP SKL_PIPE_STARTED = 3, 2562004432fSJeeja KP SKL_PIPE_RESET = 4 25723db472bSJeeja KP }; 25823db472bSJeeja KP 25923db472bSJeeja KP struct skl_pipe_module { 26023db472bSJeeja KP struct snd_soc_dapm_widget *w; 26123db472bSJeeja KP struct list_head node; 26223db472bSJeeja KP }; 26323db472bSJeeja KP 26423db472bSJeeja KP struct skl_pipe_params { 26523db472bSJeeja KP u8 host_dma_id; 26623db472bSJeeja KP u8 link_dma_id; 26723db472bSJeeja KP u32 ch; 26823db472bSJeeja KP u32 s_freq; 26923db472bSJeeja KP u32 s_fmt; 27023db472bSJeeja KP u8 linktype; 27112c3be0eSJeeja KP snd_pcm_format_t format; 27212c3be0eSJeeja KP int link_index; 27323db472bSJeeja KP int stream; 2747f975a38SJeeja KP unsigned int host_bps; 2757f975a38SJeeja KP unsigned int link_bps; 27623db472bSJeeja KP }; 27723db472bSJeeja KP 278f6fa56e2SRamesh Babu struct skl_pipe_fmt { 279f6fa56e2SRamesh Babu u32 freq; 280f6fa56e2SRamesh Babu u8 channels; 281f6fa56e2SRamesh Babu u8 bps; 282f6fa56e2SRamesh Babu }; 283f6fa56e2SRamesh Babu 284f6fa56e2SRamesh Babu struct skl_pipe_mcfg { 285f6fa56e2SRamesh Babu u8 res_idx; 286f6fa56e2SRamesh Babu u8 fmt_idx; 287f6fa56e2SRamesh Babu }; 288f6fa56e2SRamesh Babu 289f6fa56e2SRamesh Babu struct skl_path_config { 290f6fa56e2SRamesh Babu u8 mem_pages; 291f6fa56e2SRamesh Babu struct skl_pipe_fmt in_fmt; 292f6fa56e2SRamesh Babu struct skl_pipe_fmt out_fmt; 293f6fa56e2SRamesh Babu }; 294f6fa56e2SRamesh Babu 29523db472bSJeeja KP struct skl_pipe { 29623db472bSJeeja KP u8 ppl_id; 29723db472bSJeeja KP u8 pipe_priority; 29823db472bSJeeja KP u16 conn_type; 29923db472bSJeeja KP u32 memory_pages; 3008a0cb236SVinod Koul u8 lp_mode; 30123db472bSJeeja KP struct skl_pipe_params *p_params; 30223db472bSJeeja KP enum skl_pipe_state state; 303f6fa56e2SRamesh Babu u8 direction; 304f6fa56e2SRamesh Babu u8 cur_config_idx; 305f6fa56e2SRamesh Babu u8 nr_cfgs; 306f6fa56e2SRamesh Babu struct skl_path_config configs[SKL_MAX_PATH_CONFIGS]; 30723db472bSJeeja KP struct list_head w_list; 308f0aa94faSJeeja KP bool passthru; 3091b450791SMateusz Gorski u32 pipe_config_idx; 31023db472bSJeeja KP }; 31123db472bSJeeja KP 31223db472bSJeeja KP enum skl_module_state { 31323db472bSJeeja KP SKL_MODULE_UNINIT = 0, 314d643678bSJeeja KP SKL_MODULE_LOADED = 1, 315d643678bSJeeja KP SKL_MODULE_INIT_DONE = 2, 316d643678bSJeeja KP SKL_MODULE_BIND_DONE = 3, 317d643678bSJeeja KP SKL_MODULE_UNLOADED = 4, 31823db472bSJeeja KP }; 31923db472bSJeeja KP 3206bd9dcf3SVinod Koul enum d0i3_capability { 3216bd9dcf3SVinod Koul SKL_D0I3_NONE = 0, 3226bd9dcf3SVinod Koul SKL_D0I3_STREAMING = 1, 3236bd9dcf3SVinod Koul SKL_D0I3_NON_STREAMING = 2, 3246bd9dcf3SVinod Koul }; 3256bd9dcf3SVinod Koul 326822c3b04SShreyas NC struct skl_module_pin_fmt { 327822c3b04SShreyas NC u8 id; 328822c3b04SShreyas NC struct skl_module_fmt fmt; 329822c3b04SShreyas NC }; 330822c3b04SShreyas NC 331822c3b04SShreyas NC struct skl_module_iface { 332822c3b04SShreyas NC u8 fmt_idx; 333822c3b04SShreyas NC u8 nr_in_fmt; 334822c3b04SShreyas NC u8 nr_out_fmt; 335822c3b04SShreyas NC struct skl_module_pin_fmt inputs[MAX_IN_QUEUE]; 336822c3b04SShreyas NC struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE]; 337822c3b04SShreyas NC }; 338822c3b04SShreyas NC 339822c3b04SShreyas NC struct skl_module_pin_resources { 340822c3b04SShreyas NC u8 pin_index; 341822c3b04SShreyas NC u32 buf_size; 342822c3b04SShreyas NC }; 343822c3b04SShreyas NC 344822c3b04SShreyas NC struct skl_module_res { 345822c3b04SShreyas NC u8 id; 346822c3b04SShreyas NC u32 is_pages; 347822c3b04SShreyas NC u32 ibs; 348822c3b04SShreyas NC u32 obs; 349822c3b04SShreyas NC u32 dma_buffer_size; 350822c3b04SShreyas NC u32 cpc; 351822c3b04SShreyas NC u8 nr_input_pins; 352822c3b04SShreyas NC u8 nr_output_pins; 353822c3b04SShreyas NC struct skl_module_pin_resources input[MAX_IN_QUEUE]; 354822c3b04SShreyas NC struct skl_module_pin_resources output[MAX_OUT_QUEUE]; 355822c3b04SShreyas NC }; 356822c3b04SShreyas NC 357822c3b04SShreyas NC struct skl_module { 3589e0784d0SAndy Shevchenko guid_t uuid; 359822c3b04SShreyas NC u8 loadable; 360822c3b04SShreyas NC u8 input_pin_type; 361822c3b04SShreyas NC u8 output_pin_type; 362822c3b04SShreyas NC u8 max_input_pins; 363822c3b04SShreyas NC u8 max_output_pins; 364822c3b04SShreyas NC u8 nr_resources; 365822c3b04SShreyas NC u8 nr_interfaces; 366822c3b04SShreyas NC struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES]; 367822c3b04SShreyas NC struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS]; 368822c3b04SShreyas NC }; 369822c3b04SShreyas NC 37023db472bSJeeja KP struct skl_module_cfg { 37109305da9SShreyas NC u8 guid[16]; 37223db472bSJeeja KP struct skl_module_inst_id id; 373f6fa56e2SRamesh Babu struct skl_module *module; 374f6fa56e2SRamesh Babu int res_idx; 375f6fa56e2SRamesh Babu int fmt_idx; 37604afbbbbSHardik T Shah u8 domain; 3774cd9899fSHardik T Shah bool homogenous_inputs; 3784cd9899fSHardik T Shah bool homogenous_outputs; 3794cd9899fSHardik T Shah struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 3804cd9899fSHardik T Shah struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 38123db472bSJeeja KP u8 max_in_queue; 38223db472bSJeeja KP u8 max_out_queue; 38323db472bSJeeja KP u8 in_queue_mask; 38423db472bSJeeja KP u8 out_queue_mask; 38523db472bSJeeja KP u8 in_queue; 38623db472bSJeeja KP u8 out_queue; 38723db472bSJeeja KP u8 is_loadable; 38823db472bSJeeja KP u8 core_id; 38923db472bSJeeja KP u8 dev_type; 39023db472bSJeeja KP u8 dma_id; 39123db472bSJeeja KP u8 time_slot; 3927a1b749bSDharageswari R u8 dmic_ch_combo_index; 3937a1b749bSDharageswari R u32 dmic_ch_type; 39423db472bSJeeja KP u32 params_fixup; 39523db472bSJeeja KP u32 converter; 39623db472bSJeeja KP u32 vbus_id; 397b18c458dSJeeja KP u32 mem_pages; 3986bd9dcf3SVinod Koul enum d0i3_capability d0i3_caps; 399939df3adSRamesh Babu u32 dma_buffer_size; /* in milli seconds */ 40023db472bSJeeja KP struct skl_module_pin *m_in_pin; 40123db472bSJeeja KP struct skl_module_pin *m_out_pin; 40223db472bSJeeja KP enum skl_module_type m_type; 40323db472bSJeeja KP enum skl_hw_conn_type hw_conn_type; 40423db472bSJeeja KP enum skl_module_state m_state; 40523db472bSJeeja KP struct skl_pipe *pipe; 40623db472bSJeeja KP struct skl_specific_cfg formats_config; 407f6fa56e2SRamesh Babu struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE]; 40823db472bSJeeja KP }; 409a0ffe48bSHardik T Shah 410abb74003SJeeja KP struct skl_algo_data { 411abb74003SJeeja KP u32 param_id; 4124ced1827SJeeja KP u32 set_params; 413abb74003SJeeja KP u32 max; 4140d682104SDharageswari R u32 size; 415abb74003SJeeja KP char *params; 416abb74003SJeeja KP }; 417abb74003SJeeja KP 418e4e2d2f4SJeeja KP struct skl_pipeline { 419e4e2d2f4SJeeja KP struct skl_pipe *pipe; 420e4e2d2f4SJeeja KP struct list_head node; 421e4e2d2f4SJeeja KP }; 422e4e2d2f4SJeeja KP 423b8c722ddSJeeja KP struct skl_module_deferred_bind { 424b8c722ddSJeeja KP struct skl_module_cfg *src; 425b8c722ddSJeeja KP struct skl_module_cfg *dst; 426b8c722ddSJeeja KP struct list_head node; 427b8c722ddSJeeja KP }; 428b8c722ddSJeeja KP 4297a1b749bSDharageswari R struct skl_mic_sel_config { 4307a1b749bSDharageswari R u16 mic_switch; 4317a1b749bSDharageswari R u16 flags; 4327a1b749bSDharageswari R u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 4337a1b749bSDharageswari R } __packed; 4347a1b749bSDharageswari R 4357a1b749bSDharageswari R enum skl_channel { 4367a1b749bSDharageswari R SKL_CH_MONO = 1, 4377a1b749bSDharageswari R SKL_CH_STEREO = 2, 4387a1b749bSDharageswari R SKL_CH_TRIO = 3, 4397a1b749bSDharageswari R SKL_CH_QUATRO = 4, 4407a1b749bSDharageswari R }; 4417a1b749bSDharageswari R 442bcc2a2dcSCezary Rojewski static inline struct skl_dev *get_skl_ctx(struct device *dev) 443d93f8e55SVinod Koul { 44476f56faeSRakesh Ughreja struct hdac_bus *bus = dev_get_drvdata(dev); 445d93f8e55SVinod Koul 44676f56faeSRakesh Ughreja return bus_to_skl(bus); 447d93f8e55SVinod Koul } 448d93f8e55SVinod Koul 449cfb0a873SVinod Koul int skl_tplg_be_update_params(struct snd_soc_dai *dai, 450cfb0a873SVinod Koul struct skl_pipe_params *params); 451bcc2a2dcSCezary Rojewski int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps, 4525514830dSJaikrishna Nemallapudi u32 caps_size, u32 node_id); 453cfb0a873SVinod Koul void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 454cfb0a873SVinod Koul struct skl_pipe_params *params, int stream); 45524ada035SMark Brown int skl_tplg_init(struct snd_soc_component *component, 45676f56faeSRakesh Ughreja struct hdac_bus *ebus); 457e79986ceSAmadeusz Sławiński void skl_tplg_exit(struct snd_soc_component *component, 458e79986ceSAmadeusz Sławiński struct hdac_bus *bus); 459cfb0a873SVinod Koul struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 460cfb0a873SVinod Koul struct snd_soc_dai *dai, int stream); 461cfb0a873SVinod Koul int skl_tplg_update_pipe_params(struct device *dev, 462cfb0a873SVinod Koul struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 463cfb0a873SVinod Koul 464bcc2a2dcSCezary Rojewski void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps); 465bcc2a2dcSCezary Rojewski void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps); 466a83e3b4cSVinod Koul 467bcc2a2dcSCezary Rojewski int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe); 468c9b1e834SJeeja KP 469bcc2a2dcSCezary Rojewski int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 470c9b1e834SJeeja KP 471bcc2a2dcSCezary Rojewski int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 472c9b1e834SJeeja KP 473bcc2a2dcSCezary Rojewski int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 474c9b1e834SJeeja KP 475bcc2a2dcSCezary Rojewski int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 476c9b1e834SJeeja KP 477bcc2a2dcSCezary Rojewski int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe); 4782004432fSJeeja KP 479bcc2a2dcSCezary Rojewski int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *module_config); 480beb73b26SJeeja KP 481bcc2a2dcSCezary Rojewski int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg 482beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 483beb73b26SJeeja KP 484bcc2a2dcSCezary Rojewski int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg 485beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 486beb73b26SJeeja KP 487bcc2a2dcSCezary Rojewski int skl_set_module_params(struct skl_dev *skl, u32 *params, int size, 4889939a9c3SJeeja KP u32 param_id, struct skl_module_cfg *mcfg); 489bcc2a2dcSCezary Rojewski int skl_get_module_params(struct skl_dev *skl, u32 *params, int size, 4907d9f2911SOmair M Abdullah u32 param_id, struct skl_module_cfg *mcfg); 4919939a9c3SJeeja KP 492718a42b5SDharageswari.R struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 493718a42b5SDharageswari.R int stream); 49423db472bSJeeja KP enum skl_bitdepth skl_get_bit_depth(int params); 495ad036bdeSJeeja KP int skl_pcm_host_dma_prepare(struct device *dev, 496ad036bdeSJeeja KP struct skl_pipe_params *params); 497ad036bdeSJeeja KP int skl_pcm_link_dma_prepare(struct device *dev, 498ad036bdeSJeeja KP struct skl_pipe_params *params); 499606e21fdSGuneshwor Singh 500c60b613aSLiam Girdwood int skl_dai_load(struct snd_soc_component *cmp, int index, 501c60b613aSLiam Girdwood struct snd_soc_dai_driver *dai_drv, 502c60b613aSLiam Girdwood struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); 503bcc2a2dcSCezary Rojewski void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl, 50424ada035SMark Brown struct snd_soc_dapm_widget *w); 50523db472bSJeeja KP #endif 506