123db472bSJeeja KP /* 223db472bSJeeja KP * skl_topology.h - Intel HDA Platform topology header file 323db472bSJeeja KP * 423db472bSJeeja KP * Copyright (C) 2014-15 Intel Corp 523db472bSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com> 623db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 723db472bSJeeja KP * 823db472bSJeeja KP * This program is free software; you can redistribute it and/or modify 923db472bSJeeja KP * it under the terms of the GNU General Public License as published by 1023db472bSJeeja KP * the Free Software Foundation; version 2 of the License. 1123db472bSJeeja KP * 1223db472bSJeeja KP * This program is distributed in the hope that it will be useful, but 1323db472bSJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1423db472bSJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1523db472bSJeeja KP * General Public License for more details. 1623db472bSJeeja KP * 1723db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1823db472bSJeeja KP * 1923db472bSJeeja KP */ 2023db472bSJeeja KP 2123db472bSJeeja KP #ifndef __SKL_TOPOLOGY_H__ 2223db472bSJeeja KP #define __SKL_TOPOLOGY_H__ 2323db472bSJeeja KP 2423db472bSJeeja KP #include <linux/types.h> 2523db472bSJeeja KP 2623db472bSJeeja KP #include <sound/hdaudio_ext.h> 2723db472bSJeeja KP #include <sound/soc.h> 2823db472bSJeeja KP #include "skl.h" 2923db472bSJeeja KP #include "skl-tplg-interface.h" 3023db472bSJeeja KP 3123db472bSJeeja KP #define BITS_PER_BYTE 8 3223db472bSJeeja KP #define MAX_TS_GROUPS 8 3323db472bSJeeja KP #define MAX_DMIC_TS_GROUPS 4 3423db472bSJeeja KP #define MAX_FIXED_DMIC_PARAMS_SIZE 727 3523db472bSJeeja KP 3623db472bSJeeja KP /* Maximum number of coefficients up down mixer module */ 3723db472bSJeeja KP #define UP_DOWN_MIXER_MAX_COEFF 6 3823db472bSJeeja KP 394cd9899fSHardik T Shah #define MODULE_MAX_IN_PINS 8 404cd9899fSHardik T Shah #define MODULE_MAX_OUT_PINS 8 414cd9899fSHardik T Shah 427a1b749bSDharageswari R #define SKL_MIC_CH_SUPPORT 4 437a1b749bSDharageswari R #define SKL_MIC_MAX_CH_SUPPORT 8 447a1b749bSDharageswari R #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF 457a1b749bSDharageswari R #define SKL_MIC_SEL_SWITCH 0x3 467a1b749bSDharageswari R 47822c3b04SShreyas NC #define SKL_OUTPUT_PIN 0 48822c3b04SShreyas NC #define SKL_INPUT_PIN 1 49822c3b04SShreyas NC #define SKL_MAX_PATH_CONFIGS 8 50822c3b04SShreyas NC #define SKL_MAX_MODULES_IN_PIPE 8 51822c3b04SShreyas NC #define SKL_MAX_MODULE_FORMATS 32 52822c3b04SShreyas NC #define SKL_MAX_MODULE_RESOURCES 32 53822c3b04SShreyas NC 5423db472bSJeeja KP enum skl_channel_index { 5523db472bSJeeja KP SKL_CHANNEL_LEFT = 0, 5623db472bSJeeja KP SKL_CHANNEL_RIGHT = 1, 5723db472bSJeeja KP SKL_CHANNEL_CENTER = 2, 5823db472bSJeeja KP SKL_CHANNEL_LEFT_SURROUND = 3, 5923db472bSJeeja KP SKL_CHANNEL_CENTER_SURROUND = 3, 6023db472bSJeeja KP SKL_CHANNEL_RIGHT_SURROUND = 4, 6123db472bSJeeja KP SKL_CHANNEL_LFE = 7, 6223db472bSJeeja KP SKL_CHANNEL_INVALID = 0xF, 6323db472bSJeeja KP }; 6423db472bSJeeja KP 6523db472bSJeeja KP enum skl_bitdepth { 6623db472bSJeeja KP SKL_DEPTH_8BIT = 8, 6723db472bSJeeja KP SKL_DEPTH_16BIT = 16, 6823db472bSJeeja KP SKL_DEPTH_24BIT = 24, 6923db472bSJeeja KP SKL_DEPTH_32BIT = 32, 7023db472bSJeeja KP SKL_DEPTH_INVALID 7123db472bSJeeja KP }; 7223db472bSJeeja KP 7323db472bSJeeja KP 7423db472bSJeeja KP enum skl_s_freq { 7523db472bSJeeja KP SKL_FS_8000 = 8000, 7623db472bSJeeja KP SKL_FS_11025 = 11025, 7723db472bSJeeja KP SKL_FS_12000 = 12000, 7823db472bSJeeja KP SKL_FS_16000 = 16000, 7923db472bSJeeja KP SKL_FS_22050 = 22050, 8023db472bSJeeja KP SKL_FS_24000 = 24000, 8123db472bSJeeja KP SKL_FS_32000 = 32000, 8223db472bSJeeja KP SKL_FS_44100 = 44100, 8323db472bSJeeja KP SKL_FS_48000 = 48000, 8423db472bSJeeja KP SKL_FS_64000 = 64000, 8523db472bSJeeja KP SKL_FS_88200 = 88200, 8623db472bSJeeja KP SKL_FS_96000 = 96000, 8723db472bSJeeja KP SKL_FS_128000 = 128000, 8823db472bSJeeja KP SKL_FS_176400 = 176400, 8923db472bSJeeja KP SKL_FS_192000 = 192000, 9023db472bSJeeja KP SKL_FS_INVALID 9123db472bSJeeja KP }; 9223db472bSJeeja KP 9323db472bSJeeja KP enum skl_widget_type { 9423db472bSJeeja KP SKL_WIDGET_VMIXER = 1, 9523db472bSJeeja KP SKL_WIDGET_MIXER = 2, 9623db472bSJeeja KP SKL_WIDGET_PGA = 3, 9723db472bSJeeja KP SKL_WIDGET_MUX = 4 9823db472bSJeeja KP }; 9923db472bSJeeja KP 10023db472bSJeeja KP struct skl_audio_data_format { 10123db472bSJeeja KP enum skl_s_freq s_freq; 10223db472bSJeeja KP enum skl_bitdepth bit_depth; 10323db472bSJeeja KP u32 channel_map; 10423db472bSJeeja KP enum skl_ch_cfg ch_cfg; 10523db472bSJeeja KP enum skl_interleaving interleaving; 10623db472bSJeeja KP u8 number_of_channels; 10723db472bSJeeja KP u8 valid_bit_depth; 10823db472bSJeeja KP u8 sample_type; 10923db472bSJeeja KP u8 reserved[1]; 11023db472bSJeeja KP } __packed; 11123db472bSJeeja KP 11223db472bSJeeja KP struct skl_base_cfg { 11323db472bSJeeja KP u32 cps; 11423db472bSJeeja KP u32 ibs; 11523db472bSJeeja KP u32 obs; 11623db472bSJeeja KP u32 is_pages; 11723db472bSJeeja KP struct skl_audio_data_format audio_fmt; 11823db472bSJeeja KP }; 11923db472bSJeeja KP 12023db472bSJeeja KP struct skl_cpr_gtw_cfg { 12123db472bSJeeja KP u32 node_id; 12223db472bSJeeja KP u32 dma_buffer_size; 12323db472bSJeeja KP u32 config_length; 12423db472bSJeeja KP /* not mandatory; required only for DMIC/I2S */ 12523db472bSJeeja KP u32 config_data[1]; 12623db472bSJeeja KP } __packed; 12723db472bSJeeja KP 128c115fa5eSDharageswari.R struct skl_dma_control { 129c115fa5eSDharageswari.R u32 node_id; 130c115fa5eSDharageswari.R u32 config_length; 1310b6d76bbSJeeja KP u32 config_data[0]; 132c115fa5eSDharageswari.R } __packed; 133c115fa5eSDharageswari.R 13423db472bSJeeja KP struct skl_cpr_cfg { 13523db472bSJeeja KP struct skl_base_cfg base_cfg; 13623db472bSJeeja KP struct skl_audio_data_format out_fmt; 13723db472bSJeeja KP u32 cpr_feature_mask; 13823db472bSJeeja KP struct skl_cpr_gtw_cfg gtw_cfg; 13923db472bSJeeja KP } __packed; 14023db472bSJeeja KP 141a0ffe48bSHardik T Shah 142a0ffe48bSHardik T Shah struct skl_src_module_cfg { 143a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 144a0ffe48bSHardik T Shah enum skl_s_freq src_cfg; 145a0ffe48bSHardik T Shah } __packed; 146a0ffe48bSHardik T Shah 1474e10996bSJeeja KP struct notification_mask { 1484e10996bSJeeja KP u32 notify; 1494e10996bSJeeja KP u32 enable; 1504e10996bSJeeja KP } __packed; 1514e10996bSJeeja KP 152a0ffe48bSHardik T Shah struct skl_up_down_mixer_cfg { 153a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 154a0ffe48bSHardik T Shah enum skl_ch_cfg out_ch_cfg; 155a0ffe48bSHardik T Shah /* This should be set to 1 if user coefficients are required */ 156a0ffe48bSHardik T Shah u32 coeff_sel; 157a0ffe48bSHardik T Shah /* Pass the user coeff in this array */ 158a0ffe48bSHardik T Shah s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 159a0ffe48bSHardik T Shah } __packed; 160a0ffe48bSHardik T Shah 161399b210bSJeeja KP struct skl_algo_cfg { 162399b210bSJeeja KP struct skl_base_cfg base_cfg; 163399b210bSJeeja KP char params[0]; 164399b210bSJeeja KP } __packed; 165399b210bSJeeja KP 166fd18110fSDharageswari R struct skl_base_outfmt_cfg { 167fd18110fSDharageswari R struct skl_base_cfg base_cfg; 168fd18110fSDharageswari R struct skl_audio_data_format out_fmt; 169fd18110fSDharageswari R } __packed; 170fd18110fSDharageswari R 17123db472bSJeeja KP enum skl_dma_type { 17223db472bSJeeja KP SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 17323db472bSJeeja KP SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 17423db472bSJeeja KP SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 17523db472bSJeeja KP SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 17623db472bSJeeja KP SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 17723db472bSJeeja KP SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 17823db472bSJeeja KP SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 17923db472bSJeeja KP SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 18023db472bSJeeja KP SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 18123db472bSJeeja KP }; 18223db472bSJeeja KP 18323db472bSJeeja KP union skl_ssp_dma_node { 18423db472bSJeeja KP u8 val; 18523db472bSJeeja KP struct { 186d7b18813SJeeja KP u8 time_slot_index:4; 18723db472bSJeeja KP u8 i2s_instance:4; 18823db472bSJeeja KP } dma_node; 18923db472bSJeeja KP }; 19023db472bSJeeja KP 19123db472bSJeeja KP union skl_connector_node_id { 19223db472bSJeeja KP u32 val; 19323db472bSJeeja KP struct { 19423db472bSJeeja KP u32 vindex:8; 19523db472bSJeeja KP u32 dma_type:4; 19623db472bSJeeja KP u32 rsvd:20; 19723db472bSJeeja KP } node; 19823db472bSJeeja KP }; 19923db472bSJeeja KP 20023db472bSJeeja KP struct skl_module_fmt { 20123db472bSJeeja KP u32 channels; 20223db472bSJeeja KP u32 s_freq; 20323db472bSJeeja KP u32 bit_depth; 20423db472bSJeeja KP u32 valid_bit_depth; 20523db472bSJeeja KP u32 ch_cfg; 2064cd9899fSHardik T Shah u32 interleaving_style; 2074cd9899fSHardik T Shah u32 sample_type; 2084cd9899fSHardik T Shah u32 ch_map; 20923db472bSJeeja KP }; 21023db472bSJeeja KP 2114f745708SJeeja KP struct skl_module_cfg; 2124f745708SJeeja KP 2135e8f0ee4SDharageswari R struct skl_mod_inst_map { 2145e8f0ee4SDharageswari R u16 mod_id; 2155e8f0ee4SDharageswari R u16 inst_id; 2165e8f0ee4SDharageswari R }; 2175e8f0ee4SDharageswari R 2185e8f0ee4SDharageswari R struct skl_kpb_params { 2195e8f0ee4SDharageswari R u32 num_modules; 2205e8f0ee4SDharageswari R struct skl_mod_inst_map map[0]; 2215e8f0ee4SDharageswari R }; 2225e8f0ee4SDharageswari R 22323db472bSJeeja KP struct skl_module_inst_id { 224b7c50555SVinod Koul int module_id; 22523db472bSJeeja KP u32 instance_id; 226700a9a63SDharageswari R int pvt_id; 22723db472bSJeeja KP }; 22823db472bSJeeja KP 2294f745708SJeeja KP enum skl_module_pin_state { 2304f745708SJeeja KP SKL_PIN_UNBIND = 0, 2314f745708SJeeja KP SKL_PIN_BIND_DONE = 1, 2324f745708SJeeja KP }; 2334f745708SJeeja KP 23423db472bSJeeja KP struct skl_module_pin { 23523db472bSJeeja KP struct skl_module_inst_id id; 23623db472bSJeeja KP bool is_dynamic; 23723db472bSJeeja KP bool in_use; 2384f745708SJeeja KP enum skl_module_pin_state pin_state; 2394f745708SJeeja KP struct skl_module_cfg *tgt_mcfg; 24023db472bSJeeja KP }; 24123db472bSJeeja KP 24223db472bSJeeja KP struct skl_specific_cfg { 2434ced1827SJeeja KP u32 set_params; 244abb74003SJeeja KP u32 param_id; 24523db472bSJeeja KP u32 caps_size; 24623db472bSJeeja KP u32 *caps; 24723db472bSJeeja KP }; 24823db472bSJeeja KP 24923db472bSJeeja KP enum skl_pipe_state { 25023db472bSJeeja KP SKL_PIPE_INVALID = 0, 25123db472bSJeeja KP SKL_PIPE_CREATED = 1, 25223db472bSJeeja KP SKL_PIPE_PAUSED = 2, 2532004432fSJeeja KP SKL_PIPE_STARTED = 3, 2542004432fSJeeja KP SKL_PIPE_RESET = 4 25523db472bSJeeja KP }; 25623db472bSJeeja KP 25723db472bSJeeja KP struct skl_pipe_module { 25823db472bSJeeja KP struct snd_soc_dapm_widget *w; 25923db472bSJeeja KP struct list_head node; 26023db472bSJeeja KP }; 26123db472bSJeeja KP 26223db472bSJeeja KP struct skl_pipe_params { 26323db472bSJeeja KP u8 host_dma_id; 26423db472bSJeeja KP u8 link_dma_id; 26523db472bSJeeja KP u32 ch; 26623db472bSJeeja KP u32 s_freq; 26723db472bSJeeja KP u32 s_fmt; 26823db472bSJeeja KP u8 linktype; 26912c3be0eSJeeja KP snd_pcm_format_t format; 27012c3be0eSJeeja KP int link_index; 27123db472bSJeeja KP int stream; 2727f975a38SJeeja KP unsigned int host_bps; 2737f975a38SJeeja KP unsigned int link_bps; 27423db472bSJeeja KP }; 27523db472bSJeeja KP 27623db472bSJeeja KP struct skl_pipe { 27723db472bSJeeja KP u8 ppl_id; 27823db472bSJeeja KP u8 pipe_priority; 27923db472bSJeeja KP u16 conn_type; 28023db472bSJeeja KP u32 memory_pages; 2818a0cb236SVinod Koul u8 lp_mode; 28223db472bSJeeja KP struct skl_pipe_params *p_params; 28323db472bSJeeja KP enum skl_pipe_state state; 28423db472bSJeeja KP struct list_head w_list; 285f0aa94faSJeeja KP bool passthru; 28623db472bSJeeja KP }; 28723db472bSJeeja KP 28823db472bSJeeja KP enum skl_module_state { 28923db472bSJeeja KP SKL_MODULE_UNINIT = 0, 290d643678bSJeeja KP SKL_MODULE_LOADED = 1, 291d643678bSJeeja KP SKL_MODULE_INIT_DONE = 2, 292d643678bSJeeja KP SKL_MODULE_BIND_DONE = 3, 293d643678bSJeeja KP SKL_MODULE_UNLOADED = 4, 29423db472bSJeeja KP }; 29523db472bSJeeja KP 2966bd9dcf3SVinod Koul enum d0i3_capability { 2976bd9dcf3SVinod Koul SKL_D0I3_NONE = 0, 2986bd9dcf3SVinod Koul SKL_D0I3_STREAMING = 1, 2996bd9dcf3SVinod Koul SKL_D0I3_NON_STREAMING = 2, 3006bd9dcf3SVinod Koul }; 3016bd9dcf3SVinod Koul 302822c3b04SShreyas NC struct skl_module_pin_fmt { 303822c3b04SShreyas NC u8 id; 304822c3b04SShreyas NC struct skl_module_fmt fmt; 305822c3b04SShreyas NC }; 306822c3b04SShreyas NC 307822c3b04SShreyas NC struct skl_module_iface { 308822c3b04SShreyas NC u8 fmt_idx; 309822c3b04SShreyas NC u8 nr_in_fmt; 310822c3b04SShreyas NC u8 nr_out_fmt; 311822c3b04SShreyas NC struct skl_module_pin_fmt inputs[MAX_IN_QUEUE]; 312822c3b04SShreyas NC struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE]; 313822c3b04SShreyas NC }; 314822c3b04SShreyas NC 315822c3b04SShreyas NC struct skl_module_pin_resources { 316822c3b04SShreyas NC u8 pin_index; 317822c3b04SShreyas NC u32 buf_size; 318822c3b04SShreyas NC }; 319822c3b04SShreyas NC 320822c3b04SShreyas NC struct skl_module_res { 321822c3b04SShreyas NC u8 id; 322822c3b04SShreyas NC u32 is_pages; 323822c3b04SShreyas NC u32 cps; 324822c3b04SShreyas NC u32 ibs; 325822c3b04SShreyas NC u32 obs; 326822c3b04SShreyas NC u32 dma_buffer_size; 327822c3b04SShreyas NC u32 cpc; 328822c3b04SShreyas NC u8 nr_input_pins; 329822c3b04SShreyas NC u8 nr_output_pins; 330822c3b04SShreyas NC struct skl_module_pin_resources input[MAX_IN_QUEUE]; 331822c3b04SShreyas NC struct skl_module_pin_resources output[MAX_OUT_QUEUE]; 332822c3b04SShreyas NC }; 333822c3b04SShreyas NC 334822c3b04SShreyas NC struct skl_module { 335822c3b04SShreyas NC uuid_le uuid; 336822c3b04SShreyas NC u8 loadable; 337822c3b04SShreyas NC u8 input_pin_type; 338822c3b04SShreyas NC u8 output_pin_type; 339822c3b04SShreyas NC u8 max_input_pins; 340822c3b04SShreyas NC u8 max_output_pins; 341822c3b04SShreyas NC u8 nr_resources; 342822c3b04SShreyas NC u8 nr_interfaces; 343822c3b04SShreyas NC struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES]; 344822c3b04SShreyas NC struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS]; 345822c3b04SShreyas NC }; 346822c3b04SShreyas NC 34723db472bSJeeja KP struct skl_module_cfg { 34809305da9SShreyas NC u8 guid[16]; 34923db472bSJeeja KP struct skl_module_inst_id id; 35004afbbbbSHardik T Shah u8 domain; 3514cd9899fSHardik T Shah bool homogenous_inputs; 3524cd9899fSHardik T Shah bool homogenous_outputs; 3534cd9899fSHardik T Shah struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 3544cd9899fSHardik T Shah struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 35523db472bSJeeja KP u8 max_in_queue; 35623db472bSJeeja KP u8 max_out_queue; 35723db472bSJeeja KP u8 in_queue_mask; 35823db472bSJeeja KP u8 out_queue_mask; 35923db472bSJeeja KP u8 in_queue; 36023db472bSJeeja KP u8 out_queue; 36123db472bSJeeja KP u32 mcps; 36223db472bSJeeja KP u32 ibs; 36323db472bSJeeja KP u32 obs; 36423db472bSJeeja KP u8 is_loadable; 36523db472bSJeeja KP u8 core_id; 36623db472bSJeeja KP u8 dev_type; 36723db472bSJeeja KP u8 dma_id; 36823db472bSJeeja KP u8 time_slot; 3697a1b749bSDharageswari R u8 dmic_ch_combo_index; 3707a1b749bSDharageswari R u32 dmic_ch_type; 37123db472bSJeeja KP u32 params_fixup; 37223db472bSJeeja KP u32 converter; 37323db472bSJeeja KP u32 vbus_id; 374b18c458dSJeeja KP u32 mem_pages; 3756bd9dcf3SVinod Koul enum d0i3_capability d0i3_caps; 376939df3adSRamesh Babu u32 dma_buffer_size; /* in milli seconds */ 37723db472bSJeeja KP struct skl_module_pin *m_in_pin; 37823db472bSJeeja KP struct skl_module_pin *m_out_pin; 37923db472bSJeeja KP enum skl_module_type m_type; 38023db472bSJeeja KP enum skl_hw_conn_type hw_conn_type; 38123db472bSJeeja KP enum skl_module_state m_state; 38223db472bSJeeja KP struct skl_pipe *pipe; 38323db472bSJeeja KP struct skl_specific_cfg formats_config; 38423db472bSJeeja KP }; 385a0ffe48bSHardik T Shah 386abb74003SJeeja KP struct skl_algo_data { 387abb74003SJeeja KP u32 param_id; 3884ced1827SJeeja KP u32 set_params; 389abb74003SJeeja KP u32 max; 3900d682104SDharageswari R u32 size; 391abb74003SJeeja KP char *params; 392abb74003SJeeja KP }; 393abb74003SJeeja KP 394e4e2d2f4SJeeja KP struct skl_pipeline { 395e4e2d2f4SJeeja KP struct skl_pipe *pipe; 396e4e2d2f4SJeeja KP struct list_head node; 397e4e2d2f4SJeeja KP }; 398e4e2d2f4SJeeja KP 399b8c722ddSJeeja KP struct skl_module_deferred_bind { 400b8c722ddSJeeja KP struct skl_module_cfg *src; 401b8c722ddSJeeja KP struct skl_module_cfg *dst; 402b8c722ddSJeeja KP struct list_head node; 403b8c722ddSJeeja KP }; 404b8c722ddSJeeja KP 4057a1b749bSDharageswari R struct skl_mic_sel_config { 4067a1b749bSDharageswari R u16 mic_switch; 4077a1b749bSDharageswari R u16 flags; 4087a1b749bSDharageswari R u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT]; 4097a1b749bSDharageswari R } __packed; 4107a1b749bSDharageswari R 4117a1b749bSDharageswari R enum skl_channel { 4127a1b749bSDharageswari R SKL_CH_MONO = 1, 4137a1b749bSDharageswari R SKL_CH_STEREO = 2, 4147a1b749bSDharageswari R SKL_CH_TRIO = 3, 4157a1b749bSDharageswari R SKL_CH_QUATRO = 4, 4167a1b749bSDharageswari R }; 4177a1b749bSDharageswari R 418d93f8e55SVinod Koul static inline struct skl *get_skl_ctx(struct device *dev) 419d93f8e55SVinod Koul { 420d93f8e55SVinod Koul struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 421d93f8e55SVinod Koul 422d93f8e55SVinod Koul return ebus_to_skl(ebus); 423d93f8e55SVinod Koul } 424d93f8e55SVinod Koul 425cfb0a873SVinod Koul int skl_tplg_be_update_params(struct snd_soc_dai *dai, 426cfb0a873SVinod Koul struct skl_pipe_params *params); 427c115fa5eSDharageswari.R int skl_dsp_set_dma_control(struct skl_sst *ctx, 428c115fa5eSDharageswari.R struct skl_module_cfg *mconfig); 429cfb0a873SVinod Koul void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 430cfb0a873SVinod Koul struct skl_pipe_params *params, int stream); 431cfb0a873SVinod Koul int skl_tplg_init(struct snd_soc_platform *platform, 432cfb0a873SVinod Koul struct hdac_ext_bus *ebus); 433cfb0a873SVinod Koul struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 434cfb0a873SVinod Koul struct snd_soc_dai *dai, int stream); 435cfb0a873SVinod Koul int skl_tplg_update_pipe_params(struct device *dev, 436cfb0a873SVinod Koul struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 437cfb0a873SVinod Koul 438a83e3b4cSVinod Koul void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps); 439a83e3b4cSVinod Koul void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps); 440a83e3b4cSVinod Koul 441c9b1e834SJeeja KP int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 442c9b1e834SJeeja KP 443c9b1e834SJeeja KP int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 444c9b1e834SJeeja KP 445c9b1e834SJeeja KP int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 446c9b1e834SJeeja KP 447c9b1e834SJeeja KP int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 448c9b1e834SJeeja KP 449c9b1e834SJeeja KP int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 450c9b1e834SJeeja KP 4512004432fSJeeja KP int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 4522004432fSJeeja KP 4539939a9c3SJeeja KP int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 454beb73b26SJeeja KP 455beb73b26SJeeja KP int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 456beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 457beb73b26SJeeja KP 458beb73b26SJeeja KP int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 459beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 460beb73b26SJeeja KP 4619939a9c3SJeeja KP int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 4629939a9c3SJeeja KP u32 param_id, struct skl_module_cfg *mcfg); 4637d9f2911SOmair M Abdullah int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 4647d9f2911SOmair M Abdullah u32 param_id, struct skl_module_cfg *mcfg); 4659939a9c3SJeeja KP 466718a42b5SDharageswari.R struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 467718a42b5SDharageswari.R int stream); 46823db472bSJeeja KP enum skl_bitdepth skl_get_bit_depth(int params); 469ad036bdeSJeeja KP int skl_pcm_host_dma_prepare(struct device *dev, 470ad036bdeSJeeja KP struct skl_pipe_params *params); 471ad036bdeSJeeja KP int skl_pcm_link_dma_prepare(struct device *dev, 472ad036bdeSJeeja KP struct skl_pipe_params *params); 47323db472bSJeeja KP #endif 474