123db472bSJeeja KP /* 223db472bSJeeja KP * skl_topology.h - Intel HDA Platform topology header file 323db472bSJeeja KP * 423db472bSJeeja KP * Copyright (C) 2014-15 Intel Corp 523db472bSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com> 623db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 723db472bSJeeja KP * 823db472bSJeeja KP * This program is free software; you can redistribute it and/or modify 923db472bSJeeja KP * it under the terms of the GNU General Public License as published by 1023db472bSJeeja KP * the Free Software Foundation; version 2 of the License. 1123db472bSJeeja KP * 1223db472bSJeeja KP * This program is distributed in the hope that it will be useful, but 1323db472bSJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1423db472bSJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1523db472bSJeeja KP * General Public License for more details. 1623db472bSJeeja KP * 1723db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1823db472bSJeeja KP * 1923db472bSJeeja KP */ 2023db472bSJeeja KP 2123db472bSJeeja KP #ifndef __SKL_TOPOLOGY_H__ 2223db472bSJeeja KP #define __SKL_TOPOLOGY_H__ 2323db472bSJeeja KP 2423db472bSJeeja KP #include <linux/types.h> 2523db472bSJeeja KP 2623db472bSJeeja KP #include <sound/hdaudio_ext.h> 2723db472bSJeeja KP #include <sound/soc.h> 2823db472bSJeeja KP #include "skl.h" 2923db472bSJeeja KP #include "skl-tplg-interface.h" 3023db472bSJeeja KP 3123db472bSJeeja KP #define BITS_PER_BYTE 8 3223db472bSJeeja KP #define MAX_TS_GROUPS 8 3323db472bSJeeja KP #define MAX_DMIC_TS_GROUPS 4 3423db472bSJeeja KP #define MAX_FIXED_DMIC_PARAMS_SIZE 727 3523db472bSJeeja KP 3623db472bSJeeja KP /* Maximum number of coefficients up down mixer module */ 3723db472bSJeeja KP #define UP_DOWN_MIXER_MAX_COEFF 6 3823db472bSJeeja KP 394cd9899fSHardik T Shah #define MODULE_MAX_IN_PINS 8 404cd9899fSHardik T Shah #define MODULE_MAX_OUT_PINS 8 414cd9899fSHardik T Shah 4223db472bSJeeja KP enum skl_channel_index { 4323db472bSJeeja KP SKL_CHANNEL_LEFT = 0, 4423db472bSJeeja KP SKL_CHANNEL_RIGHT = 1, 4523db472bSJeeja KP SKL_CHANNEL_CENTER = 2, 4623db472bSJeeja KP SKL_CHANNEL_LEFT_SURROUND = 3, 4723db472bSJeeja KP SKL_CHANNEL_CENTER_SURROUND = 3, 4823db472bSJeeja KP SKL_CHANNEL_RIGHT_SURROUND = 4, 4923db472bSJeeja KP SKL_CHANNEL_LFE = 7, 5023db472bSJeeja KP SKL_CHANNEL_INVALID = 0xF, 5123db472bSJeeja KP }; 5223db472bSJeeja KP 5323db472bSJeeja KP enum skl_bitdepth { 5423db472bSJeeja KP SKL_DEPTH_8BIT = 8, 5523db472bSJeeja KP SKL_DEPTH_16BIT = 16, 5623db472bSJeeja KP SKL_DEPTH_24BIT = 24, 5723db472bSJeeja KP SKL_DEPTH_32BIT = 32, 5823db472bSJeeja KP SKL_DEPTH_INVALID 5923db472bSJeeja KP }; 6023db472bSJeeja KP 6123db472bSJeeja KP enum skl_interleaving { 6223db472bSJeeja KP /* [s1_ch1...s1_chN,...,sM_ch1...sM_chN] */ 6323db472bSJeeja KP SKL_INTERLEAVING_PER_CHANNEL = 0, 6423db472bSJeeja KP /* [s1_ch1...sM_ch1,...,s1_chN...sM_chN] */ 6523db472bSJeeja KP SKL_INTERLEAVING_PER_SAMPLE = 1, 6623db472bSJeeja KP }; 6723db472bSJeeja KP 6823db472bSJeeja KP enum skl_s_freq { 6923db472bSJeeja KP SKL_FS_8000 = 8000, 7023db472bSJeeja KP SKL_FS_11025 = 11025, 7123db472bSJeeja KP SKL_FS_12000 = 12000, 7223db472bSJeeja KP SKL_FS_16000 = 16000, 7323db472bSJeeja KP SKL_FS_22050 = 22050, 7423db472bSJeeja KP SKL_FS_24000 = 24000, 7523db472bSJeeja KP SKL_FS_32000 = 32000, 7623db472bSJeeja KP SKL_FS_44100 = 44100, 7723db472bSJeeja KP SKL_FS_48000 = 48000, 7823db472bSJeeja KP SKL_FS_64000 = 64000, 7923db472bSJeeja KP SKL_FS_88200 = 88200, 8023db472bSJeeja KP SKL_FS_96000 = 96000, 8123db472bSJeeja KP SKL_FS_128000 = 128000, 8223db472bSJeeja KP SKL_FS_176400 = 176400, 8323db472bSJeeja KP SKL_FS_192000 = 192000, 8423db472bSJeeja KP SKL_FS_INVALID 8523db472bSJeeja KP }; 8623db472bSJeeja KP 8723db472bSJeeja KP enum skl_widget_type { 8823db472bSJeeja KP SKL_WIDGET_VMIXER = 1, 8923db472bSJeeja KP SKL_WIDGET_MIXER = 2, 9023db472bSJeeja KP SKL_WIDGET_PGA = 3, 9123db472bSJeeja KP SKL_WIDGET_MUX = 4 9223db472bSJeeja KP }; 9323db472bSJeeja KP 9423db472bSJeeja KP struct skl_audio_data_format { 9523db472bSJeeja KP enum skl_s_freq s_freq; 9623db472bSJeeja KP enum skl_bitdepth bit_depth; 9723db472bSJeeja KP u32 channel_map; 9823db472bSJeeja KP enum skl_ch_cfg ch_cfg; 9923db472bSJeeja KP enum skl_interleaving interleaving; 10023db472bSJeeja KP u8 number_of_channels; 10123db472bSJeeja KP u8 valid_bit_depth; 10223db472bSJeeja KP u8 sample_type; 10323db472bSJeeja KP u8 reserved[1]; 10423db472bSJeeja KP } __packed; 10523db472bSJeeja KP 10623db472bSJeeja KP struct skl_base_cfg { 10723db472bSJeeja KP u32 cps; 10823db472bSJeeja KP u32 ibs; 10923db472bSJeeja KP u32 obs; 11023db472bSJeeja KP u32 is_pages; 11123db472bSJeeja KP struct skl_audio_data_format audio_fmt; 11223db472bSJeeja KP }; 11323db472bSJeeja KP 11423db472bSJeeja KP struct skl_cpr_gtw_cfg { 11523db472bSJeeja KP u32 node_id; 11623db472bSJeeja KP u32 dma_buffer_size; 11723db472bSJeeja KP u32 config_length; 11823db472bSJeeja KP /* not mandatory; required only for DMIC/I2S */ 11923db472bSJeeja KP u32 config_data[1]; 12023db472bSJeeja KP } __packed; 12123db472bSJeeja KP 12223db472bSJeeja KP struct skl_cpr_cfg { 12323db472bSJeeja KP struct skl_base_cfg base_cfg; 12423db472bSJeeja KP struct skl_audio_data_format out_fmt; 12523db472bSJeeja KP u32 cpr_feature_mask; 12623db472bSJeeja KP struct skl_cpr_gtw_cfg gtw_cfg; 12723db472bSJeeja KP } __packed; 12823db472bSJeeja KP 129a0ffe48bSHardik T Shah 130a0ffe48bSHardik T Shah struct skl_src_module_cfg { 131a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 132a0ffe48bSHardik T Shah enum skl_s_freq src_cfg; 133a0ffe48bSHardik T Shah } __packed; 134a0ffe48bSHardik T Shah 1354e10996bSJeeja KP struct notification_mask { 1364e10996bSJeeja KP u32 notify; 1374e10996bSJeeja KP u32 enable; 1384e10996bSJeeja KP } __packed; 1394e10996bSJeeja KP 140a0ffe48bSHardik T Shah struct skl_up_down_mixer_cfg { 141a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 142a0ffe48bSHardik T Shah enum skl_ch_cfg out_ch_cfg; 143a0ffe48bSHardik T Shah /* This should be set to 1 if user coefficients are required */ 144a0ffe48bSHardik T Shah u32 coeff_sel; 145a0ffe48bSHardik T Shah /* Pass the user coeff in this array */ 146a0ffe48bSHardik T Shah s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 147a0ffe48bSHardik T Shah } __packed; 148a0ffe48bSHardik T Shah 14923db472bSJeeja KP enum skl_dma_type { 15023db472bSJeeja KP SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 15123db472bSJeeja KP SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 15223db472bSJeeja KP SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 15323db472bSJeeja KP SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 15423db472bSJeeja KP SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 15523db472bSJeeja KP SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 15623db472bSJeeja KP SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 15723db472bSJeeja KP SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 15823db472bSJeeja KP SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 15923db472bSJeeja KP }; 16023db472bSJeeja KP 16123db472bSJeeja KP union skl_ssp_dma_node { 16223db472bSJeeja KP u8 val; 16323db472bSJeeja KP struct { 164d7b18813SJeeja KP u8 time_slot_index:4; 16523db472bSJeeja KP u8 i2s_instance:4; 16623db472bSJeeja KP } dma_node; 16723db472bSJeeja KP }; 16823db472bSJeeja KP 16923db472bSJeeja KP union skl_connector_node_id { 17023db472bSJeeja KP u32 val; 17123db472bSJeeja KP struct { 17223db472bSJeeja KP u32 vindex:8; 17323db472bSJeeja KP u32 dma_type:4; 17423db472bSJeeja KP u32 rsvd:20; 17523db472bSJeeja KP } node; 17623db472bSJeeja KP }; 17723db472bSJeeja KP 17823db472bSJeeja KP struct skl_module_fmt { 17923db472bSJeeja KP u32 channels; 18023db472bSJeeja KP u32 s_freq; 18123db472bSJeeja KP u32 bit_depth; 18223db472bSJeeja KP u32 valid_bit_depth; 18323db472bSJeeja KP u32 ch_cfg; 1844cd9899fSHardik T Shah u32 interleaving_style; 1854cd9899fSHardik T Shah u32 sample_type; 1864cd9899fSHardik T Shah u32 ch_map; 18723db472bSJeeja KP }; 18823db472bSJeeja KP 1894f745708SJeeja KP struct skl_module_cfg; 1904f745708SJeeja KP 19123db472bSJeeja KP struct skl_module_inst_id { 19223db472bSJeeja KP u32 module_id; 19323db472bSJeeja KP u32 instance_id; 19423db472bSJeeja KP }; 19523db472bSJeeja KP 1964f745708SJeeja KP enum skl_module_pin_state { 1974f745708SJeeja KP SKL_PIN_UNBIND = 0, 1984f745708SJeeja KP SKL_PIN_BIND_DONE = 1, 1994f745708SJeeja KP }; 2004f745708SJeeja KP 20123db472bSJeeja KP struct skl_module_pin { 20223db472bSJeeja KP struct skl_module_inst_id id; 20323db472bSJeeja KP bool is_dynamic; 20423db472bSJeeja KP bool in_use; 2054f745708SJeeja KP enum skl_module_pin_state pin_state; 2064f745708SJeeja KP struct skl_module_cfg *tgt_mcfg; 20723db472bSJeeja KP }; 20823db472bSJeeja KP 20923db472bSJeeja KP struct skl_specific_cfg { 21023db472bSJeeja KP u32 caps_size; 21123db472bSJeeja KP u32 *caps; 21223db472bSJeeja KP }; 21323db472bSJeeja KP 21423db472bSJeeja KP enum skl_pipe_state { 21523db472bSJeeja KP SKL_PIPE_INVALID = 0, 21623db472bSJeeja KP SKL_PIPE_CREATED = 1, 21723db472bSJeeja KP SKL_PIPE_PAUSED = 2, 21823db472bSJeeja KP SKL_PIPE_STARTED = 3 21923db472bSJeeja KP }; 22023db472bSJeeja KP 22123db472bSJeeja KP struct skl_pipe_module { 22223db472bSJeeja KP struct snd_soc_dapm_widget *w; 22323db472bSJeeja KP struct list_head node; 22423db472bSJeeja KP }; 22523db472bSJeeja KP 22623db472bSJeeja KP struct skl_pipe_params { 22723db472bSJeeja KP u8 host_dma_id; 22823db472bSJeeja KP u8 link_dma_id; 22923db472bSJeeja KP u32 ch; 23023db472bSJeeja KP u32 s_freq; 23123db472bSJeeja KP u32 s_fmt; 23223db472bSJeeja KP u8 linktype; 23323db472bSJeeja KP int stream; 23423db472bSJeeja KP }; 23523db472bSJeeja KP 23623db472bSJeeja KP struct skl_pipe { 23723db472bSJeeja KP u8 ppl_id; 23823db472bSJeeja KP u8 pipe_priority; 23923db472bSJeeja KP u16 conn_type; 24023db472bSJeeja KP u32 memory_pages; 24123db472bSJeeja KP struct skl_pipe_params *p_params; 24223db472bSJeeja KP enum skl_pipe_state state; 24323db472bSJeeja KP struct list_head w_list; 24423db472bSJeeja KP }; 24523db472bSJeeja KP 24623db472bSJeeja KP enum skl_module_state { 24723db472bSJeeja KP SKL_MODULE_UNINIT = 0, 24823db472bSJeeja KP SKL_MODULE_INIT_DONE = 1, 24923db472bSJeeja KP SKL_MODULE_LOADED = 2, 25023db472bSJeeja KP SKL_MODULE_UNLOADED = 3, 25123db472bSJeeja KP SKL_MODULE_BIND_DONE = 4 25223db472bSJeeja KP }; 25323db472bSJeeja KP 25423db472bSJeeja KP struct skl_module_cfg { 25523db472bSJeeja KP struct skl_module_inst_id id; 2564cd9899fSHardik T Shah bool homogenous_inputs; 2574cd9899fSHardik T Shah bool homogenous_outputs; 2584cd9899fSHardik T Shah struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 2594cd9899fSHardik T Shah struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 26023db472bSJeeja KP u8 max_in_queue; 26123db472bSJeeja KP u8 max_out_queue; 26223db472bSJeeja KP u8 in_queue_mask; 26323db472bSJeeja KP u8 out_queue_mask; 26423db472bSJeeja KP u8 in_queue; 26523db472bSJeeja KP u8 out_queue; 26623db472bSJeeja KP u32 mcps; 26723db472bSJeeja KP u32 ibs; 26823db472bSJeeja KP u32 obs; 26923db472bSJeeja KP u8 is_loadable; 27023db472bSJeeja KP u8 core_id; 27123db472bSJeeja KP u8 dev_type; 27223db472bSJeeja KP u8 dma_id; 27323db472bSJeeja KP u8 time_slot; 27423db472bSJeeja KP u32 params_fixup; 27523db472bSJeeja KP u32 converter; 27623db472bSJeeja KP u32 vbus_id; 27723db472bSJeeja KP struct skl_module_pin *m_in_pin; 27823db472bSJeeja KP struct skl_module_pin *m_out_pin; 27923db472bSJeeja KP enum skl_module_type m_type; 28023db472bSJeeja KP enum skl_hw_conn_type hw_conn_type; 28123db472bSJeeja KP enum skl_module_state m_state; 28223db472bSJeeja KP struct skl_pipe *pipe; 28323db472bSJeeja KP struct skl_specific_cfg formats_config; 28423db472bSJeeja KP }; 285a0ffe48bSHardik T Shah 286e4e2d2f4SJeeja KP struct skl_pipeline { 287e4e2d2f4SJeeja KP struct skl_pipe *pipe; 288e4e2d2f4SJeeja KP struct list_head node; 289e4e2d2f4SJeeja KP }; 290e4e2d2f4SJeeja KP 291d93f8e55SVinod Koul static inline struct skl *get_skl_ctx(struct device *dev) 292d93f8e55SVinod Koul { 293d93f8e55SVinod Koul struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 294d93f8e55SVinod Koul 295d93f8e55SVinod Koul return ebus_to_skl(ebus); 296d93f8e55SVinod Koul } 297d93f8e55SVinod Koul 298cfb0a873SVinod Koul int skl_tplg_be_update_params(struct snd_soc_dai *dai, 299cfb0a873SVinod Koul struct skl_pipe_params *params); 300cfb0a873SVinod Koul void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 301cfb0a873SVinod Koul struct skl_pipe_params *params, int stream); 302cfb0a873SVinod Koul int skl_tplg_init(struct snd_soc_platform *platform, 303cfb0a873SVinod Koul struct hdac_ext_bus *ebus); 304cfb0a873SVinod Koul struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 305cfb0a873SVinod Koul struct snd_soc_dai *dai, int stream); 306cfb0a873SVinod Koul int skl_tplg_update_pipe_params(struct device *dev, 307cfb0a873SVinod Koul struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 308cfb0a873SVinod Koul 309c9b1e834SJeeja KP int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 310c9b1e834SJeeja KP 311c9b1e834SJeeja KP int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 312c9b1e834SJeeja KP 313c9b1e834SJeeja KP int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 314c9b1e834SJeeja KP 315c9b1e834SJeeja KP int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 316c9b1e834SJeeja KP 317c9b1e834SJeeja KP int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 318c9b1e834SJeeja KP 319beb73b26SJeeja KP int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config, 320beb73b26SJeeja KP char *param); 321beb73b26SJeeja KP 322beb73b26SJeeja KP int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 323beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 324beb73b26SJeeja KP 325beb73b26SJeeja KP int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 326beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 327beb73b26SJeeja KP 32823db472bSJeeja KP enum skl_bitdepth skl_get_bit_depth(int params); 32923db472bSJeeja KP #endif 330