123db472bSJeeja KP /* 223db472bSJeeja KP * skl_topology.h - Intel HDA Platform topology header file 323db472bSJeeja KP * 423db472bSJeeja KP * Copyright (C) 2014-15 Intel Corp 523db472bSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com> 623db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 723db472bSJeeja KP * 823db472bSJeeja KP * This program is free software; you can redistribute it and/or modify 923db472bSJeeja KP * it under the terms of the GNU General Public License as published by 1023db472bSJeeja KP * the Free Software Foundation; version 2 of the License. 1123db472bSJeeja KP * 1223db472bSJeeja KP * This program is distributed in the hope that it will be useful, but 1323db472bSJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1423db472bSJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1523db472bSJeeja KP * General Public License for more details. 1623db472bSJeeja KP * 1723db472bSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1823db472bSJeeja KP * 1923db472bSJeeja KP */ 2023db472bSJeeja KP 2123db472bSJeeja KP #ifndef __SKL_TOPOLOGY_H__ 2223db472bSJeeja KP #define __SKL_TOPOLOGY_H__ 2323db472bSJeeja KP 2423db472bSJeeja KP #include <linux/types.h> 2523db472bSJeeja KP 2623db472bSJeeja KP #include <sound/hdaudio_ext.h> 2723db472bSJeeja KP #include <sound/soc.h> 2823db472bSJeeja KP #include "skl.h" 2923db472bSJeeja KP #include "skl-tplg-interface.h" 3023db472bSJeeja KP 3123db472bSJeeja KP #define BITS_PER_BYTE 8 3223db472bSJeeja KP #define MAX_TS_GROUPS 8 3323db472bSJeeja KP #define MAX_DMIC_TS_GROUPS 4 3423db472bSJeeja KP #define MAX_FIXED_DMIC_PARAMS_SIZE 727 3523db472bSJeeja KP 3623db472bSJeeja KP /* Maximum number of coefficients up down mixer module */ 3723db472bSJeeja KP #define UP_DOWN_MIXER_MAX_COEFF 6 3823db472bSJeeja KP 394cd9899fSHardik T Shah #define MODULE_MAX_IN_PINS 8 404cd9899fSHardik T Shah #define MODULE_MAX_OUT_PINS 8 414cd9899fSHardik T Shah 4223db472bSJeeja KP enum skl_channel_index { 4323db472bSJeeja KP SKL_CHANNEL_LEFT = 0, 4423db472bSJeeja KP SKL_CHANNEL_RIGHT = 1, 4523db472bSJeeja KP SKL_CHANNEL_CENTER = 2, 4623db472bSJeeja KP SKL_CHANNEL_LEFT_SURROUND = 3, 4723db472bSJeeja KP SKL_CHANNEL_CENTER_SURROUND = 3, 4823db472bSJeeja KP SKL_CHANNEL_RIGHT_SURROUND = 4, 4923db472bSJeeja KP SKL_CHANNEL_LFE = 7, 5023db472bSJeeja KP SKL_CHANNEL_INVALID = 0xF, 5123db472bSJeeja KP }; 5223db472bSJeeja KP 5323db472bSJeeja KP enum skl_bitdepth { 5423db472bSJeeja KP SKL_DEPTH_8BIT = 8, 5523db472bSJeeja KP SKL_DEPTH_16BIT = 16, 5623db472bSJeeja KP SKL_DEPTH_24BIT = 24, 5723db472bSJeeja KP SKL_DEPTH_32BIT = 32, 5823db472bSJeeja KP SKL_DEPTH_INVALID 5923db472bSJeeja KP }; 6023db472bSJeeja KP 6123db472bSJeeja KP 6223db472bSJeeja KP enum skl_s_freq { 6323db472bSJeeja KP SKL_FS_8000 = 8000, 6423db472bSJeeja KP SKL_FS_11025 = 11025, 6523db472bSJeeja KP SKL_FS_12000 = 12000, 6623db472bSJeeja KP SKL_FS_16000 = 16000, 6723db472bSJeeja KP SKL_FS_22050 = 22050, 6823db472bSJeeja KP SKL_FS_24000 = 24000, 6923db472bSJeeja KP SKL_FS_32000 = 32000, 7023db472bSJeeja KP SKL_FS_44100 = 44100, 7123db472bSJeeja KP SKL_FS_48000 = 48000, 7223db472bSJeeja KP SKL_FS_64000 = 64000, 7323db472bSJeeja KP SKL_FS_88200 = 88200, 7423db472bSJeeja KP SKL_FS_96000 = 96000, 7523db472bSJeeja KP SKL_FS_128000 = 128000, 7623db472bSJeeja KP SKL_FS_176400 = 176400, 7723db472bSJeeja KP SKL_FS_192000 = 192000, 7823db472bSJeeja KP SKL_FS_INVALID 7923db472bSJeeja KP }; 8023db472bSJeeja KP 8123db472bSJeeja KP enum skl_widget_type { 8223db472bSJeeja KP SKL_WIDGET_VMIXER = 1, 8323db472bSJeeja KP SKL_WIDGET_MIXER = 2, 8423db472bSJeeja KP SKL_WIDGET_PGA = 3, 8523db472bSJeeja KP SKL_WIDGET_MUX = 4 8623db472bSJeeja KP }; 8723db472bSJeeja KP 8823db472bSJeeja KP struct skl_audio_data_format { 8923db472bSJeeja KP enum skl_s_freq s_freq; 9023db472bSJeeja KP enum skl_bitdepth bit_depth; 9123db472bSJeeja KP u32 channel_map; 9223db472bSJeeja KP enum skl_ch_cfg ch_cfg; 9323db472bSJeeja KP enum skl_interleaving interleaving; 9423db472bSJeeja KP u8 number_of_channels; 9523db472bSJeeja KP u8 valid_bit_depth; 9623db472bSJeeja KP u8 sample_type; 9723db472bSJeeja KP u8 reserved[1]; 9823db472bSJeeja KP } __packed; 9923db472bSJeeja KP 10023db472bSJeeja KP struct skl_base_cfg { 10123db472bSJeeja KP u32 cps; 10223db472bSJeeja KP u32 ibs; 10323db472bSJeeja KP u32 obs; 10423db472bSJeeja KP u32 is_pages; 10523db472bSJeeja KP struct skl_audio_data_format audio_fmt; 10623db472bSJeeja KP }; 10723db472bSJeeja KP 10823db472bSJeeja KP struct skl_cpr_gtw_cfg { 10923db472bSJeeja KP u32 node_id; 11023db472bSJeeja KP u32 dma_buffer_size; 11123db472bSJeeja KP u32 config_length; 11223db472bSJeeja KP /* not mandatory; required only for DMIC/I2S */ 11323db472bSJeeja KP u32 config_data[1]; 11423db472bSJeeja KP } __packed; 11523db472bSJeeja KP 116c115fa5eSDharageswari.R struct skl_dma_control { 117c115fa5eSDharageswari.R u32 node_id; 118c115fa5eSDharageswari.R u32 config_length; 1190b6d76bbSJeeja KP u32 config_data[0]; 120c115fa5eSDharageswari.R } __packed; 121c115fa5eSDharageswari.R 12223db472bSJeeja KP struct skl_cpr_cfg { 12323db472bSJeeja KP struct skl_base_cfg base_cfg; 12423db472bSJeeja KP struct skl_audio_data_format out_fmt; 12523db472bSJeeja KP u32 cpr_feature_mask; 12623db472bSJeeja KP struct skl_cpr_gtw_cfg gtw_cfg; 12723db472bSJeeja KP } __packed; 12823db472bSJeeja KP 129a0ffe48bSHardik T Shah 130a0ffe48bSHardik T Shah struct skl_src_module_cfg { 131a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 132a0ffe48bSHardik T Shah enum skl_s_freq src_cfg; 133a0ffe48bSHardik T Shah } __packed; 134a0ffe48bSHardik T Shah 1354e10996bSJeeja KP struct notification_mask { 1364e10996bSJeeja KP u32 notify; 1374e10996bSJeeja KP u32 enable; 1384e10996bSJeeja KP } __packed; 1394e10996bSJeeja KP 140a0ffe48bSHardik T Shah struct skl_up_down_mixer_cfg { 141a0ffe48bSHardik T Shah struct skl_base_cfg base_cfg; 142a0ffe48bSHardik T Shah enum skl_ch_cfg out_ch_cfg; 143a0ffe48bSHardik T Shah /* This should be set to 1 if user coefficients are required */ 144a0ffe48bSHardik T Shah u32 coeff_sel; 145a0ffe48bSHardik T Shah /* Pass the user coeff in this array */ 146a0ffe48bSHardik T Shah s32 coeff[UP_DOWN_MIXER_MAX_COEFF]; 147a0ffe48bSHardik T Shah } __packed; 148a0ffe48bSHardik T Shah 149399b210bSJeeja KP struct skl_algo_cfg { 150399b210bSJeeja KP struct skl_base_cfg base_cfg; 151399b210bSJeeja KP char params[0]; 152399b210bSJeeja KP } __packed; 153399b210bSJeeja KP 154fd18110fSDharageswari R struct skl_base_outfmt_cfg { 155fd18110fSDharageswari R struct skl_base_cfg base_cfg; 156fd18110fSDharageswari R struct skl_audio_data_format out_fmt; 157fd18110fSDharageswari R } __packed; 158fd18110fSDharageswari R 15923db472bSJeeja KP enum skl_dma_type { 16023db472bSJeeja KP SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0, 16123db472bSJeeja KP SKL_DMA_HDA_HOST_INPUT_CLASS = 1, 16223db472bSJeeja KP SKL_DMA_HDA_HOST_INOUT_CLASS = 2, 16323db472bSJeeja KP SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8, 16423db472bSJeeja KP SKL_DMA_HDA_LINK_INPUT_CLASS = 9, 16523db472bSJeeja KP SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA, 16623db472bSJeeja KP SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB, 16723db472bSJeeja KP SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC, 16823db472bSJeeja KP SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD, 16923db472bSJeeja KP }; 17023db472bSJeeja KP 17123db472bSJeeja KP union skl_ssp_dma_node { 17223db472bSJeeja KP u8 val; 17323db472bSJeeja KP struct { 174d7b18813SJeeja KP u8 time_slot_index:4; 17523db472bSJeeja KP u8 i2s_instance:4; 17623db472bSJeeja KP } dma_node; 17723db472bSJeeja KP }; 17823db472bSJeeja KP 17923db472bSJeeja KP union skl_connector_node_id { 18023db472bSJeeja KP u32 val; 18123db472bSJeeja KP struct { 18223db472bSJeeja KP u32 vindex:8; 18323db472bSJeeja KP u32 dma_type:4; 18423db472bSJeeja KP u32 rsvd:20; 18523db472bSJeeja KP } node; 18623db472bSJeeja KP }; 18723db472bSJeeja KP 18823db472bSJeeja KP struct skl_module_fmt { 18923db472bSJeeja KP u32 channels; 19023db472bSJeeja KP u32 s_freq; 19123db472bSJeeja KP u32 bit_depth; 19223db472bSJeeja KP u32 valid_bit_depth; 19323db472bSJeeja KP u32 ch_cfg; 1944cd9899fSHardik T Shah u32 interleaving_style; 1954cd9899fSHardik T Shah u32 sample_type; 1964cd9899fSHardik T Shah u32 ch_map; 19723db472bSJeeja KP }; 19823db472bSJeeja KP 1994f745708SJeeja KP struct skl_module_cfg; 2004f745708SJeeja KP 2015e8f0ee4SDharageswari R struct skl_mod_inst_map { 2025e8f0ee4SDharageswari R u16 mod_id; 2035e8f0ee4SDharageswari R u16 inst_id; 2045e8f0ee4SDharageswari R }; 2055e8f0ee4SDharageswari R 2065e8f0ee4SDharageswari R struct skl_kpb_params { 2075e8f0ee4SDharageswari R u32 num_modules; 2085e8f0ee4SDharageswari R struct skl_mod_inst_map map[0]; 2095e8f0ee4SDharageswari R }; 2105e8f0ee4SDharageswari R 21123db472bSJeeja KP struct skl_module_inst_id { 212b7c50555SVinod Koul int module_id; 21323db472bSJeeja KP u32 instance_id; 214700a9a63SDharageswari R int pvt_id; 21523db472bSJeeja KP }; 21623db472bSJeeja KP 2174f745708SJeeja KP enum skl_module_pin_state { 2184f745708SJeeja KP SKL_PIN_UNBIND = 0, 2194f745708SJeeja KP SKL_PIN_BIND_DONE = 1, 2204f745708SJeeja KP }; 2214f745708SJeeja KP 22223db472bSJeeja KP struct skl_module_pin { 22323db472bSJeeja KP struct skl_module_inst_id id; 22423db472bSJeeja KP bool is_dynamic; 22523db472bSJeeja KP bool in_use; 2264f745708SJeeja KP enum skl_module_pin_state pin_state; 2274f745708SJeeja KP struct skl_module_cfg *tgt_mcfg; 22823db472bSJeeja KP }; 22923db472bSJeeja KP 23023db472bSJeeja KP struct skl_specific_cfg { 2314ced1827SJeeja KP u32 set_params; 232abb74003SJeeja KP u32 param_id; 23323db472bSJeeja KP u32 caps_size; 23423db472bSJeeja KP u32 *caps; 23523db472bSJeeja KP }; 23623db472bSJeeja KP 23723db472bSJeeja KP enum skl_pipe_state { 23823db472bSJeeja KP SKL_PIPE_INVALID = 0, 23923db472bSJeeja KP SKL_PIPE_CREATED = 1, 24023db472bSJeeja KP SKL_PIPE_PAUSED = 2, 2412004432fSJeeja KP SKL_PIPE_STARTED = 3, 2422004432fSJeeja KP SKL_PIPE_RESET = 4 24323db472bSJeeja KP }; 24423db472bSJeeja KP 24523db472bSJeeja KP struct skl_pipe_module { 24623db472bSJeeja KP struct snd_soc_dapm_widget *w; 24723db472bSJeeja KP struct list_head node; 24823db472bSJeeja KP }; 24923db472bSJeeja KP 25023db472bSJeeja KP struct skl_pipe_params { 25123db472bSJeeja KP u8 host_dma_id; 25223db472bSJeeja KP u8 link_dma_id; 25323db472bSJeeja KP u32 ch; 25423db472bSJeeja KP u32 s_freq; 25523db472bSJeeja KP u32 s_fmt; 25623db472bSJeeja KP u8 linktype; 25712c3be0eSJeeja KP snd_pcm_format_t format; 25812c3be0eSJeeja KP int link_index; 25923db472bSJeeja KP int stream; 26023db472bSJeeja KP }; 26123db472bSJeeja KP 26223db472bSJeeja KP struct skl_pipe { 26323db472bSJeeja KP u8 ppl_id; 26423db472bSJeeja KP u8 pipe_priority; 26523db472bSJeeja KP u16 conn_type; 26623db472bSJeeja KP u32 memory_pages; 2678a0cb236SVinod Koul u8 lp_mode; 26823db472bSJeeja KP struct skl_pipe_params *p_params; 26923db472bSJeeja KP enum skl_pipe_state state; 27023db472bSJeeja KP struct list_head w_list; 271f0aa94faSJeeja KP bool passthru; 27223db472bSJeeja KP }; 27323db472bSJeeja KP 27423db472bSJeeja KP enum skl_module_state { 27523db472bSJeeja KP SKL_MODULE_UNINIT = 0, 276d643678bSJeeja KP SKL_MODULE_LOADED = 1, 277d643678bSJeeja KP SKL_MODULE_INIT_DONE = 2, 278d643678bSJeeja KP SKL_MODULE_BIND_DONE = 3, 279d643678bSJeeja KP SKL_MODULE_UNLOADED = 4, 28023db472bSJeeja KP }; 28123db472bSJeeja KP 2826bd9dcf3SVinod Koul enum d0i3_capability { 2836bd9dcf3SVinod Koul SKL_D0I3_NONE = 0, 2846bd9dcf3SVinod Koul SKL_D0I3_STREAMING = 1, 2856bd9dcf3SVinod Koul SKL_D0I3_NON_STREAMING = 2, 2866bd9dcf3SVinod Koul }; 2876bd9dcf3SVinod Koul 28823db472bSJeeja KP struct skl_module_cfg { 28909305da9SShreyas NC u8 guid[16]; 29023db472bSJeeja KP struct skl_module_inst_id id; 29104afbbbbSHardik T Shah u8 domain; 2924cd9899fSHardik T Shah bool homogenous_inputs; 2934cd9899fSHardik T Shah bool homogenous_outputs; 2944cd9899fSHardik T Shah struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS]; 2954cd9899fSHardik T Shah struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS]; 29623db472bSJeeja KP u8 max_in_queue; 29723db472bSJeeja KP u8 max_out_queue; 29823db472bSJeeja KP u8 in_queue_mask; 29923db472bSJeeja KP u8 out_queue_mask; 30023db472bSJeeja KP u8 in_queue; 30123db472bSJeeja KP u8 out_queue; 30223db472bSJeeja KP u32 mcps; 30323db472bSJeeja KP u32 ibs; 30423db472bSJeeja KP u32 obs; 30523db472bSJeeja KP u8 is_loadable; 30623db472bSJeeja KP u8 core_id; 30723db472bSJeeja KP u8 dev_type; 30823db472bSJeeja KP u8 dma_id; 30923db472bSJeeja KP u8 time_slot; 31023db472bSJeeja KP u32 params_fixup; 31123db472bSJeeja KP u32 converter; 31223db472bSJeeja KP u32 vbus_id; 313b18c458dSJeeja KP u32 mem_pages; 3146bd9dcf3SVinod Koul enum d0i3_capability d0i3_caps; 31523db472bSJeeja KP struct skl_module_pin *m_in_pin; 31623db472bSJeeja KP struct skl_module_pin *m_out_pin; 31723db472bSJeeja KP enum skl_module_type m_type; 31823db472bSJeeja KP enum skl_hw_conn_type hw_conn_type; 31923db472bSJeeja KP enum skl_module_state m_state; 32023db472bSJeeja KP struct skl_pipe *pipe; 32123db472bSJeeja KP struct skl_specific_cfg formats_config; 32223db472bSJeeja KP }; 323a0ffe48bSHardik T Shah 324abb74003SJeeja KP struct skl_algo_data { 325abb74003SJeeja KP u32 param_id; 3264ced1827SJeeja KP u32 set_params; 327abb74003SJeeja KP u32 max; 3280d682104SDharageswari R u32 size; 329abb74003SJeeja KP char *params; 330abb74003SJeeja KP }; 331abb74003SJeeja KP 332e4e2d2f4SJeeja KP struct skl_pipeline { 333e4e2d2f4SJeeja KP struct skl_pipe *pipe; 334e4e2d2f4SJeeja KP struct list_head node; 335e4e2d2f4SJeeja KP }; 336e4e2d2f4SJeeja KP 337d93f8e55SVinod Koul static inline struct skl *get_skl_ctx(struct device *dev) 338d93f8e55SVinod Koul { 339d93f8e55SVinod Koul struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 340d93f8e55SVinod Koul 341d93f8e55SVinod Koul return ebus_to_skl(ebus); 342d93f8e55SVinod Koul } 343d93f8e55SVinod Koul 344cfb0a873SVinod Koul int skl_tplg_be_update_params(struct snd_soc_dai *dai, 345cfb0a873SVinod Koul struct skl_pipe_params *params); 346c115fa5eSDharageswari.R int skl_dsp_set_dma_control(struct skl_sst *ctx, 347c115fa5eSDharageswari.R struct skl_module_cfg *mconfig); 348cfb0a873SVinod Koul void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai, 349cfb0a873SVinod Koul struct skl_pipe_params *params, int stream); 350cfb0a873SVinod Koul int skl_tplg_init(struct snd_soc_platform *platform, 351cfb0a873SVinod Koul struct hdac_ext_bus *ebus); 352cfb0a873SVinod Koul struct skl_module_cfg *skl_tplg_fe_get_cpr_module( 353cfb0a873SVinod Koul struct snd_soc_dai *dai, int stream); 354cfb0a873SVinod Koul int skl_tplg_update_pipe_params(struct device *dev, 355cfb0a873SVinod Koul struct skl_module_cfg *mconfig, struct skl_pipe_params *params); 356cfb0a873SVinod Koul 357a83e3b4cSVinod Koul void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps); 358a83e3b4cSVinod Koul void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps); 359a83e3b4cSVinod Koul 360c9b1e834SJeeja KP int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe); 361c9b1e834SJeeja KP 362c9b1e834SJeeja KP int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 363c9b1e834SJeeja KP 364c9b1e834SJeeja KP int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 365c9b1e834SJeeja KP 366c9b1e834SJeeja KP int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 367c9b1e834SJeeja KP 368c9b1e834SJeeja KP int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 369c9b1e834SJeeja KP 3702004432fSJeeja KP int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe); 3712004432fSJeeja KP 3729939a9c3SJeeja KP int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config); 373beb73b26SJeeja KP 374beb73b26SJeeja KP int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg 375beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 376beb73b26SJeeja KP 377beb73b26SJeeja KP int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg 378beb73b26SJeeja KP *src_module, struct skl_module_cfg *dst_module); 379beb73b26SJeeja KP 3809939a9c3SJeeja KP int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, 3819939a9c3SJeeja KP u32 param_id, struct skl_module_cfg *mcfg); 3827d9f2911SOmair M Abdullah int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, 3837d9f2911SOmair M Abdullah u32 param_id, struct skl_module_cfg *mcfg); 3849939a9c3SJeeja KP 385718a42b5SDharageswari.R struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, 386718a42b5SDharageswari.R int stream); 38723db472bSJeeja KP enum skl_bitdepth skl_get_bit_depth(int params); 38823db472bSJeeja KP #endif 389