1 /* 2 * skl-topology.c - Implements Platform component ALSA controls/widget 3 * handlers. 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 #include <linux/firmware.h> 22 #include <sound/soc.h> 23 #include <sound/soc-topology.h> 24 #include "skl-sst-dsp.h" 25 #include "skl-sst-ipc.h" 26 #include "skl-topology.h" 27 #include "skl.h" 28 #include "skl-tplg-interface.h" 29 #include "../common/sst-dsp.h" 30 #include "../common/sst-dsp-priv.h" 31 32 #define SKL_CH_FIXUP_MASK (1 << 0) 33 #define SKL_RATE_FIXUP_MASK (1 << 1) 34 #define SKL_FMT_FIXUP_MASK (1 << 2) 35 36 /* 37 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will 38 * ignore. This helpers checks if the SKL driver handles this widget type 39 */ 40 static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w) 41 { 42 switch (w->id) { 43 case snd_soc_dapm_dai_link: 44 case snd_soc_dapm_dai_in: 45 case snd_soc_dapm_aif_in: 46 case snd_soc_dapm_aif_out: 47 case snd_soc_dapm_dai_out: 48 case snd_soc_dapm_switch: 49 return false; 50 default: 51 return true; 52 } 53 } 54 55 /* 56 * Each pipelines needs memory to be allocated. Check if we have free memory 57 * from available pool. 58 */ 59 static bool skl_is_pipe_mem_avail(struct skl *skl, 60 struct skl_module_cfg *mconfig) 61 { 62 struct skl_sst *ctx = skl->skl_sst; 63 64 if (skl->resource.mem + mconfig->pipe->memory_pages > 65 skl->resource.max_mem) { 66 dev_err(ctx->dev, 67 "%s: module_id %d instance %d\n", __func__, 68 mconfig->id.module_id, 69 mconfig->id.instance_id); 70 dev_err(ctx->dev, 71 "exceeds ppl memory available %d mem %d\n", 72 skl->resource.max_mem, skl->resource.mem); 73 return false; 74 } else { 75 return true; 76 } 77 } 78 79 /* 80 * Add the mem to the mem pool. This is freed when pipe is deleted. 81 * Note: DSP does actual memory management we only keep track for complete 82 * pool 83 */ 84 static void skl_tplg_alloc_pipe_mem(struct skl *skl, 85 struct skl_module_cfg *mconfig) 86 { 87 skl->resource.mem += mconfig->pipe->memory_pages; 88 } 89 90 /* 91 * Pipeline needs needs DSP CPU resources for computation, this is 92 * quantified in MCPS (Million Clocks Per Second) required for module/pipe 93 * 94 * Each pipelines needs mcps to be allocated. Check if we have mcps for this 95 * pipe. 96 */ 97 98 static bool skl_is_pipe_mcps_avail(struct skl *skl, 99 struct skl_module_cfg *mconfig) 100 { 101 struct skl_sst *ctx = skl->skl_sst; 102 103 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) { 104 dev_err(ctx->dev, 105 "%s: module_id %d instance %d\n", __func__, 106 mconfig->id.module_id, mconfig->id.instance_id); 107 dev_err(ctx->dev, 108 "exceeds ppl mcps available %d > mem %d\n", 109 skl->resource.max_mcps, skl->resource.mcps); 110 return false; 111 } else { 112 return true; 113 } 114 } 115 116 static void skl_tplg_alloc_pipe_mcps(struct skl *skl, 117 struct skl_module_cfg *mconfig) 118 { 119 skl->resource.mcps += mconfig->mcps; 120 } 121 122 /* 123 * Free the mcps when tearing down 124 */ 125 static void 126 skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig) 127 { 128 skl->resource.mcps -= mconfig->mcps; 129 } 130 131 /* 132 * Free the memory when tearing down 133 */ 134 static void 135 skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig) 136 { 137 skl->resource.mem -= mconfig->pipe->memory_pages; 138 } 139 140 141 static void skl_dump_mconfig(struct skl_sst *ctx, 142 struct skl_module_cfg *mcfg) 143 { 144 dev_dbg(ctx->dev, "Dumping config\n"); 145 dev_dbg(ctx->dev, "Input Format:\n"); 146 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels); 147 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq); 148 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg); 149 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth); 150 dev_dbg(ctx->dev, "Output Format:\n"); 151 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels); 152 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq); 153 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth); 154 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg); 155 } 156 157 static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs) 158 { 159 int slot_map = 0xFFFFFFFF; 160 int start_slot = 0; 161 int i; 162 163 for (i = 0; i < chs; i++) { 164 /* 165 * For 2 channels with starting slot as 0, slot map will 166 * look like 0xFFFFFF10. 167 */ 168 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i))); 169 start_slot++; 170 } 171 fmt->ch_map = slot_map; 172 } 173 174 static void skl_tplg_update_params(struct skl_module_fmt *fmt, 175 struct skl_pipe_params *params, int fixup) 176 { 177 if (fixup & SKL_RATE_FIXUP_MASK) 178 fmt->s_freq = params->s_freq; 179 if (fixup & SKL_CH_FIXUP_MASK) { 180 fmt->channels = params->ch; 181 skl_tplg_update_chmap(fmt, fmt->channels); 182 } 183 if (fixup & SKL_FMT_FIXUP_MASK) { 184 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt); 185 186 /* 187 * 16 bit is 16 bit container whereas 24 bit is in 32 bit 188 * container so update bit depth accordingly 189 */ 190 switch (fmt->valid_bit_depth) { 191 case SKL_DEPTH_16BIT: 192 fmt->bit_depth = fmt->valid_bit_depth; 193 break; 194 195 default: 196 fmt->bit_depth = SKL_DEPTH_32BIT; 197 break; 198 } 199 } 200 201 } 202 203 /* 204 * A pipeline may have modules which impact the pcm parameters, like SRC, 205 * channel converter, format converter. 206 * We need to calculate the output params by applying the 'fixup' 207 * Topology will tell driver which type of fixup is to be applied by 208 * supplying the fixup mask, so based on that we calculate the output 209 * 210 * Now In FE the pcm hw_params is source/target format. Same is applicable 211 * for BE with its hw_params invoked. 212 * here based on FE, BE pipeline and direction we calculate the input and 213 * outfix and then apply that for a module 214 */ 215 static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg, 216 struct skl_pipe_params *params, bool is_fe) 217 { 218 int in_fixup, out_fixup; 219 struct skl_module_fmt *in_fmt, *out_fmt; 220 221 /* Fixups will be applied to pin 0 only */ 222 in_fmt = &m_cfg->in_fmt[0]; 223 out_fmt = &m_cfg->out_fmt[0]; 224 225 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { 226 if (is_fe) { 227 in_fixup = m_cfg->params_fixup; 228 out_fixup = (~m_cfg->converter) & 229 m_cfg->params_fixup; 230 } else { 231 out_fixup = m_cfg->params_fixup; 232 in_fixup = (~m_cfg->converter) & 233 m_cfg->params_fixup; 234 } 235 } else { 236 if (is_fe) { 237 out_fixup = m_cfg->params_fixup; 238 in_fixup = (~m_cfg->converter) & 239 m_cfg->params_fixup; 240 } else { 241 in_fixup = m_cfg->params_fixup; 242 out_fixup = (~m_cfg->converter) & 243 m_cfg->params_fixup; 244 } 245 } 246 247 skl_tplg_update_params(in_fmt, params, in_fixup); 248 skl_tplg_update_params(out_fmt, params, out_fixup); 249 } 250 251 /* 252 * A module needs input and output buffers, which are dependent upon pcm 253 * params, so once we have calculate params, we need buffer calculation as 254 * well. 255 */ 256 static void skl_tplg_update_buffer_size(struct skl_sst *ctx, 257 struct skl_module_cfg *mcfg) 258 { 259 int multiplier = 1; 260 struct skl_module_fmt *in_fmt, *out_fmt; 261 int in_rate, out_rate; 262 263 264 /* Since fixups is applied to pin 0 only, ibs, obs needs 265 * change for pin 0 only 266 */ 267 in_fmt = &mcfg->in_fmt[0]; 268 out_fmt = &mcfg->out_fmt[0]; 269 270 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT) 271 multiplier = 5; 272 273 if (in_fmt->s_freq % 1000) 274 in_rate = (in_fmt->s_freq / 1000) + 1; 275 else 276 in_rate = (in_fmt->s_freq / 1000); 277 278 mcfg->ibs = in_rate * (mcfg->in_fmt->channels) * 279 (mcfg->in_fmt->bit_depth >> 3) * 280 multiplier; 281 282 if (mcfg->out_fmt->s_freq % 1000) 283 out_rate = (mcfg->out_fmt->s_freq / 1000) + 1; 284 else 285 out_rate = (mcfg->out_fmt->s_freq / 1000); 286 287 mcfg->obs = out_rate * (mcfg->out_fmt->channels) * 288 (mcfg->out_fmt->bit_depth >> 3) * 289 multiplier; 290 } 291 292 static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w, 293 struct skl_sst *ctx) 294 { 295 struct skl_module_cfg *m_cfg = w->priv; 296 int link_type, dir; 297 u32 ch, s_freq, s_fmt; 298 struct nhlt_specific_cfg *cfg; 299 struct skl *skl = get_skl_ctx(ctx->dev); 300 301 /* check if we already have blob */ 302 if (m_cfg->formats_config.caps_size > 0) 303 return 0; 304 305 dev_dbg(ctx->dev, "Applying default cfg blob\n"); 306 switch (m_cfg->dev_type) { 307 case SKL_DEVICE_DMIC: 308 link_type = NHLT_LINK_DMIC; 309 dir = SNDRV_PCM_STREAM_CAPTURE; 310 s_freq = m_cfg->in_fmt[0].s_freq; 311 s_fmt = m_cfg->in_fmt[0].bit_depth; 312 ch = m_cfg->in_fmt[0].channels; 313 break; 314 315 case SKL_DEVICE_I2S: 316 link_type = NHLT_LINK_SSP; 317 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) { 318 dir = SNDRV_PCM_STREAM_PLAYBACK; 319 s_freq = m_cfg->out_fmt[0].s_freq; 320 s_fmt = m_cfg->out_fmt[0].bit_depth; 321 ch = m_cfg->out_fmt[0].channels; 322 } else { 323 dir = SNDRV_PCM_STREAM_CAPTURE; 324 s_freq = m_cfg->in_fmt[0].s_freq; 325 s_fmt = m_cfg->in_fmt[0].bit_depth; 326 ch = m_cfg->in_fmt[0].channels; 327 } 328 break; 329 330 default: 331 return -EINVAL; 332 } 333 334 /* update the blob based on virtual bus_id and default params */ 335 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type, 336 s_fmt, ch, s_freq, dir); 337 if (cfg) { 338 m_cfg->formats_config.caps_size = cfg->size; 339 m_cfg->formats_config.caps = (u32 *) &cfg->caps; 340 } else { 341 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n", 342 m_cfg->vbus_id, link_type, dir); 343 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n", 344 ch, s_freq, s_fmt); 345 return -EIO; 346 } 347 348 return 0; 349 } 350 351 static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w, 352 struct skl_sst *ctx) 353 { 354 struct skl_module_cfg *m_cfg = w->priv; 355 struct skl_pipe_params *params = m_cfg->pipe->p_params; 356 int p_conn_type = m_cfg->pipe->conn_type; 357 bool is_fe; 358 359 if (!m_cfg->params_fixup) 360 return; 361 362 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n", 363 w->name); 364 365 skl_dump_mconfig(ctx, m_cfg); 366 367 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE) 368 is_fe = true; 369 else 370 is_fe = false; 371 372 skl_tplg_update_params_fixup(m_cfg, params, is_fe); 373 skl_tplg_update_buffer_size(ctx, m_cfg); 374 375 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n", 376 w->name); 377 378 skl_dump_mconfig(ctx, m_cfg); 379 } 380 381 /* 382 * some modules can have multiple params set from user control and 383 * need to be set after module is initialized. If set_param flag is 384 * set module params will be done after module is initialised. 385 */ 386 static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w, 387 struct skl_sst *ctx) 388 { 389 int i, ret; 390 struct skl_module_cfg *mconfig = w->priv; 391 const struct snd_kcontrol_new *k; 392 struct soc_bytes_ext *sb; 393 struct skl_algo_data *bc; 394 struct skl_specific_cfg *sp_cfg; 395 396 if (mconfig->formats_config.caps_size > 0 && 397 mconfig->formats_config.set_params == SKL_PARAM_SET) { 398 sp_cfg = &mconfig->formats_config; 399 ret = skl_set_module_params(ctx, sp_cfg->caps, 400 sp_cfg->caps_size, 401 sp_cfg->param_id, mconfig); 402 if (ret < 0) 403 return ret; 404 } 405 406 for (i = 0; i < w->num_kcontrols; i++) { 407 k = &w->kcontrol_news[i]; 408 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { 409 sb = (void *) k->private_value; 410 bc = (struct skl_algo_data *)sb->dobj.private; 411 412 if (bc->set_params == SKL_PARAM_SET) { 413 ret = skl_set_module_params(ctx, 414 (u32 *)bc->params, bc->size, 415 bc->param_id, mconfig); 416 if (ret < 0) 417 return ret; 418 } 419 } 420 } 421 422 return 0; 423 } 424 425 /* 426 * some module param can set from user control and this is required as 427 * when module is initailzed. if module param is required in init it is 428 * identifed by set_param flag. if set_param flag is not set, then this 429 * parameter needs to set as part of module init. 430 */ 431 static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w) 432 { 433 const struct snd_kcontrol_new *k; 434 struct soc_bytes_ext *sb; 435 struct skl_algo_data *bc; 436 struct skl_module_cfg *mconfig = w->priv; 437 int i; 438 439 for (i = 0; i < w->num_kcontrols; i++) { 440 k = &w->kcontrol_news[i]; 441 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { 442 sb = (struct soc_bytes_ext *)k->private_value; 443 bc = (struct skl_algo_data *)sb->dobj.private; 444 445 if (bc->set_params != SKL_PARAM_INIT) 446 continue; 447 448 mconfig->formats_config.caps = (u32 *)&bc->params; 449 mconfig->formats_config.caps_size = bc->size; 450 451 break; 452 } 453 } 454 455 return 0; 456 } 457 458 /* 459 * Inside a pipe instance, we can have various modules. These modules need 460 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by 461 * skl_init_module() routine, so invoke that for all modules in a pipeline 462 */ 463 static int 464 skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe) 465 { 466 struct skl_pipe_module *w_module; 467 struct snd_soc_dapm_widget *w; 468 struct skl_module_cfg *mconfig; 469 struct skl_sst *ctx = skl->skl_sst; 470 int ret = 0; 471 472 list_for_each_entry(w_module, &pipe->w_list, node) { 473 w = w_module->w; 474 mconfig = w->priv; 475 476 /* check resource available */ 477 if (!skl_is_pipe_mcps_avail(skl, mconfig)) 478 return -ENOMEM; 479 480 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) { 481 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp, 482 mconfig->id.module_id, mconfig->guid); 483 if (ret < 0) 484 return ret; 485 486 mconfig->m_state = SKL_MODULE_LOADED; 487 } 488 489 /* update blob if blob is null for be with default value */ 490 skl_tplg_update_be_blob(w, ctx); 491 492 /* 493 * apply fix/conversion to module params based on 494 * FE/BE params 495 */ 496 skl_tplg_update_module_params(w, ctx); 497 498 skl_tplg_set_module_init_data(w); 499 ret = skl_init_module(ctx, mconfig); 500 if (ret < 0) 501 return ret; 502 503 skl_tplg_alloc_pipe_mcps(skl, mconfig); 504 ret = skl_tplg_set_module_params(w, ctx); 505 if (ret < 0) 506 return ret; 507 } 508 509 return 0; 510 } 511 512 static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx, 513 struct skl_pipe *pipe) 514 { 515 struct skl_pipe_module *w_module = NULL; 516 struct skl_module_cfg *mconfig = NULL; 517 518 list_for_each_entry(w_module, &pipe->w_list, node) { 519 mconfig = w_module->w->priv; 520 521 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod && 522 mconfig->m_state > SKL_MODULE_UNINIT) 523 return ctx->dsp->fw_ops.unload_mod(ctx->dsp, 524 mconfig->id.module_id); 525 } 526 527 /* no modules to unload in this path, so return */ 528 return 0; 529 } 530 531 /* 532 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we 533 * need create the pipeline. So we do following: 534 * - check the resources 535 * - Create the pipeline 536 * - Initialize the modules in pipeline 537 * - finally bind all modules together 538 */ 539 static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, 540 struct skl *skl) 541 { 542 int ret; 543 struct skl_module_cfg *mconfig = w->priv; 544 struct skl_pipe_module *w_module; 545 struct skl_pipe *s_pipe = mconfig->pipe; 546 struct skl_module_cfg *src_module = NULL, *dst_module; 547 struct skl_sst *ctx = skl->skl_sst; 548 549 /* check resource available */ 550 if (!skl_is_pipe_mcps_avail(skl, mconfig)) 551 return -EBUSY; 552 553 if (!skl_is_pipe_mem_avail(skl, mconfig)) 554 return -ENOMEM; 555 556 /* 557 * Create a list of modules for pipe. 558 * This list contains modules from source to sink 559 */ 560 ret = skl_create_pipeline(ctx, mconfig->pipe); 561 if (ret < 0) 562 return ret; 563 564 skl_tplg_alloc_pipe_mem(skl, mconfig); 565 skl_tplg_alloc_pipe_mcps(skl, mconfig); 566 567 /* Init all pipe modules from source to sink */ 568 ret = skl_tplg_init_pipe_modules(skl, s_pipe); 569 if (ret < 0) 570 return ret; 571 572 /* Bind modules from source to sink */ 573 list_for_each_entry(w_module, &s_pipe->w_list, node) { 574 dst_module = w_module->w->priv; 575 576 if (src_module == NULL) { 577 src_module = dst_module; 578 continue; 579 } 580 581 ret = skl_bind_modules(ctx, src_module, dst_module); 582 if (ret < 0) 583 return ret; 584 585 src_module = dst_module; 586 } 587 588 return 0; 589 } 590 591 /* 592 * Some modules require params to be set after the module is bound to 593 * all pins connected. 594 * 595 * The module provider initializes set_param flag for such modules and we 596 * send params after binding 597 */ 598 static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w, 599 struct skl_module_cfg *mcfg, struct skl_sst *ctx) 600 { 601 int i, ret; 602 struct skl_module_cfg *mconfig = w->priv; 603 const struct snd_kcontrol_new *k; 604 struct soc_bytes_ext *sb; 605 struct skl_algo_data *bc; 606 struct skl_specific_cfg *sp_cfg; 607 608 /* 609 * check all out/in pins are in bind state. 610 * if so set the module param 611 */ 612 for (i = 0; i < mcfg->max_out_queue; i++) { 613 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE) 614 return 0; 615 } 616 617 for (i = 0; i < mcfg->max_in_queue; i++) { 618 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE) 619 return 0; 620 } 621 622 if (mconfig->formats_config.caps_size > 0 && 623 mconfig->formats_config.set_params == SKL_PARAM_BIND) { 624 sp_cfg = &mconfig->formats_config; 625 ret = skl_set_module_params(ctx, sp_cfg->caps, 626 sp_cfg->caps_size, 627 sp_cfg->param_id, mconfig); 628 if (ret < 0) 629 return ret; 630 } 631 632 for (i = 0; i < w->num_kcontrols; i++) { 633 k = &w->kcontrol_news[i]; 634 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { 635 sb = (void *) k->private_value; 636 bc = (struct skl_algo_data *)sb->dobj.private; 637 638 if (bc->set_params == SKL_PARAM_BIND) { 639 ret = skl_set_module_params(ctx, 640 (u32 *)bc->params, bc->max, 641 bc->param_id, mconfig); 642 if (ret < 0) 643 return ret; 644 } 645 } 646 } 647 648 return 0; 649 } 650 651 static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w, 652 struct skl *skl, 653 struct snd_soc_dapm_widget *src_w, 654 struct skl_module_cfg *src_mconfig) 655 { 656 struct snd_soc_dapm_path *p; 657 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL; 658 struct skl_module_cfg *sink_mconfig; 659 struct skl_sst *ctx = skl->skl_sst; 660 int ret; 661 662 snd_soc_dapm_widget_for_each_sink_path(w, p) { 663 if (!p->connect) 664 continue; 665 666 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name); 667 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name); 668 669 next_sink = p->sink; 670 671 if (!is_skl_dsp_widget_type(p->sink)) 672 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig); 673 674 /* 675 * here we will check widgets in sink pipelines, so that 676 * can be any widgets type and we are only interested if 677 * they are ones used for SKL so check that first 678 */ 679 if ((p->sink->priv != NULL) && 680 is_skl_dsp_widget_type(p->sink)) { 681 682 sink = p->sink; 683 sink_mconfig = sink->priv; 684 685 if (src_mconfig->m_state == SKL_MODULE_UNINIT || 686 sink_mconfig->m_state == SKL_MODULE_UNINIT) 687 continue; 688 689 /* Bind source to sink, mixin is always source */ 690 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig); 691 if (ret) 692 return ret; 693 694 /* set module params after bind */ 695 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx); 696 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx); 697 698 /* Start sinks pipe first */ 699 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) { 700 if (sink_mconfig->pipe->conn_type != 701 SKL_PIPE_CONN_TYPE_FE) 702 ret = skl_run_pipe(ctx, 703 sink_mconfig->pipe); 704 if (ret) 705 return ret; 706 } 707 } 708 } 709 710 if (!sink) 711 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig); 712 713 return 0; 714 } 715 716 /* 717 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA 718 * we need to do following: 719 * - Bind to sink pipeline 720 * Since the sink pipes can be running and we don't get mixer event on 721 * connect for already running mixer, we need to find the sink pipes 722 * here and bind to them. This way dynamic connect works. 723 * - Start sink pipeline, if not running 724 * - Then run current pipe 725 */ 726 static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, 727 struct skl *skl) 728 { 729 struct skl_module_cfg *src_mconfig; 730 struct skl_sst *ctx = skl->skl_sst; 731 int ret = 0; 732 733 src_mconfig = w->priv; 734 735 /* 736 * find which sink it is connected to, bind with the sink, 737 * if sink is not started, start sink pipe first, then start 738 * this pipe 739 */ 740 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig); 741 if (ret) 742 return ret; 743 744 /* Start source pipe last after starting all sinks */ 745 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE) 746 return skl_run_pipe(ctx, src_mconfig->pipe); 747 748 return 0; 749 } 750 751 static struct snd_soc_dapm_widget *skl_get_src_dsp_widget( 752 struct snd_soc_dapm_widget *w, struct skl *skl) 753 { 754 struct snd_soc_dapm_path *p; 755 struct snd_soc_dapm_widget *src_w = NULL; 756 struct skl_sst *ctx = skl->skl_sst; 757 758 snd_soc_dapm_widget_for_each_source_path(w, p) { 759 src_w = p->source; 760 if (!p->connect) 761 continue; 762 763 dev_dbg(ctx->dev, "sink widget=%s\n", w->name); 764 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name); 765 766 /* 767 * here we will check widgets in sink pipelines, so that can 768 * be any widgets type and we are only interested if they are 769 * ones used for SKL so check that first 770 */ 771 if ((p->source->priv != NULL) && 772 is_skl_dsp_widget_type(p->source)) { 773 return p->source; 774 } 775 } 776 777 if (src_w != NULL) 778 return skl_get_src_dsp_widget(src_w, skl); 779 780 return NULL; 781 } 782 783 /* 784 * in the Post-PMU event of mixer we need to do following: 785 * - Check if this pipe is running 786 * - if not, then 787 * - bind this pipeline to its source pipeline 788 * if source pipe is already running, this means it is a dynamic 789 * connection and we need to bind only to that pipe 790 * - start this pipeline 791 */ 792 static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w, 793 struct skl *skl) 794 { 795 int ret = 0; 796 struct snd_soc_dapm_widget *source, *sink; 797 struct skl_module_cfg *src_mconfig, *sink_mconfig; 798 struct skl_sst *ctx = skl->skl_sst; 799 int src_pipe_started = 0; 800 801 sink = w; 802 sink_mconfig = sink->priv; 803 804 /* 805 * If source pipe is already started, that means source is driving 806 * one more sink before this sink got connected, Since source is 807 * started, bind this sink to source and start this pipe. 808 */ 809 source = skl_get_src_dsp_widget(w, skl); 810 if (source != NULL) { 811 src_mconfig = source->priv; 812 sink_mconfig = sink->priv; 813 src_pipe_started = 1; 814 815 /* 816 * check pipe state, then no need to bind or start the 817 * pipe 818 */ 819 if (src_mconfig->pipe->state != SKL_PIPE_STARTED) 820 src_pipe_started = 0; 821 } 822 823 if (src_pipe_started) { 824 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig); 825 if (ret) 826 return ret; 827 828 /* set module params after bind */ 829 skl_tplg_set_module_bind_params(source, src_mconfig, ctx); 830 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx); 831 832 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE) 833 ret = skl_run_pipe(ctx, sink_mconfig->pipe); 834 } 835 836 return ret; 837 } 838 839 /* 840 * in the Pre-PMD event of mixer we need to do following: 841 * - Stop the pipe 842 * - find the source connections and remove that from dapm_path_list 843 * - unbind with source pipelines if still connected 844 */ 845 static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w, 846 struct skl *skl) 847 { 848 struct skl_module_cfg *src_mconfig, *sink_mconfig; 849 int ret = 0, i; 850 struct skl_sst *ctx = skl->skl_sst; 851 852 sink_mconfig = w->priv; 853 854 /* Stop the pipe */ 855 ret = skl_stop_pipe(ctx, sink_mconfig->pipe); 856 if (ret) 857 return ret; 858 859 for (i = 0; i < sink_mconfig->max_in_queue; i++) { 860 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) { 861 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg; 862 if (!src_mconfig) 863 continue; 864 /* 865 * If path_found == 1, that means pmd for source 866 * pipe has not occurred, source is connected to 867 * some other sink. so its responsibility of sink 868 * to unbind itself from source. 869 */ 870 ret = skl_stop_pipe(ctx, src_mconfig->pipe); 871 if (ret < 0) 872 return ret; 873 874 ret = skl_unbind_modules(ctx, 875 src_mconfig, sink_mconfig); 876 } 877 } 878 879 return ret; 880 } 881 882 /* 883 * in the Post-PMD event of mixer we need to do following: 884 * - Free the mcps used 885 * - Free the mem used 886 * - Unbind the modules within the pipeline 887 * - Delete the pipeline (modules are not required to be explicitly 888 * deleted, pipeline delete is enough here 889 */ 890 static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w, 891 struct skl *skl) 892 { 893 struct skl_module_cfg *mconfig = w->priv; 894 struct skl_pipe_module *w_module; 895 struct skl_module_cfg *src_module = NULL, *dst_module; 896 struct skl_sst *ctx = skl->skl_sst; 897 struct skl_pipe *s_pipe = mconfig->pipe; 898 int ret = 0; 899 900 if (s_pipe->state == SKL_PIPE_INVALID) 901 return -EINVAL; 902 903 skl_tplg_free_pipe_mcps(skl, mconfig); 904 skl_tplg_free_pipe_mem(skl, mconfig); 905 906 list_for_each_entry(w_module, &s_pipe->w_list, node) { 907 dst_module = w_module->w->priv; 908 909 if (mconfig->m_state >= SKL_MODULE_INIT_DONE) 910 skl_tplg_free_pipe_mcps(skl, dst_module); 911 if (src_module == NULL) { 912 src_module = dst_module; 913 continue; 914 } 915 916 skl_unbind_modules(ctx, src_module, dst_module); 917 src_module = dst_module; 918 } 919 920 ret = skl_delete_pipe(ctx, mconfig->pipe); 921 922 return skl_tplg_unload_pipe_modules(ctx, s_pipe); 923 } 924 925 /* 926 * in the Post-PMD event of PGA we need to do following: 927 * - Free the mcps used 928 * - Stop the pipeline 929 * - In source pipe is connected, unbind with source pipelines 930 */ 931 static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w, 932 struct skl *skl) 933 { 934 struct skl_module_cfg *src_mconfig, *sink_mconfig; 935 int ret = 0, i; 936 struct skl_sst *ctx = skl->skl_sst; 937 938 src_mconfig = w->priv; 939 940 /* Stop the pipe since this is a mixin module */ 941 ret = skl_stop_pipe(ctx, src_mconfig->pipe); 942 if (ret) 943 return ret; 944 945 for (i = 0; i < src_mconfig->max_out_queue; i++) { 946 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) { 947 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg; 948 if (!sink_mconfig) 949 continue; 950 /* 951 * This is a connecter and if path is found that means 952 * unbind between source and sink has not happened yet 953 */ 954 ret = skl_unbind_modules(ctx, src_mconfig, 955 sink_mconfig); 956 } 957 } 958 959 return ret; 960 } 961 962 /* 963 * In modelling, we assume there will be ONLY one mixer in a pipeline. If 964 * mixer is not required then it is treated as static mixer aka vmixer with 965 * a hard path to source module 966 * So we don't need to check if source is started or not as hard path puts 967 * dependency on each other 968 */ 969 static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w, 970 struct snd_kcontrol *k, int event) 971 { 972 struct snd_soc_dapm_context *dapm = w->dapm; 973 struct skl *skl = get_skl_ctx(dapm->dev); 974 975 switch (event) { 976 case SND_SOC_DAPM_PRE_PMU: 977 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl); 978 979 case SND_SOC_DAPM_POST_PMU: 980 return skl_tplg_mixer_dapm_post_pmu_event(w, skl); 981 982 case SND_SOC_DAPM_PRE_PMD: 983 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl); 984 985 case SND_SOC_DAPM_POST_PMD: 986 return skl_tplg_mixer_dapm_post_pmd_event(w, skl); 987 } 988 989 return 0; 990 } 991 992 /* 993 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a 994 * second one is required that is created as another pipe entity. 995 * The mixer is responsible for pipe management and represent a pipeline 996 * instance 997 */ 998 static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w, 999 struct snd_kcontrol *k, int event) 1000 { 1001 struct snd_soc_dapm_context *dapm = w->dapm; 1002 struct skl *skl = get_skl_ctx(dapm->dev); 1003 1004 switch (event) { 1005 case SND_SOC_DAPM_PRE_PMU: 1006 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl); 1007 1008 case SND_SOC_DAPM_POST_PMU: 1009 return skl_tplg_mixer_dapm_post_pmu_event(w, skl); 1010 1011 case SND_SOC_DAPM_PRE_PMD: 1012 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl); 1013 1014 case SND_SOC_DAPM_POST_PMD: 1015 return skl_tplg_mixer_dapm_post_pmd_event(w, skl); 1016 } 1017 1018 return 0; 1019 } 1020 1021 /* 1022 * In modelling, we assumed rest of the modules in pipeline are PGA. But we 1023 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with 1024 * the sink when it is running (two FE to one BE or one FE to two BE) 1025 * scenarios 1026 */ 1027 static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w, 1028 struct snd_kcontrol *k, int event) 1029 1030 { 1031 struct snd_soc_dapm_context *dapm = w->dapm; 1032 struct skl *skl = get_skl_ctx(dapm->dev); 1033 1034 switch (event) { 1035 case SND_SOC_DAPM_PRE_PMU: 1036 return skl_tplg_pga_dapm_pre_pmu_event(w, skl); 1037 1038 case SND_SOC_DAPM_POST_PMD: 1039 return skl_tplg_pga_dapm_post_pmd_event(w, skl); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol, 1046 unsigned int __user *data, unsigned int size) 1047 { 1048 struct soc_bytes_ext *sb = 1049 (struct soc_bytes_ext *)kcontrol->private_value; 1050 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private; 1051 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); 1052 struct skl_module_cfg *mconfig = w->priv; 1053 struct skl *skl = get_skl_ctx(w->dapm->dev); 1054 1055 if (w->power) 1056 skl_get_module_params(skl->skl_sst, (u32 *)bc->params, 1057 bc->size, bc->param_id, mconfig); 1058 1059 /* decrement size for TLV header */ 1060 size -= 2 * sizeof(u32); 1061 1062 /* check size as we don't want to send kernel data */ 1063 if (size > bc->max) 1064 size = bc->max; 1065 1066 if (bc->params) { 1067 if (copy_to_user(data, &bc->param_id, sizeof(u32))) 1068 return -EFAULT; 1069 if (copy_to_user(data + 1, &size, sizeof(u32))) 1070 return -EFAULT; 1071 if (copy_to_user(data + 2, bc->params, size)) 1072 return -EFAULT; 1073 } 1074 1075 return 0; 1076 } 1077 1078 #define SKL_PARAM_VENDOR_ID 0xff 1079 1080 static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol, 1081 const unsigned int __user *data, unsigned int size) 1082 { 1083 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); 1084 struct skl_module_cfg *mconfig = w->priv; 1085 struct soc_bytes_ext *sb = 1086 (struct soc_bytes_ext *)kcontrol->private_value; 1087 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private; 1088 struct skl *skl = get_skl_ctx(w->dapm->dev); 1089 1090 if (ac->params) { 1091 if (size > ac->max) 1092 return -EINVAL; 1093 1094 ac->size = size; 1095 /* 1096 * if the param_is is of type Vendor, firmware expects actual 1097 * parameter id and size from the control. 1098 */ 1099 if (ac->param_id == SKL_PARAM_VENDOR_ID) { 1100 if (copy_from_user(ac->params, data, size)) 1101 return -EFAULT; 1102 } else { 1103 if (copy_from_user(ac->params, 1104 data + 2, size)) 1105 return -EFAULT; 1106 } 1107 1108 if (w->power) 1109 return skl_set_module_params(skl->skl_sst, 1110 (u32 *)ac->params, ac->size, 1111 ac->param_id, mconfig); 1112 } 1113 1114 return 0; 1115 } 1116 1117 /* 1118 * Fill the dma id for host and link. In case of passthrough 1119 * pipeline, this will both host and link in the same 1120 * pipeline, so need to copy the link and host based on dev_type 1121 */ 1122 static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg, 1123 struct skl_pipe_params *params) 1124 { 1125 struct skl_pipe *pipe = mcfg->pipe; 1126 1127 if (pipe->passthru) { 1128 switch (mcfg->dev_type) { 1129 case SKL_DEVICE_HDALINK: 1130 pipe->p_params->link_dma_id = params->link_dma_id; 1131 break; 1132 1133 case SKL_DEVICE_HDAHOST: 1134 pipe->p_params->host_dma_id = params->host_dma_id; 1135 break; 1136 1137 default: 1138 break; 1139 } 1140 pipe->p_params->s_fmt = params->s_fmt; 1141 pipe->p_params->ch = params->ch; 1142 pipe->p_params->s_freq = params->s_freq; 1143 pipe->p_params->stream = params->stream; 1144 1145 } else { 1146 memcpy(pipe->p_params, params, sizeof(*params)); 1147 } 1148 } 1149 1150 /* 1151 * The FE params are passed by hw_params of the DAI. 1152 * On hw_params, the params are stored in Gateway module of the FE and we 1153 * need to calculate the format in DSP module configuration, that 1154 * conversion is done here 1155 */ 1156 int skl_tplg_update_pipe_params(struct device *dev, 1157 struct skl_module_cfg *mconfig, 1158 struct skl_pipe_params *params) 1159 { 1160 struct skl_module_fmt *format = NULL; 1161 1162 skl_tplg_fill_dma_id(mconfig, params); 1163 1164 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) 1165 format = &mconfig->in_fmt[0]; 1166 else 1167 format = &mconfig->out_fmt[0]; 1168 1169 /* set the hw_params */ 1170 format->s_freq = params->s_freq; 1171 format->channels = params->ch; 1172 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt); 1173 1174 /* 1175 * 16 bit is 16 bit container whereas 24 bit is in 32 bit 1176 * container so update bit depth accordingly 1177 */ 1178 switch (format->valid_bit_depth) { 1179 case SKL_DEPTH_16BIT: 1180 format->bit_depth = format->valid_bit_depth; 1181 break; 1182 1183 case SKL_DEPTH_24BIT: 1184 case SKL_DEPTH_32BIT: 1185 format->bit_depth = SKL_DEPTH_32BIT; 1186 break; 1187 1188 default: 1189 dev_err(dev, "Invalid bit depth %x for pipe\n", 1190 format->valid_bit_depth); 1191 return -EINVAL; 1192 } 1193 1194 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1195 mconfig->ibs = (format->s_freq / 1000) * 1196 (format->channels) * 1197 (format->bit_depth >> 3); 1198 } else { 1199 mconfig->obs = (format->s_freq / 1000) * 1200 (format->channels) * 1201 (format->bit_depth >> 3); 1202 } 1203 1204 return 0; 1205 } 1206 1207 /* 1208 * Query the module config for the FE DAI 1209 * This is used to find the hw_params set for that DAI and apply to FE 1210 * pipeline 1211 */ 1212 struct skl_module_cfg * 1213 skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream) 1214 { 1215 struct snd_soc_dapm_widget *w; 1216 struct snd_soc_dapm_path *p = NULL; 1217 1218 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1219 w = dai->playback_widget; 1220 snd_soc_dapm_widget_for_each_sink_path(w, p) { 1221 if (p->connect && p->sink->power && 1222 !is_skl_dsp_widget_type(p->sink)) 1223 continue; 1224 1225 if (p->sink->priv) { 1226 dev_dbg(dai->dev, "set params for %s\n", 1227 p->sink->name); 1228 return p->sink->priv; 1229 } 1230 } 1231 } else { 1232 w = dai->capture_widget; 1233 snd_soc_dapm_widget_for_each_source_path(w, p) { 1234 if (p->connect && p->source->power && 1235 !is_skl_dsp_widget_type(p->source)) 1236 continue; 1237 1238 if (p->source->priv) { 1239 dev_dbg(dai->dev, "set params for %s\n", 1240 p->source->name); 1241 return p->source->priv; 1242 } 1243 } 1244 } 1245 1246 return NULL; 1247 } 1248 1249 static struct skl_module_cfg *skl_get_mconfig_pb_cpr( 1250 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w) 1251 { 1252 struct snd_soc_dapm_path *p; 1253 struct skl_module_cfg *mconfig = NULL; 1254 1255 snd_soc_dapm_widget_for_each_source_path(w, p) { 1256 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) { 1257 if (p->connect && 1258 (p->sink->id == snd_soc_dapm_aif_out) && 1259 p->source->priv) { 1260 mconfig = p->source->priv; 1261 return mconfig; 1262 } 1263 mconfig = skl_get_mconfig_pb_cpr(dai, p->source); 1264 if (mconfig) 1265 return mconfig; 1266 } 1267 } 1268 return mconfig; 1269 } 1270 1271 static struct skl_module_cfg *skl_get_mconfig_cap_cpr( 1272 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w) 1273 { 1274 struct snd_soc_dapm_path *p; 1275 struct skl_module_cfg *mconfig = NULL; 1276 1277 snd_soc_dapm_widget_for_each_sink_path(w, p) { 1278 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) { 1279 if (p->connect && 1280 (p->source->id == snd_soc_dapm_aif_in) && 1281 p->sink->priv) { 1282 mconfig = p->sink->priv; 1283 return mconfig; 1284 } 1285 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink); 1286 if (mconfig) 1287 return mconfig; 1288 } 1289 } 1290 return mconfig; 1291 } 1292 1293 struct skl_module_cfg * 1294 skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream) 1295 { 1296 struct snd_soc_dapm_widget *w; 1297 struct skl_module_cfg *mconfig; 1298 1299 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1300 w = dai->playback_widget; 1301 mconfig = skl_get_mconfig_pb_cpr(dai, w); 1302 } else { 1303 w = dai->capture_widget; 1304 mconfig = skl_get_mconfig_cap_cpr(dai, w); 1305 } 1306 return mconfig; 1307 } 1308 1309 static u8 skl_tplg_be_link_type(int dev_type) 1310 { 1311 int ret; 1312 1313 switch (dev_type) { 1314 case SKL_DEVICE_BT: 1315 ret = NHLT_LINK_SSP; 1316 break; 1317 1318 case SKL_DEVICE_DMIC: 1319 ret = NHLT_LINK_DMIC; 1320 break; 1321 1322 case SKL_DEVICE_I2S: 1323 ret = NHLT_LINK_SSP; 1324 break; 1325 1326 case SKL_DEVICE_HDALINK: 1327 ret = NHLT_LINK_HDA; 1328 break; 1329 1330 default: 1331 ret = NHLT_LINK_INVALID; 1332 break; 1333 } 1334 1335 return ret; 1336 } 1337 1338 /* 1339 * Fill the BE gateway parameters 1340 * The BE gateway expects a blob of parameters which are kept in the ACPI 1341 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance. 1342 * The port can have multiple settings so pick based on the PCM 1343 * parameters 1344 */ 1345 static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai, 1346 struct skl_module_cfg *mconfig, 1347 struct skl_pipe_params *params) 1348 { 1349 struct nhlt_specific_cfg *cfg; 1350 struct skl *skl = get_skl_ctx(dai->dev); 1351 int link_type = skl_tplg_be_link_type(mconfig->dev_type); 1352 1353 skl_tplg_fill_dma_id(mconfig, params); 1354 1355 if (link_type == NHLT_LINK_HDA) 1356 return 0; 1357 1358 /* update the blob based on virtual bus_id*/ 1359 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type, 1360 params->s_fmt, params->ch, 1361 params->s_freq, params->stream); 1362 if (cfg) { 1363 mconfig->formats_config.caps_size = cfg->size; 1364 mconfig->formats_config.caps = (u32 *) &cfg->caps; 1365 } else { 1366 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n", 1367 mconfig->vbus_id, link_type, 1368 params->stream); 1369 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n", 1370 params->ch, params->s_freq, params->s_fmt); 1371 return -EINVAL; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai, 1378 struct snd_soc_dapm_widget *w, 1379 struct skl_pipe_params *params) 1380 { 1381 struct snd_soc_dapm_path *p; 1382 int ret = -EIO; 1383 1384 snd_soc_dapm_widget_for_each_source_path(w, p) { 1385 if (p->connect && is_skl_dsp_widget_type(p->source) && 1386 p->source->priv) { 1387 1388 ret = skl_tplg_be_fill_pipe_params(dai, 1389 p->source->priv, params); 1390 if (ret < 0) 1391 return ret; 1392 } else { 1393 ret = skl_tplg_be_set_src_pipe_params(dai, 1394 p->source, params); 1395 if (ret < 0) 1396 return ret; 1397 } 1398 } 1399 1400 return ret; 1401 } 1402 1403 static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai, 1404 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params) 1405 { 1406 struct snd_soc_dapm_path *p = NULL; 1407 int ret = -EIO; 1408 1409 snd_soc_dapm_widget_for_each_sink_path(w, p) { 1410 if (p->connect && is_skl_dsp_widget_type(p->sink) && 1411 p->sink->priv) { 1412 1413 ret = skl_tplg_be_fill_pipe_params(dai, 1414 p->sink->priv, params); 1415 if (ret < 0) 1416 return ret; 1417 } else { 1418 ret = skl_tplg_be_set_sink_pipe_params( 1419 dai, p->sink, params); 1420 if (ret < 0) 1421 return ret; 1422 } 1423 } 1424 1425 return ret; 1426 } 1427 1428 /* 1429 * BE hw_params can be a source parameters (capture) or sink parameters 1430 * (playback). Based on sink and source we need to either find the source 1431 * list or the sink list and set the pipeline parameters 1432 */ 1433 int skl_tplg_be_update_params(struct snd_soc_dai *dai, 1434 struct skl_pipe_params *params) 1435 { 1436 struct snd_soc_dapm_widget *w; 1437 1438 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1439 w = dai->playback_widget; 1440 1441 return skl_tplg_be_set_src_pipe_params(dai, w, params); 1442 1443 } else { 1444 w = dai->capture_widget; 1445 1446 return skl_tplg_be_set_sink_pipe_params(dai, w, params); 1447 } 1448 1449 return 0; 1450 } 1451 1452 static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = { 1453 {SKL_MIXER_EVENT, skl_tplg_mixer_event}, 1454 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event}, 1455 {SKL_PGA_EVENT, skl_tplg_pga_event}, 1456 }; 1457 1458 static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = { 1459 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get, 1460 skl_tplg_tlv_control_set}, 1461 }; 1462 1463 /* 1464 * The topology binary passes the pin info for a module so initialize the pin 1465 * info passed into module instance 1466 */ 1467 static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin, 1468 struct skl_module_pin *m_pin, 1469 bool is_dynamic, int max_pin) 1470 { 1471 int i; 1472 1473 for (i = 0; i < max_pin; i++) { 1474 m_pin[i].id.module_id = dfw_pin[i].module_id; 1475 m_pin[i].id.instance_id = dfw_pin[i].instance_id; 1476 m_pin[i].in_use = false; 1477 m_pin[i].is_dynamic = is_dynamic; 1478 m_pin[i].pin_state = SKL_PIN_UNBIND; 1479 } 1480 } 1481 1482 /* 1483 * Add pipeline from topology binary into driver pipeline list 1484 * 1485 * If already added we return that instance 1486 * Otherwise we create a new instance and add into driver list 1487 */ 1488 static struct skl_pipe *skl_tplg_add_pipe(struct device *dev, 1489 struct skl *skl, struct skl_dfw_pipe *dfw_pipe) 1490 { 1491 struct skl_pipeline *ppl; 1492 struct skl_pipe *pipe; 1493 struct skl_pipe_params *params; 1494 1495 list_for_each_entry(ppl, &skl->ppl_list, node) { 1496 if (ppl->pipe->ppl_id == dfw_pipe->pipe_id) 1497 return ppl->pipe; 1498 } 1499 1500 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL); 1501 if (!ppl) 1502 return NULL; 1503 1504 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL); 1505 if (!pipe) 1506 return NULL; 1507 1508 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL); 1509 if (!params) 1510 return NULL; 1511 1512 pipe->ppl_id = dfw_pipe->pipe_id; 1513 pipe->memory_pages = dfw_pipe->memory_pages; 1514 pipe->pipe_priority = dfw_pipe->pipe_priority; 1515 pipe->conn_type = dfw_pipe->conn_type; 1516 pipe->state = SKL_PIPE_INVALID; 1517 pipe->p_params = params; 1518 INIT_LIST_HEAD(&pipe->w_list); 1519 1520 ppl->pipe = pipe; 1521 list_add(&ppl->node, &skl->ppl_list); 1522 1523 return ppl->pipe; 1524 } 1525 1526 static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt, 1527 struct skl_dfw_module_fmt *src_fmt, 1528 int pins) 1529 { 1530 int i; 1531 1532 for (i = 0; i < pins; i++) { 1533 dst_fmt[i].channels = src_fmt[i].channels; 1534 dst_fmt[i].s_freq = src_fmt[i].freq; 1535 dst_fmt[i].bit_depth = src_fmt[i].bit_depth; 1536 dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth; 1537 dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg; 1538 dst_fmt[i].ch_map = src_fmt[i].ch_map; 1539 dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style; 1540 dst_fmt[i].sample_type = src_fmt[i].sample_type; 1541 } 1542 } 1543 1544 static void skl_clear_pin_config(struct snd_soc_platform *platform, 1545 struct snd_soc_dapm_widget *w) 1546 { 1547 int i; 1548 struct skl_module_cfg *mconfig; 1549 struct skl_pipe *pipe; 1550 1551 if (!strncmp(w->dapm->component->name, platform->component.name, 1552 strlen(platform->component.name))) { 1553 mconfig = w->priv; 1554 pipe = mconfig->pipe; 1555 for (i = 0; i < mconfig->max_in_queue; i++) { 1556 mconfig->m_in_pin[i].in_use = false; 1557 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND; 1558 } 1559 for (i = 0; i < mconfig->max_out_queue; i++) { 1560 mconfig->m_out_pin[i].in_use = false; 1561 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND; 1562 } 1563 pipe->state = SKL_PIPE_INVALID; 1564 mconfig->m_state = SKL_MODULE_UNINIT; 1565 } 1566 } 1567 1568 void skl_cleanup_resources(struct skl *skl) 1569 { 1570 struct skl_sst *ctx = skl->skl_sst; 1571 struct snd_soc_platform *soc_platform = skl->platform; 1572 struct snd_soc_dapm_widget *w; 1573 struct snd_soc_card *card; 1574 1575 if (soc_platform == NULL) 1576 return; 1577 1578 card = soc_platform->component.card; 1579 if (!card || !card->instantiated) 1580 return; 1581 1582 skl->resource.mem = 0; 1583 skl->resource.mcps = 0; 1584 1585 list_for_each_entry(w, &card->widgets, list) { 1586 if (is_skl_dsp_widget_type(w) && (w->priv != NULL)) 1587 skl_clear_pin_config(soc_platform, w); 1588 } 1589 1590 skl_clear_module_cnt(ctx->dsp); 1591 } 1592 1593 /* 1594 * Topology core widget load callback 1595 * 1596 * This is used to save the private data for each widget which gives 1597 * information to the driver about module and pipeline parameters which DSP 1598 * FW expects like ids, resource values, formats etc 1599 */ 1600 static int skl_tplg_widget_load(struct snd_soc_component *cmpnt, 1601 struct snd_soc_dapm_widget *w, 1602 struct snd_soc_tplg_dapm_widget *tplg_w) 1603 { 1604 int ret; 1605 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt); 1606 struct skl *skl = ebus_to_skl(ebus); 1607 struct hdac_bus *bus = ebus_to_hbus(ebus); 1608 struct skl_module_cfg *mconfig; 1609 struct skl_pipe *pipe; 1610 struct skl_dfw_module *dfw_config = 1611 (struct skl_dfw_module *)tplg_w->priv.data; 1612 1613 if (!tplg_w->priv.size) 1614 goto bind_event; 1615 1616 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL); 1617 1618 if (!mconfig) 1619 return -ENOMEM; 1620 1621 w->priv = mconfig; 1622 memcpy(&mconfig->guid, &dfw_config->uuid, 16); 1623 1624 ret = snd_skl_get_module_info(skl->skl_sst, mconfig->guid, dfw_config); 1625 if (ret < 0) 1626 return ret; 1627 1628 mconfig->id.module_id = dfw_config->module_id; 1629 mconfig->id.instance_id = dfw_config->instance_id; 1630 mconfig->mcps = dfw_config->max_mcps; 1631 mconfig->ibs = dfw_config->ibs; 1632 mconfig->obs = dfw_config->obs; 1633 mconfig->core_id = dfw_config->core_id; 1634 mconfig->max_in_queue = dfw_config->max_in_queue; 1635 mconfig->max_out_queue = dfw_config->max_out_queue; 1636 mconfig->is_loadable = dfw_config->is_loadable; 1637 skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt, 1638 MODULE_MAX_IN_PINS); 1639 skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt, 1640 MODULE_MAX_OUT_PINS); 1641 1642 mconfig->params_fixup = dfw_config->params_fixup; 1643 mconfig->converter = dfw_config->converter; 1644 mconfig->m_type = dfw_config->module_type; 1645 mconfig->vbus_id = dfw_config->vbus_id; 1646 mconfig->mem_pages = dfw_config->mem_pages; 1647 1648 pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe); 1649 if (pipe) 1650 mconfig->pipe = pipe; 1651 1652 mconfig->dev_type = dfw_config->dev_type; 1653 mconfig->hw_conn_type = dfw_config->hw_conn_type; 1654 mconfig->time_slot = dfw_config->time_slot; 1655 mconfig->formats_config.caps_size = dfw_config->caps.caps_size; 1656 1657 mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) * 1658 sizeof(*mconfig->m_in_pin), 1659 GFP_KERNEL); 1660 if (!mconfig->m_in_pin) 1661 return -ENOMEM; 1662 1663 mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) * 1664 sizeof(*mconfig->m_out_pin), 1665 GFP_KERNEL); 1666 if (!mconfig->m_out_pin) 1667 return -ENOMEM; 1668 1669 skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin, 1670 dfw_config->is_dynamic_in_pin, 1671 mconfig->max_in_queue); 1672 1673 skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin, 1674 dfw_config->is_dynamic_out_pin, 1675 mconfig->max_out_queue); 1676 1677 1678 if (mconfig->formats_config.caps_size == 0) 1679 goto bind_event; 1680 1681 mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev, 1682 mconfig->formats_config.caps_size, GFP_KERNEL); 1683 1684 if (mconfig->formats_config.caps == NULL) 1685 return -ENOMEM; 1686 1687 memcpy(mconfig->formats_config.caps, dfw_config->caps.caps, 1688 dfw_config->caps.caps_size); 1689 mconfig->formats_config.param_id = dfw_config->caps.param_id; 1690 mconfig->formats_config.set_params = dfw_config->caps.set_params; 1691 1692 bind_event: 1693 if (tplg_w->event_type == 0) { 1694 dev_dbg(bus->dev, "ASoC: No event handler required\n"); 1695 return 0; 1696 } 1697 1698 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops, 1699 ARRAY_SIZE(skl_tplg_widget_ops), 1700 tplg_w->event_type); 1701 1702 if (ret) { 1703 dev_err(bus->dev, "%s: No matching event handlers found for %d\n", 1704 __func__, tplg_w->event_type); 1705 return -EINVAL; 1706 } 1707 1708 return 0; 1709 } 1710 1711 static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be, 1712 struct snd_soc_tplg_bytes_control *bc) 1713 { 1714 struct skl_algo_data *ac; 1715 struct skl_dfw_algo_data *dfw_ac = 1716 (struct skl_dfw_algo_data *)bc->priv.data; 1717 1718 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL); 1719 if (!ac) 1720 return -ENOMEM; 1721 1722 /* Fill private data */ 1723 ac->max = dfw_ac->max; 1724 ac->param_id = dfw_ac->param_id; 1725 ac->set_params = dfw_ac->set_params; 1726 ac->size = dfw_ac->max; 1727 1728 if (ac->max) { 1729 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL); 1730 if (!ac->params) 1731 return -ENOMEM; 1732 1733 memcpy(ac->params, dfw_ac->params, ac->max); 1734 } 1735 1736 be->dobj.private = ac; 1737 return 0; 1738 } 1739 1740 static int skl_tplg_control_load(struct snd_soc_component *cmpnt, 1741 struct snd_kcontrol_new *kctl, 1742 struct snd_soc_tplg_ctl_hdr *hdr) 1743 { 1744 struct soc_bytes_ext *sb; 1745 struct snd_soc_tplg_bytes_control *tplg_bc; 1746 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt); 1747 struct hdac_bus *bus = ebus_to_hbus(ebus); 1748 1749 switch (hdr->ops.info) { 1750 case SND_SOC_TPLG_CTL_BYTES: 1751 tplg_bc = container_of(hdr, 1752 struct snd_soc_tplg_bytes_control, hdr); 1753 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { 1754 sb = (struct soc_bytes_ext *)kctl->private_value; 1755 if (tplg_bc->priv.size) 1756 return skl_init_algo_data( 1757 bus->dev, sb, tplg_bc); 1758 } 1759 break; 1760 1761 default: 1762 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n", 1763 hdr->ops.get, hdr->ops.put, hdr->ops.info); 1764 break; 1765 } 1766 1767 return 0; 1768 } 1769 1770 static struct snd_soc_tplg_ops skl_tplg_ops = { 1771 .widget_load = skl_tplg_widget_load, 1772 .control_load = skl_tplg_control_load, 1773 .bytes_ext_ops = skl_tlv_ops, 1774 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops), 1775 }; 1776 1777 /* 1778 * A pipe can have multiple modules, each of them will be a DAPM widget as 1779 * well. While managing a pipeline we need to get the list of all the 1780 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list() 1781 * helps to get the SKL type widgets in that pipeline 1782 */ 1783 static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform) 1784 { 1785 struct snd_soc_dapm_widget *w; 1786 struct skl_module_cfg *mcfg = NULL; 1787 struct skl_pipe_module *p_module = NULL; 1788 struct skl_pipe *pipe; 1789 1790 list_for_each_entry(w, &platform->component.card->widgets, list) { 1791 if (is_skl_dsp_widget_type(w) && w->priv != NULL) { 1792 mcfg = w->priv; 1793 pipe = mcfg->pipe; 1794 1795 p_module = devm_kzalloc(platform->dev, 1796 sizeof(*p_module), GFP_KERNEL); 1797 if (!p_module) 1798 return -ENOMEM; 1799 1800 p_module->w = w; 1801 list_add_tail(&p_module->node, &pipe->w_list); 1802 } 1803 } 1804 1805 return 0; 1806 } 1807 1808 static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe) 1809 { 1810 struct skl_pipe_module *w_module; 1811 struct snd_soc_dapm_widget *w; 1812 struct skl_module_cfg *mconfig; 1813 bool host_found = false, link_found = false; 1814 1815 list_for_each_entry(w_module, &pipe->w_list, node) { 1816 w = w_module->w; 1817 mconfig = w->priv; 1818 1819 if (mconfig->dev_type == SKL_DEVICE_HDAHOST) 1820 host_found = true; 1821 else if (mconfig->dev_type != SKL_DEVICE_NONE) 1822 link_found = true; 1823 } 1824 1825 if (host_found && link_found) 1826 pipe->passthru = true; 1827 else 1828 pipe->passthru = false; 1829 } 1830 1831 /* This will be read from topology manifest, currently defined here */ 1832 #define SKL_MAX_MCPS 30000000 1833 #define SKL_FW_MAX_MEM 1000000 1834 1835 /* 1836 * SKL topology init routine 1837 */ 1838 int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus) 1839 { 1840 int ret; 1841 const struct firmware *fw; 1842 struct hdac_bus *bus = ebus_to_hbus(ebus); 1843 struct skl *skl = ebus_to_skl(ebus); 1844 struct skl_pipeline *ppl; 1845 1846 ret = request_firmware(&fw, skl->tplg_name, bus->dev); 1847 if (ret < 0) { 1848 dev_err(bus->dev, "tplg fw %s load failed with %d\n", 1849 skl->tplg_name, ret); 1850 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev); 1851 if (ret < 0) { 1852 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n", 1853 "dfw_sst.bin", ret); 1854 return ret; 1855 } 1856 } 1857 1858 /* 1859 * The complete tplg for SKL is loaded as index 0, we don't use 1860 * any other index 1861 */ 1862 ret = snd_soc_tplg_component_load(&platform->component, 1863 &skl_tplg_ops, fw, 0); 1864 if (ret < 0) { 1865 dev_err(bus->dev, "tplg component load failed%d\n", ret); 1866 release_firmware(fw); 1867 return -EINVAL; 1868 } 1869 1870 skl->resource.max_mcps = SKL_MAX_MCPS; 1871 skl->resource.max_mem = SKL_FW_MAX_MEM; 1872 1873 skl->tplg = fw; 1874 ret = skl_tplg_create_pipe_widget_list(platform); 1875 if (ret < 0) 1876 return ret; 1877 1878 list_for_each_entry(ppl, &skl->ppl_list, node) 1879 skl_tplg_set_pipe_type(skl, ppl->pipe); 1880 1881 return 0; 1882 } 1883