1 /* 2 * skl-sst.c - HDA DSP library functions for SKL platform 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 6 * Jeeja KP <jeeja.kp@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/delay.h> 21 #include <linux/device.h> 22 #include "../common/sst-dsp.h" 23 #include "../common/sst-dsp-priv.h" 24 #include "../common/sst-ipc.h" 25 #include "skl-sst-ipc.h" 26 27 #define SKL_BASEFW_TIMEOUT 300 28 #define SKL_INIT_TIMEOUT 1000 29 30 /* Intel HD Audio SRAM Window 0*/ 31 #define SKL_ADSP_SRAM0_BASE 0x8000 32 33 /* Firmware status window */ 34 #define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE 35 #define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4) 36 37 #define SKL_INSTANCE_ID 0 38 #define SKL_BASE_FW_MODULE_ID 0 39 40 static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status) 41 { 42 u32 cur_sts; 43 44 cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK; 45 46 return (cur_sts == status); 47 } 48 49 static int skl_transfer_firmware(struct sst_dsp *ctx, 50 const void *basefw, u32 base_fw_size) 51 { 52 int ret = 0; 53 54 ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size); 55 if (ret < 0) 56 return ret; 57 58 ret = sst_dsp_register_poll(ctx, 59 SKL_ADSP_FW_STATUS, 60 SKL_FW_STS_MASK, 61 SKL_FW_RFW_START, 62 SKL_BASEFW_TIMEOUT, 63 "Firmware boot"); 64 65 ctx->cl_dev.ops.cl_stop_dma(ctx); 66 67 return ret; 68 } 69 70 static int skl_load_base_firmware(struct sst_dsp *ctx) 71 { 72 int ret = 0, i; 73 const struct firmware *fw = NULL; 74 struct skl_sst *skl = ctx->thread_context; 75 u32 reg; 76 77 ret = request_firmware(&fw, "dsp_fw_release.bin", ctx->dev); 78 if (ret < 0) { 79 dev_err(ctx->dev, "Request firmware failed %d\n", ret); 80 skl_dsp_disable_core(ctx); 81 return -EIO; 82 } 83 84 /* enable Interrupt */ 85 skl_ipc_int_enable(ctx); 86 skl_ipc_op_int_enable(ctx); 87 88 /* check ROM Status */ 89 for (i = SKL_INIT_TIMEOUT; i > 0; --i) { 90 if (skl_check_fw_status(ctx, SKL_FW_INIT)) { 91 dev_dbg(ctx->dev, 92 "ROM loaded, we can continue with FW loading\n"); 93 break; 94 } 95 mdelay(1); 96 } 97 if (!i) { 98 reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS); 99 dev_err(ctx->dev, 100 "Timeout waiting for ROM init done, reg:0x%x\n", reg); 101 ret = -EIO; 102 goto skl_load_base_firmware_failed; 103 } 104 105 ret = skl_transfer_firmware(ctx, fw->data, fw->size); 106 if (ret < 0) { 107 dev_err(ctx->dev, "Transfer firmware failed%d\n", ret); 108 goto skl_load_base_firmware_failed; 109 } else { 110 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 111 msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 112 if (ret == 0) { 113 dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n"); 114 ret = -EIO; 115 goto skl_load_base_firmware_failed; 116 } 117 118 dev_dbg(ctx->dev, "Download firmware successful%d\n", ret); 119 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 120 } 121 release_firmware(fw); 122 123 return 0; 124 125 skl_load_base_firmware_failed: 126 skl_dsp_disable_core(ctx); 127 release_firmware(fw); 128 return ret; 129 } 130 131 static int skl_set_dsp_D0(struct sst_dsp *ctx) 132 { 133 int ret; 134 135 ret = skl_load_base_firmware(ctx); 136 if (ret < 0) { 137 dev_err(ctx->dev, "unable to load firmware\n"); 138 return ret; 139 } 140 141 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 142 143 return ret; 144 } 145 146 static int skl_set_dsp_D3(struct sst_dsp *ctx) 147 { 148 int ret; 149 struct skl_ipc_dxstate_info dx; 150 struct skl_sst *skl = ctx->thread_context; 151 152 dev_dbg(ctx->dev, "In %s:\n", __func__); 153 mutex_lock(&ctx->mutex); 154 if (!is_skl_dsp_running(ctx)) { 155 mutex_unlock(&ctx->mutex); 156 return 0; 157 } 158 mutex_unlock(&ctx->mutex); 159 160 dx.core_mask = SKL_DSP_CORE0_MASK; 161 dx.dx_mask = SKL_IPC_D3_MASK; 162 ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx); 163 if (ret < 0) { 164 dev_err(ctx->dev, "Failed to set DSP to D3 state\n"); 165 return ret; 166 } 167 168 ret = skl_dsp_disable_core(ctx); 169 if (ret < 0) { 170 dev_err(ctx->dev, "disable dsp core failed ret: %d\n", ret); 171 ret = -EIO; 172 } 173 skl_dsp_set_state_locked(ctx, SKL_DSP_RESET); 174 175 return ret; 176 } 177 178 static unsigned int skl_get_errorcode(struct sst_dsp *ctx) 179 { 180 return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE); 181 } 182 183 static struct skl_dsp_fw_ops skl_fw_ops = { 184 .set_state_D0 = skl_set_dsp_D0, 185 .set_state_D3 = skl_set_dsp_D3, 186 .load_fw = skl_load_base_firmware, 187 .get_fw_errcode = skl_get_errorcode, 188 }; 189 190 static struct sst_ops skl_ops = { 191 .irq_handler = skl_dsp_sst_interrupt, 192 .write = sst_shim32_write, 193 .read = sst_shim32_read, 194 .ram_read = sst_memcpy_fromio_32, 195 .ram_write = sst_memcpy_toio_32, 196 .free = skl_dsp_free, 197 }; 198 199 static struct sst_dsp_device skl_dev = { 200 .thread = skl_dsp_irq_thread_handler, 201 .ops = &skl_ops, 202 }; 203 204 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 205 struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp) 206 { 207 struct skl_sst *skl; 208 struct sst_dsp *sst; 209 int ret; 210 211 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 212 if (skl == NULL) 213 return -ENOMEM; 214 215 skl->dev = dev; 216 skl_dev.thread_context = skl; 217 218 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 219 if (!skl->dsp) { 220 dev_err(skl->dev, "%s: no device\n", __func__); 221 return -ENODEV; 222 } 223 224 sst = skl->dsp; 225 226 sst->addr.lpe = mmio_base; 227 sst->addr.shim = mmio_base; 228 sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 229 SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 230 231 sst->dsp_ops = dsp_ops; 232 sst->fw_ops = skl_fw_ops; 233 234 ret = skl_ipc_init(dev, skl); 235 if (ret) 236 return ret; 237 238 skl->boot_complete = false; 239 init_waitqueue_head(&skl->boot_wait); 240 241 ret = skl_dsp_boot(sst); 242 if (ret < 0) { 243 dev_err(skl->dev, "Boot dsp core failed ret: %d", ret); 244 goto free_ipc; 245 } 246 247 ret = skl_cldma_prepare(sst); 248 if (ret < 0) { 249 dev_err(dev, "CL dma prepare failed : %d", ret); 250 goto free_ipc; 251 } 252 253 254 ret = sst->fw_ops.load_fw(sst); 255 if (ret < 0) { 256 dev_err(dev, "Load base fw failed : %d", ret); 257 return ret; 258 } 259 260 if (dsp) 261 *dsp = skl; 262 263 return 0; 264 265 free_ipc: 266 skl_ipc_free(&skl->ipc); 267 return ret; 268 } 269 EXPORT_SYMBOL_GPL(skl_sst_dsp_init); 270 271 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 272 { 273 skl_ipc_free(&ctx->ipc); 274 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 275 ctx->dsp->ops->free(ctx->dsp); 276 } 277 EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup); 278 279 MODULE_LICENSE("GPL v2"); 280 MODULE_DESCRIPTION("Intel Skylake IPC driver"); 281