1 /* 2 * skl-sst.c - HDA DSP library functions for SKL platform 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 6 * Jeeja KP <jeeja.kp@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/delay.h> 21 #include <linux/device.h> 22 #include "../common/sst-dsp.h" 23 #include "../common/sst-dsp-priv.h" 24 #include "../common/sst-ipc.h" 25 #include "skl-sst-ipc.h" 26 27 #define SKL_BASEFW_TIMEOUT 300 28 #define SKL_INIT_TIMEOUT 1000 29 30 /* Intel HD Audio SRAM Window 0*/ 31 #define SKL_ADSP_SRAM0_BASE 0x8000 32 33 /* Firmware status window */ 34 #define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE 35 #define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4) 36 37 #define SKL_INSTANCE_ID 0 38 #define SKL_BASE_FW_MODULE_ID 0 39 40 static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status) 41 { 42 u32 cur_sts; 43 44 cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK; 45 46 return (cur_sts == status); 47 } 48 49 static int skl_transfer_firmware(struct sst_dsp *ctx, 50 const void *basefw, u32 base_fw_size) 51 { 52 int ret = 0; 53 54 ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size); 55 if (ret < 0) 56 return ret; 57 58 ret = sst_dsp_register_poll(ctx, 59 SKL_ADSP_FW_STATUS, 60 SKL_FW_STS_MASK, 61 SKL_FW_RFW_START, 62 SKL_BASEFW_TIMEOUT, 63 "Firmware boot"); 64 65 ctx->cl_dev.ops.cl_stop_dma(ctx); 66 67 return ret; 68 } 69 70 static int skl_load_base_firmware(struct sst_dsp *ctx) 71 { 72 int ret = 0, i; 73 struct skl_sst *skl = ctx->thread_context; 74 u32 reg; 75 76 skl->boot_complete = false; 77 init_waitqueue_head(&skl->boot_wait); 78 79 if (ctx->fw == NULL) { 80 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 81 if (ret < 0) { 82 dev_err(ctx->dev, "Request firmware failed %d\n", ret); 83 skl_dsp_disable_core(ctx); 84 return -EIO; 85 } 86 } 87 88 ret = skl_dsp_boot(ctx); 89 if (ret < 0) { 90 dev_err(ctx->dev, "Boot dsp core failed ret: %d", ret); 91 goto skl_load_base_firmware_failed; 92 } 93 94 ret = skl_cldma_prepare(ctx); 95 if (ret < 0) { 96 dev_err(ctx->dev, "CL dma prepare failed : %d", ret); 97 goto skl_load_base_firmware_failed; 98 } 99 100 /* enable Interrupt */ 101 skl_ipc_int_enable(ctx); 102 skl_ipc_op_int_enable(ctx); 103 104 /* check ROM Status */ 105 for (i = SKL_INIT_TIMEOUT; i > 0; --i) { 106 if (skl_check_fw_status(ctx, SKL_FW_INIT)) { 107 dev_dbg(ctx->dev, 108 "ROM loaded, we can continue with FW loading\n"); 109 break; 110 } 111 mdelay(1); 112 } 113 if (!i) { 114 reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS); 115 dev_err(ctx->dev, 116 "Timeout waiting for ROM init done, reg:0x%x\n", reg); 117 ret = -EIO; 118 goto transfer_firmware_failed; 119 } 120 121 ret = skl_transfer_firmware(ctx, ctx->fw->data, ctx->fw->size); 122 if (ret < 0) { 123 dev_err(ctx->dev, "Transfer firmware failed%d\n", ret); 124 goto transfer_firmware_failed; 125 } else { 126 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 127 msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 128 if (ret == 0) { 129 dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n"); 130 ret = -EIO; 131 goto transfer_firmware_failed; 132 } 133 134 dev_dbg(ctx->dev, "Download firmware successful%d\n", ret); 135 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 136 } 137 return 0; 138 transfer_firmware_failed: 139 ctx->cl_dev.ops.cl_cleanup_controller(ctx); 140 skl_load_base_firmware_failed: 141 skl_dsp_disable_core(ctx); 142 release_firmware(ctx->fw); 143 ctx->fw = NULL; 144 return ret; 145 } 146 147 static int skl_set_dsp_D0(struct sst_dsp *ctx) 148 { 149 int ret; 150 151 ret = skl_load_base_firmware(ctx); 152 if (ret < 0) { 153 dev_err(ctx->dev, "unable to load firmware\n"); 154 return ret; 155 } 156 157 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 158 159 return ret; 160 } 161 162 static int skl_set_dsp_D3(struct sst_dsp *ctx) 163 { 164 int ret; 165 struct skl_ipc_dxstate_info dx; 166 struct skl_sst *skl = ctx->thread_context; 167 168 dev_dbg(ctx->dev, "In %s:\n", __func__); 169 mutex_lock(&ctx->mutex); 170 if (!is_skl_dsp_running(ctx)) { 171 mutex_unlock(&ctx->mutex); 172 return 0; 173 } 174 mutex_unlock(&ctx->mutex); 175 176 dx.core_mask = SKL_DSP_CORE0_MASK; 177 dx.dx_mask = SKL_IPC_D3_MASK; 178 ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx); 179 if (ret < 0) { 180 dev_err(ctx->dev, "Failed to set DSP to D3 state\n"); 181 return ret; 182 } 183 184 ret = skl_dsp_disable_core(ctx); 185 if (ret < 0) { 186 dev_err(ctx->dev, "disable dsp core failed ret: %d\n", ret); 187 ret = -EIO; 188 } 189 skl_dsp_set_state_locked(ctx, SKL_DSP_RESET); 190 191 /* disable Interrupt */ 192 ctx->cl_dev.ops.cl_cleanup_controller(ctx); 193 skl_cldma_int_disable(ctx); 194 skl_ipc_op_int_disable(ctx); 195 skl_ipc_int_disable(ctx); 196 197 return ret; 198 } 199 200 static unsigned int skl_get_errorcode(struct sst_dsp *ctx) 201 { 202 return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE); 203 } 204 205 static struct skl_dsp_fw_ops skl_fw_ops = { 206 .set_state_D0 = skl_set_dsp_D0, 207 .set_state_D3 = skl_set_dsp_D3, 208 .load_fw = skl_load_base_firmware, 209 .get_fw_errcode = skl_get_errorcode, 210 }; 211 212 static struct sst_ops skl_ops = { 213 .irq_handler = skl_dsp_sst_interrupt, 214 .write = sst_shim32_write, 215 .read = sst_shim32_read, 216 .ram_read = sst_memcpy_fromio_32, 217 .ram_write = sst_memcpy_toio_32, 218 .free = skl_dsp_free, 219 }; 220 221 static struct sst_dsp_device skl_dev = { 222 .thread = skl_dsp_irq_thread_handler, 223 .ops = &skl_ops, 224 }; 225 226 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 227 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp) 228 { 229 struct skl_sst *skl; 230 struct sst_dsp *sst; 231 int ret; 232 233 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 234 if (skl == NULL) 235 return -ENOMEM; 236 237 skl->dev = dev; 238 skl_dev.thread_context = skl; 239 240 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 241 if (!skl->dsp) { 242 dev_err(skl->dev, "%s: no device\n", __func__); 243 return -ENODEV; 244 } 245 246 sst = skl->dsp; 247 248 sst->fw_name = fw_name; 249 sst->addr.lpe = mmio_base; 250 sst->addr.shim = mmio_base; 251 sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 252 SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 253 254 sst->dsp_ops = dsp_ops; 255 sst->fw_ops = skl_fw_ops; 256 257 ret = skl_ipc_init(dev, skl); 258 if (ret) 259 return ret; 260 261 ret = sst->fw_ops.load_fw(sst); 262 if (ret < 0) { 263 dev_err(dev, "Load base fw failed : %d", ret); 264 goto cleanup; 265 } 266 267 if (dsp) 268 *dsp = skl; 269 270 return ret; 271 272 cleanup: 273 skl_sst_dsp_cleanup(dev, skl); 274 return ret; 275 } 276 EXPORT_SYMBOL_GPL(skl_sst_dsp_init); 277 278 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 279 { 280 skl_ipc_free(&ctx->ipc); 281 ctx->dsp->ops->free(ctx->dsp); 282 } 283 EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup); 284 285 MODULE_LICENSE("GPL v2"); 286 MODULE_DESCRIPTION("Intel Skylake IPC driver"); 287