1 /* 2 * skl-sst-ipc.c - Intel skl IPC Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 #include <linux/device.h> 16 17 #include "../common/sst-dsp.h" 18 #include "../common/sst-dsp-priv.h" 19 #include "skl.h" 20 #include "skl-sst-dsp.h" 21 #include "skl-sst-ipc.h" 22 #include "sound/hdaudio_ext.h" 23 24 25 #define IPC_IXC_STATUS_BITS 24 26 27 /* Global Message - Generic */ 28 #define IPC_GLB_TYPE_SHIFT 24 29 #define IPC_GLB_TYPE_MASK (0xf << IPC_GLB_TYPE_SHIFT) 30 #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT) 31 32 /* Global Message - Reply */ 33 #define IPC_GLB_REPLY_STATUS_SHIFT 24 34 #define IPC_GLB_REPLY_STATUS_MASK ((0x1 << IPC_GLB_REPLY_STATUS_SHIFT) - 1) 35 #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT) 36 37 #define IPC_GLB_REPLY_TYPE_SHIFT 29 38 #define IPC_GLB_REPLY_TYPE_MASK 0x1F 39 #define IPC_GLB_REPLY_TYPE(x) (((x) >> IPC_GLB_REPLY_TYPE_SHIFT) \ 40 & IPC_GLB_RPLY_TYPE_MASK) 41 42 #define IPC_TIMEOUT_MSECS 3000 43 44 #define IPC_EMPTY_LIST_SIZE 8 45 46 #define IPC_MSG_TARGET_SHIFT 30 47 #define IPC_MSG_TARGET_MASK 0x1 48 #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \ 49 << IPC_MSG_TARGET_SHIFT) 50 51 #define IPC_MSG_DIR_SHIFT 29 52 #define IPC_MSG_DIR_MASK 0x1 53 #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \ 54 << IPC_MSG_DIR_SHIFT) 55 /* Global Notification Message */ 56 #define IPC_GLB_NOTIFY_TYPE_SHIFT 16 57 #define IPC_GLB_NOTIFY_TYPE_MASK 0xFF 58 #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \ 59 & IPC_GLB_NOTIFY_TYPE_MASK) 60 61 #define IPC_GLB_NOTIFY_MSG_TYPE_SHIFT 24 62 #define IPC_GLB_NOTIFY_MSG_TYPE_MASK 0x1F 63 #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \ 64 & IPC_GLB_NOTIFY_MSG_TYPE_MASK) 65 66 #define IPC_GLB_NOTIFY_RSP_SHIFT 29 67 #define IPC_GLB_NOTIFY_RSP_MASK 0x1 68 #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \ 69 & IPC_GLB_NOTIFY_RSP_MASK) 70 71 /* Pipeline operations */ 72 73 /* Create pipeline message */ 74 #define IPC_PPL_MEM_SIZE_SHIFT 0 75 #define IPC_PPL_MEM_SIZE_MASK 0x7FF 76 #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \ 77 << IPC_PPL_MEM_SIZE_SHIFT) 78 79 #define IPC_PPL_TYPE_SHIFT 11 80 #define IPC_PPL_TYPE_MASK 0x1F 81 #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \ 82 << IPC_PPL_TYPE_SHIFT) 83 84 #define IPC_INSTANCE_ID_SHIFT 16 85 #define IPC_INSTANCE_ID_MASK 0xFF 86 #define IPC_INSTANCE_ID(x) (((x) & IPC_INSTANCE_ID_MASK) \ 87 << IPC_INSTANCE_ID_SHIFT) 88 89 #define IPC_PPL_LP_MODE_SHIFT 0 90 #define IPC_PPL_LP_MODE_MASK 0x1 91 #define IPC_PPL_LP_MODE(x) (((x) & IPC_PPL_LP_MODE_MASK) \ 92 << IPC_PPL_LP_MODE_SHIFT) 93 94 /* Set pipeline state message */ 95 #define IPC_PPL_STATE_SHIFT 0 96 #define IPC_PPL_STATE_MASK 0x1F 97 #define IPC_PPL_STATE(x) (((x) & IPC_PPL_STATE_MASK) \ 98 << IPC_PPL_STATE_SHIFT) 99 100 /* Module operations primary register */ 101 #define IPC_MOD_ID_SHIFT 0 102 #define IPC_MOD_ID_MASK 0xFFFF 103 #define IPC_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \ 104 << IPC_MOD_ID_SHIFT) 105 106 #define IPC_MOD_INSTANCE_ID_SHIFT 16 107 #define IPC_MOD_INSTANCE_ID_MASK 0xFF 108 #define IPC_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \ 109 << IPC_MOD_INSTANCE_ID_SHIFT) 110 111 /* Init instance message extension register */ 112 #define IPC_PARAM_BLOCK_SIZE_SHIFT 0 113 #define IPC_PARAM_BLOCK_SIZE_MASK 0xFFFF 114 #define IPC_PARAM_BLOCK_SIZE(x) (((x) & IPC_PARAM_BLOCK_SIZE_MASK) \ 115 << IPC_PARAM_BLOCK_SIZE_SHIFT) 116 117 #define IPC_PPL_INSTANCE_ID_SHIFT 16 118 #define IPC_PPL_INSTANCE_ID_MASK 0xFF 119 #define IPC_PPL_INSTANCE_ID(x) (((x) & IPC_PPL_INSTANCE_ID_MASK) \ 120 << IPC_PPL_INSTANCE_ID_SHIFT) 121 122 #define IPC_CORE_ID_SHIFT 24 123 #define IPC_CORE_ID_MASK 0x1F 124 #define IPC_CORE_ID(x) (((x) & IPC_CORE_ID_MASK) \ 125 << IPC_CORE_ID_SHIFT) 126 127 #define IPC_DOMAIN_SHIFT 28 128 #define IPC_DOMAIN_MASK 0x1 129 #define IPC_DOMAIN(x) (((x) & IPC_DOMAIN_MASK) \ 130 << IPC_DOMAIN_SHIFT) 131 132 /* Bind/Unbind message extension register */ 133 #define IPC_DST_MOD_ID_SHIFT 0 134 #define IPC_DST_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \ 135 << IPC_DST_MOD_ID_SHIFT) 136 137 #define IPC_DST_MOD_INSTANCE_ID_SHIFT 16 138 #define IPC_DST_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \ 139 << IPC_DST_MOD_INSTANCE_ID_SHIFT) 140 141 #define IPC_DST_QUEUE_SHIFT 24 142 #define IPC_DST_QUEUE_MASK 0x7 143 #define IPC_DST_QUEUE(x) (((x) & IPC_DST_QUEUE_MASK) \ 144 << IPC_DST_QUEUE_SHIFT) 145 146 #define IPC_SRC_QUEUE_SHIFT 27 147 #define IPC_SRC_QUEUE_MASK 0x7 148 #define IPC_SRC_QUEUE(x) (((x) & IPC_SRC_QUEUE_MASK) \ 149 << IPC_SRC_QUEUE_SHIFT) 150 /* Load Module count */ 151 #define IPC_LOAD_MODULE_SHIFT 0 152 #define IPC_LOAD_MODULE_MASK 0xFF 153 #define IPC_LOAD_MODULE_CNT(x) (((x) & IPC_LOAD_MODULE_MASK) \ 154 << IPC_LOAD_MODULE_SHIFT) 155 156 /* Save pipeline messgae extension register */ 157 #define IPC_DMA_ID_SHIFT 0 158 #define IPC_DMA_ID_MASK 0x1F 159 #define IPC_DMA_ID(x) (((x) & IPC_DMA_ID_MASK) \ 160 << IPC_DMA_ID_SHIFT) 161 /* Large Config message extension register */ 162 #define IPC_DATA_OFFSET_SZ_SHIFT 0 163 #define IPC_DATA_OFFSET_SZ_MASK 0xFFFFF 164 #define IPC_DATA_OFFSET_SZ(x) (((x) & IPC_DATA_OFFSET_SZ_MASK) \ 165 << IPC_DATA_OFFSET_SZ_SHIFT) 166 #define IPC_DATA_OFFSET_SZ_CLEAR ~(IPC_DATA_OFFSET_SZ_MASK \ 167 << IPC_DATA_OFFSET_SZ_SHIFT) 168 169 #define IPC_LARGE_PARAM_ID_SHIFT 20 170 #define IPC_LARGE_PARAM_ID_MASK 0xFF 171 #define IPC_LARGE_PARAM_ID(x) (((x) & IPC_LARGE_PARAM_ID_MASK) \ 172 << IPC_LARGE_PARAM_ID_SHIFT) 173 174 #define IPC_FINAL_BLOCK_SHIFT 28 175 #define IPC_FINAL_BLOCK_MASK 0x1 176 #define IPC_FINAL_BLOCK(x) (((x) & IPC_FINAL_BLOCK_MASK) \ 177 << IPC_FINAL_BLOCK_SHIFT) 178 179 #define IPC_INITIAL_BLOCK_SHIFT 29 180 #define IPC_INITIAL_BLOCK_MASK 0x1 181 #define IPC_INITIAL_BLOCK(x) (((x) & IPC_INITIAL_BLOCK_MASK) \ 182 << IPC_INITIAL_BLOCK_SHIFT) 183 #define IPC_INITIAL_BLOCK_CLEAR ~(IPC_INITIAL_BLOCK_MASK \ 184 << IPC_INITIAL_BLOCK_SHIFT) 185 /* Set D0ix IPC extension register */ 186 #define IPC_D0IX_WAKE_SHIFT 0 187 #define IPC_D0IX_WAKE_MASK 0x1 188 #define IPC_D0IX_WAKE(x) (((x) & IPC_D0IX_WAKE_MASK) \ 189 << IPC_D0IX_WAKE_SHIFT) 190 191 #define IPC_D0IX_STREAMING_SHIFT 1 192 #define IPC_D0IX_STREAMING_MASK 0x1 193 #define IPC_D0IX_STREAMING(x) (((x) & IPC_D0IX_STREAMING_MASK) \ 194 << IPC_D0IX_STREAMING_SHIFT) 195 196 197 enum skl_ipc_msg_target { 198 IPC_FW_GEN_MSG = 0, 199 IPC_MOD_MSG = 1 200 }; 201 202 enum skl_ipc_msg_direction { 203 IPC_MSG_REQUEST = 0, 204 IPC_MSG_REPLY = 1 205 }; 206 207 /* Global Message Types */ 208 enum skl_ipc_glb_type { 209 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */ 210 IPC_GLB_LOAD_MULTIPLE_MODS = 15, 211 IPC_GLB_UNLOAD_MULTIPLE_MODS = 16, 212 IPC_GLB_CREATE_PPL = 17, 213 IPC_GLB_DELETE_PPL = 18, 214 IPC_GLB_SET_PPL_STATE = 19, 215 IPC_GLB_GET_PPL_STATE = 20, 216 IPC_GLB_GET_PPL_CONTEXT_SIZE = 21, 217 IPC_GLB_SAVE_PPL = 22, 218 IPC_GLB_RESTORE_PPL = 23, 219 IPC_GLB_LOAD_LIBRARY = 24, 220 IPC_GLB_NOTIFY = 26, 221 IPC_GLB_MAX_IPC_MSG_NUMBER = 31 /* Maximum message number */ 222 }; 223 224 enum skl_ipc_glb_reply { 225 IPC_GLB_REPLY_SUCCESS = 0, 226 227 IPC_GLB_REPLY_UNKNOWN_MSG_TYPE = 1, 228 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 2, 229 230 IPC_GLB_REPLY_BUSY = 3, 231 IPC_GLB_REPLY_PENDING = 4, 232 IPC_GLB_REPLY_FAILURE = 5, 233 IPC_GLB_REPLY_INVALID_REQUEST = 6, 234 235 IPC_GLB_REPLY_OUT_OF_MEMORY = 7, 236 IPC_GLB_REPLY_OUT_OF_MIPS = 8, 237 238 IPC_GLB_REPLY_INVALID_RESOURCE_ID = 9, 239 IPC_GLB_REPLY_INVALID_RESOURCE_STATE = 10, 240 241 IPC_GLB_REPLY_MOD_MGMT_ERROR = 100, 242 IPC_GLB_REPLY_MOD_LOAD_CL_FAILED = 101, 243 IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH = 102, 244 245 IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST = 103, 246 IPC_GLB_REPLY_MOD_NOT_INITIALIZED = 104, 247 248 IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID = 120, 249 IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN = 121, 250 IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED = 140, 251 IPC_GLB_REPLY_GATEWAY_NOT_EXIST = 141, 252 253 IPC_GLB_REPLY_PPL_NOT_INITIALIZED = 160, 254 IPC_GLB_REPLY_PPL_NOT_EXIST = 161, 255 IPC_GLB_REPLY_PPL_SAVE_FAILED = 162, 256 IPC_GLB_REPLY_PPL_RESTORE_FAILED = 163, 257 258 IPC_MAX_STATUS = ((1<<IPC_IXC_STATUS_BITS)-1) 259 }; 260 261 enum skl_ipc_notification_type { 262 IPC_GLB_NOTIFY_GLITCH = 0, 263 IPC_GLB_NOTIFY_OVERRUN = 1, 264 IPC_GLB_NOTIFY_UNDERRUN = 2, 265 IPC_GLB_NOTIFY_END_STREAM = 3, 266 IPC_GLB_NOTIFY_PHRASE_DETECTED = 4, 267 IPC_GLB_NOTIFY_RESOURCE_EVENT = 5, 268 IPC_GLB_NOTIFY_LOG_BUFFER_STATUS = 6, 269 IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED = 7, 270 IPC_GLB_NOTIFY_FW_READY = 8 271 }; 272 273 /* Module Message Types */ 274 enum skl_ipc_module_msg { 275 IPC_MOD_INIT_INSTANCE = 0, 276 IPC_MOD_CONFIG_GET = 1, 277 IPC_MOD_CONFIG_SET = 2, 278 IPC_MOD_LARGE_CONFIG_GET = 3, 279 IPC_MOD_LARGE_CONFIG_SET = 4, 280 IPC_MOD_BIND = 5, 281 IPC_MOD_UNBIND = 6, 282 IPC_MOD_SET_DX = 7, 283 IPC_MOD_SET_D0IX = 8 284 }; 285 286 static void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data, 287 size_t tx_size) 288 { 289 if (tx_size) 290 memcpy(msg->tx_data, tx_data, tx_size); 291 } 292 293 static bool skl_ipc_is_dsp_busy(struct sst_dsp *dsp) 294 { 295 u32 hipci; 296 297 hipci = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCI); 298 return (hipci & SKL_ADSP_REG_HIPCI_BUSY); 299 } 300 301 /* Lock to be held by caller */ 302 static void skl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg) 303 { 304 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header); 305 306 if (msg->tx_size) 307 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size); 308 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCIE, 309 header->extension); 310 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCI, 311 header->primary | SKL_ADSP_REG_HIPCI_BUSY); 312 } 313 314 int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state) 315 { 316 int ret; 317 318 /* check D0i3 support */ 319 if (!dsp->fw_ops.set_state_D0i0) 320 return 0; 321 322 /* Attempt D0i0 or D0i3 based on state */ 323 if (state) 324 ret = dsp->fw_ops.set_state_D0i0(dsp); 325 else 326 ret = dsp->fw_ops.set_state_D0i3(dsp); 327 328 return ret; 329 } 330 331 static struct ipc_message *skl_ipc_reply_get_msg(struct sst_generic_ipc *ipc, 332 u64 ipc_header) 333 { 334 struct ipc_message *msg = NULL; 335 struct skl_ipc_header *header = (struct skl_ipc_header *)(&ipc_header); 336 337 if (list_empty(&ipc->rx_list)) { 338 dev_err(ipc->dev, "ipc: rx list is empty but received 0x%x\n", 339 header->primary); 340 goto out; 341 } 342 343 msg = list_first_entry(&ipc->rx_list, struct ipc_message, list); 344 345 out: 346 return msg; 347 348 } 349 350 static int skl_ipc_process_notification(struct sst_generic_ipc *ipc, 351 struct skl_ipc_header header) 352 { 353 struct skl_sst *skl = container_of(ipc, struct skl_sst, ipc); 354 355 if (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) { 356 switch (IPC_GLB_NOTIFY_TYPE(header.primary)) { 357 358 case IPC_GLB_NOTIFY_UNDERRUN: 359 dev_err(ipc->dev, "FW Underrun %x\n", header.primary); 360 break; 361 362 case IPC_GLB_NOTIFY_RESOURCE_EVENT: 363 dev_err(ipc->dev, "MCPS Budget Violation: %x\n", 364 header.primary); 365 break; 366 367 case IPC_GLB_NOTIFY_FW_READY: 368 skl->boot_complete = true; 369 wake_up(&skl->boot_wait); 370 break; 371 372 case IPC_GLB_NOTIFY_PHRASE_DETECTED: 373 dev_dbg(ipc->dev, "***** Phrase Detected **********\n"); 374 375 /* 376 * Per HW recomendation, After phrase detection, 377 * clear the CGCTL.MISCBDCGE. 378 * 379 * This will be set back on stream closure 380 */ 381 skl->enable_miscbdcge(ipc->dev, false); 382 skl->miscbdcg_disabled = true; 383 break; 384 385 default: 386 dev_err(ipc->dev, "ipc: Unhandled error msg=%x\n", 387 header.primary); 388 break; 389 } 390 } 391 392 return 0; 393 } 394 395 static int skl_ipc_set_reply_error_code(u32 reply) 396 { 397 switch (reply) { 398 case IPC_GLB_REPLY_OUT_OF_MEMORY: 399 return -ENOMEM; 400 401 case IPC_GLB_REPLY_BUSY: 402 return -EBUSY; 403 404 default: 405 return -EINVAL; 406 } 407 } 408 409 static void skl_ipc_process_reply(struct sst_generic_ipc *ipc, 410 struct skl_ipc_header header) 411 { 412 struct ipc_message *msg; 413 u32 reply = header.primary & IPC_GLB_REPLY_STATUS_MASK; 414 u64 *ipc_header = (u64 *)(&header); 415 struct skl_sst *skl = container_of(ipc, struct skl_sst, ipc); 416 417 msg = skl_ipc_reply_get_msg(ipc, *ipc_header); 418 if (msg == NULL) { 419 dev_dbg(ipc->dev, "ipc: rx list is empty\n"); 420 return; 421 } 422 423 /* first process the header */ 424 if (reply == IPC_GLB_REPLY_SUCCESS) { 425 dev_dbg(ipc->dev, "ipc FW reply %x: success\n", header.primary); 426 /* copy the rx data from the mailbox */ 427 sst_dsp_inbox_read(ipc->dsp, msg->rx_data, msg->rx_size); 428 switch (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) { 429 case IPC_GLB_LOAD_MULTIPLE_MODS: 430 case IPC_GLB_LOAD_LIBRARY: 431 skl->mod_load_complete = true; 432 skl->mod_load_status = true; 433 wake_up(&skl->mod_load_wait); 434 break; 435 436 default: 437 break; 438 439 } 440 } else { 441 msg->errno = skl_ipc_set_reply_error_code(reply); 442 dev_err(ipc->dev, "ipc FW reply: reply=%d\n", reply); 443 dev_err(ipc->dev, "FW Error Code: %u\n", 444 ipc->dsp->fw_ops.get_fw_errcode(ipc->dsp)); 445 switch (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) { 446 case IPC_GLB_LOAD_MULTIPLE_MODS: 447 case IPC_GLB_LOAD_LIBRARY: 448 skl->mod_load_complete = true; 449 skl->mod_load_status = false; 450 wake_up(&skl->mod_load_wait); 451 break; 452 453 default: 454 break; 455 456 } 457 } 458 459 list_del(&msg->list); 460 sst_ipc_tx_msg_reply_complete(ipc, msg); 461 } 462 463 irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context) 464 { 465 struct sst_dsp *dsp = context; 466 struct skl_sst *skl = sst_dsp_get_thread_context(dsp); 467 struct sst_generic_ipc *ipc = &skl->ipc; 468 struct skl_ipc_header header = {0}; 469 u32 hipcie, hipct, hipcte; 470 int ipc_irq = 0; 471 472 if (dsp->intr_status & SKL_ADSPIS_CL_DMA) 473 skl_cldma_process_intr(dsp); 474 475 /* Here we handle IPC interrupts only */ 476 if (!(dsp->intr_status & SKL_ADSPIS_IPC)) 477 return IRQ_NONE; 478 479 hipcie = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCIE); 480 hipct = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCT); 481 482 /* reply message from DSP */ 483 if (hipcie & SKL_ADSP_REG_HIPCIE_DONE) { 484 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL, 485 SKL_ADSP_REG_HIPCCTL_DONE, 0); 486 487 /* clear DONE bit - tell DSP we have completed the operation */ 488 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCIE, 489 SKL_ADSP_REG_HIPCIE_DONE, SKL_ADSP_REG_HIPCIE_DONE); 490 491 ipc_irq = 1; 492 493 /* unmask Done interrupt */ 494 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL, 495 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE); 496 } 497 498 /* New message from DSP */ 499 if (hipct & SKL_ADSP_REG_HIPCT_BUSY) { 500 hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE); 501 header.primary = hipct; 502 header.extension = hipcte; 503 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x\n", 504 header.primary); 505 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x\n", 506 header.extension); 507 508 if (IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) { 509 /* Handle Immediate reply from DSP Core */ 510 skl_ipc_process_reply(ipc, header); 511 } else { 512 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n"); 513 skl_ipc_process_notification(ipc, header); 514 } 515 /* clear busy interrupt */ 516 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCT, 517 SKL_ADSP_REG_HIPCT_BUSY, SKL_ADSP_REG_HIPCT_BUSY); 518 ipc_irq = 1; 519 } 520 521 if (ipc_irq == 0) 522 return IRQ_NONE; 523 524 skl_ipc_int_enable(dsp); 525 526 /* continue to send any remaining messages... */ 527 schedule_work(&ipc->kwork); 528 529 return IRQ_HANDLED; 530 } 531 532 void skl_ipc_int_enable(struct sst_dsp *ctx) 533 { 534 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_ADSPIC, 535 SKL_ADSPIC_IPC, SKL_ADSPIC_IPC); 536 } 537 538 void skl_ipc_int_disable(struct sst_dsp *ctx) 539 { 540 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC, 541 SKL_ADSPIC_IPC, 0); 542 } 543 544 void skl_ipc_op_int_enable(struct sst_dsp *ctx) 545 { 546 /* enable IPC DONE interrupt */ 547 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL, 548 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE); 549 550 /* Enable IPC BUSY interrupt */ 551 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL, 552 SKL_ADSP_REG_HIPCCTL_BUSY, SKL_ADSP_REG_HIPCCTL_BUSY); 553 } 554 555 void skl_ipc_op_int_disable(struct sst_dsp *ctx) 556 { 557 /* disable IPC DONE interrupt */ 558 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL, 559 SKL_ADSP_REG_HIPCCTL_DONE, 0); 560 561 /* Disable IPC BUSY interrupt */ 562 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL, 563 SKL_ADSP_REG_HIPCCTL_BUSY, 0); 564 565 } 566 567 bool skl_ipc_int_status(struct sst_dsp *ctx) 568 { 569 return sst_dsp_shim_read_unlocked(ctx, 570 SKL_ADSP_REG_ADSPIS) & SKL_ADSPIS_IPC; 571 } 572 573 int skl_ipc_init(struct device *dev, struct skl_sst *skl) 574 { 575 struct sst_generic_ipc *ipc; 576 int err; 577 578 ipc = &skl->ipc; 579 ipc->dsp = skl->dsp; 580 ipc->dev = dev; 581 582 ipc->tx_data_max_size = SKL_ADSP_W1_SZ; 583 ipc->rx_data_max_size = SKL_ADSP_W0_UP_SZ; 584 585 err = sst_ipc_init(ipc); 586 if (err) 587 return err; 588 589 ipc->ops.tx_msg = skl_ipc_tx_msg; 590 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy; 591 ipc->ops.is_dsp_busy = skl_ipc_is_dsp_busy; 592 593 return 0; 594 } 595 596 void skl_ipc_free(struct sst_generic_ipc *ipc) 597 { 598 /* Disable IPC DONE interrupt */ 599 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL, 600 SKL_ADSP_REG_HIPCCTL_DONE, 0); 601 602 /* Disable IPC BUSY interrupt */ 603 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL, 604 SKL_ADSP_REG_HIPCCTL_BUSY, 0); 605 606 sst_ipc_fini(ipc); 607 } 608 609 int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc, 610 u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode) 611 { 612 struct skl_ipc_header header = {0}; 613 u64 *ipc_header = (u64 *)(&header); 614 int ret; 615 616 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 617 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 618 header.primary |= IPC_GLB_TYPE(IPC_GLB_CREATE_PPL); 619 header.primary |= IPC_INSTANCE_ID(instance_id); 620 header.primary |= IPC_PPL_TYPE(ppl_type); 621 header.primary |= IPC_PPL_MEM_SIZE(ppl_mem_size); 622 623 header.extension = IPC_PPL_LP_MODE(lp_mode); 624 625 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary); 626 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0); 627 if (ret < 0) { 628 dev_err(ipc->dev, "ipc: create pipeline fail, err: %d\n", ret); 629 return ret; 630 } 631 632 return ret; 633 } 634 EXPORT_SYMBOL_GPL(skl_ipc_create_pipeline); 635 636 int skl_ipc_delete_pipeline(struct sst_generic_ipc *ipc, u8 instance_id) 637 { 638 struct skl_ipc_header header = {0}; 639 u64 *ipc_header = (u64 *)(&header); 640 int ret; 641 642 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 643 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 644 header.primary |= IPC_GLB_TYPE(IPC_GLB_DELETE_PPL); 645 header.primary |= IPC_INSTANCE_ID(instance_id); 646 647 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary); 648 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0); 649 if (ret < 0) { 650 dev_err(ipc->dev, "ipc: delete pipeline failed, err %d\n", ret); 651 return ret; 652 } 653 654 return 0; 655 } 656 EXPORT_SYMBOL_GPL(skl_ipc_delete_pipeline); 657 658 int skl_ipc_set_pipeline_state(struct sst_generic_ipc *ipc, 659 u8 instance_id, enum skl_ipc_pipeline_state state) 660 { 661 struct skl_ipc_header header = {0}; 662 u64 *ipc_header = (u64 *)(&header); 663 int ret; 664 665 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 666 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 667 header.primary |= IPC_GLB_TYPE(IPC_GLB_SET_PPL_STATE); 668 header.primary |= IPC_INSTANCE_ID(instance_id); 669 header.primary |= IPC_PPL_STATE(state); 670 671 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary); 672 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0); 673 if (ret < 0) { 674 dev_err(ipc->dev, "ipc: set pipeline state failed, err: %d\n", ret); 675 return ret; 676 } 677 return ret; 678 } 679 EXPORT_SYMBOL_GPL(skl_ipc_set_pipeline_state); 680 681 int 682 skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, u8 instance_id, int dma_id) 683 { 684 struct skl_ipc_header header = {0}; 685 u64 *ipc_header = (u64 *)(&header); 686 int ret; 687 688 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 689 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 690 header.primary |= IPC_GLB_TYPE(IPC_GLB_SAVE_PPL); 691 header.primary |= IPC_INSTANCE_ID(instance_id); 692 693 header.extension = IPC_DMA_ID(dma_id); 694 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary); 695 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0); 696 if (ret < 0) { 697 dev_err(ipc->dev, "ipc: save pipeline failed, err: %d\n", ret); 698 return ret; 699 } 700 701 return ret; 702 } 703 EXPORT_SYMBOL_GPL(skl_ipc_save_pipeline); 704 705 int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id) 706 { 707 struct skl_ipc_header header = {0}; 708 u64 *ipc_header = (u64 *)(&header); 709 int ret; 710 711 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 712 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 713 header.primary |= IPC_GLB_TYPE(IPC_GLB_RESTORE_PPL); 714 header.primary |= IPC_INSTANCE_ID(instance_id); 715 716 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary); 717 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0); 718 if (ret < 0) { 719 dev_err(ipc->dev, "ipc: restore pipeline failed, err: %d\n", ret); 720 return ret; 721 } 722 723 return ret; 724 } 725 EXPORT_SYMBOL_GPL(skl_ipc_restore_pipeline); 726 727 int skl_ipc_set_dx(struct sst_generic_ipc *ipc, u8 instance_id, 728 u16 module_id, struct skl_ipc_dxstate_info *dx) 729 { 730 struct skl_ipc_header header = {0}; 731 u64 *ipc_header = (u64 *)(&header); 732 int ret; 733 734 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG); 735 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 736 header.primary |= IPC_GLB_TYPE(IPC_MOD_SET_DX); 737 header.primary |= IPC_MOD_INSTANCE_ID(instance_id); 738 header.primary |= IPC_MOD_ID(module_id); 739 740 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__, 741 header.primary, header.extension); 742 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, 743 dx, sizeof(*dx), NULL, 0); 744 if (ret < 0) { 745 dev_err(ipc->dev, "ipc: set dx failed, err %d\n", ret); 746 return ret; 747 } 748 749 return ret; 750 } 751 EXPORT_SYMBOL_GPL(skl_ipc_set_dx); 752 753 int skl_ipc_init_instance(struct sst_generic_ipc *ipc, 754 struct skl_ipc_init_instance_msg *msg, void *param_data) 755 { 756 struct skl_ipc_header header = {0}; 757 u64 *ipc_header = (u64 *)(&header); 758 int ret; 759 u32 *buffer = (u32 *)param_data; 760 /* param_block_size must be in dwords */ 761 u16 param_block_size = msg->param_data_size / sizeof(u32); 762 763 print_hex_dump_debug("Param data:", DUMP_PREFIX_NONE, 764 16, 4, buffer, param_block_size, false); 765 766 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG); 767 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 768 header.primary |= IPC_GLB_TYPE(IPC_MOD_INIT_INSTANCE); 769 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id); 770 header.primary |= IPC_MOD_ID(msg->module_id); 771 772 header.extension = IPC_CORE_ID(msg->core_id); 773 header.extension |= IPC_PPL_INSTANCE_ID(msg->ppl_instance_id); 774 header.extension |= IPC_PARAM_BLOCK_SIZE(param_block_size); 775 header.extension |= IPC_DOMAIN(msg->domain); 776 777 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__, 778 header.primary, header.extension); 779 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, param_data, 780 msg->param_data_size, NULL, 0); 781 782 if (ret < 0) { 783 dev_err(ipc->dev, "ipc: init instance failed\n"); 784 return ret; 785 } 786 787 return ret; 788 } 789 EXPORT_SYMBOL_GPL(skl_ipc_init_instance); 790 791 int skl_ipc_bind_unbind(struct sst_generic_ipc *ipc, 792 struct skl_ipc_bind_unbind_msg *msg) 793 { 794 struct skl_ipc_header header = {0}; 795 u64 *ipc_header = (u64 *)(&header); 796 u8 bind_unbind = msg->bind ? IPC_MOD_BIND : IPC_MOD_UNBIND; 797 int ret; 798 799 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG); 800 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 801 header.primary |= IPC_GLB_TYPE(bind_unbind); 802 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id); 803 header.primary |= IPC_MOD_ID(msg->module_id); 804 805 header.extension = IPC_DST_MOD_ID(msg->dst_module_id); 806 header.extension |= IPC_DST_MOD_INSTANCE_ID(msg->dst_instance_id); 807 header.extension |= IPC_DST_QUEUE(msg->dst_queue); 808 header.extension |= IPC_SRC_QUEUE(msg->src_queue); 809 810 dev_dbg(ipc->dev, "In %s hdr=%x ext=%x\n", __func__, header.primary, 811 header.extension); 812 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0); 813 if (ret < 0) { 814 dev_err(ipc->dev, "ipc: bind/unbind failed\n"); 815 return ret; 816 } 817 818 return ret; 819 } 820 EXPORT_SYMBOL_GPL(skl_ipc_bind_unbind); 821 822 /* 823 * In order to load a module we need to send IPC to initiate that. DMA will 824 * performed to load the module memory. The FW supports multiple module load 825 * at single shot, so we can send IPC with N modules represented by 826 * module_cnt 827 */ 828 int skl_ipc_load_modules(struct sst_generic_ipc *ipc, 829 u8 module_cnt, void *data) 830 { 831 struct skl_ipc_header header = {0}; 832 u64 *ipc_header = (u64 *)(&header); 833 int ret; 834 835 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 836 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 837 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_MULTIPLE_MODS); 838 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt); 839 840 ret = sst_ipc_tx_message_nowait(ipc, *ipc_header, data, 841 (sizeof(u16) * module_cnt)); 842 if (ret < 0) 843 dev_err(ipc->dev, "ipc: load modules failed :%d\n", ret); 844 845 return ret; 846 } 847 EXPORT_SYMBOL_GPL(skl_ipc_load_modules); 848 849 int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, u8 module_cnt, 850 void *data) 851 { 852 struct skl_ipc_header header = {0}; 853 u64 *ipc_header = (u64 *)(&header); 854 int ret; 855 856 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 857 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 858 header.primary |= IPC_GLB_TYPE(IPC_GLB_UNLOAD_MULTIPLE_MODS); 859 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt); 860 861 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data, 862 (sizeof(u16) * module_cnt), NULL, 0); 863 if (ret < 0) 864 dev_err(ipc->dev, "ipc: unload modules failed :%d\n", ret); 865 866 return ret; 867 } 868 EXPORT_SYMBOL_GPL(skl_ipc_unload_modules); 869 870 int skl_ipc_set_large_config(struct sst_generic_ipc *ipc, 871 struct skl_ipc_large_config_msg *msg, u32 *param) 872 { 873 struct skl_ipc_header header = {0}; 874 u64 *ipc_header = (u64 *)(&header); 875 int ret = 0; 876 size_t sz_remaining, tx_size, data_offset; 877 878 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG); 879 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 880 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_SET); 881 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id); 882 header.primary |= IPC_MOD_ID(msg->module_id); 883 884 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size); 885 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id); 886 header.extension |= IPC_FINAL_BLOCK(0); 887 header.extension |= IPC_INITIAL_BLOCK(1); 888 889 sz_remaining = msg->param_data_size; 890 data_offset = 0; 891 while (sz_remaining != 0) { 892 tx_size = sz_remaining > SKL_ADSP_W1_SZ 893 ? SKL_ADSP_W1_SZ : sz_remaining; 894 if (tx_size == sz_remaining) 895 header.extension |= IPC_FINAL_BLOCK(1); 896 897 dev_dbg(ipc->dev, "In %s primary=%#x ext=%#x\n", __func__, 898 header.primary, header.extension); 899 dev_dbg(ipc->dev, "transmitting offset: %#x, size: %#x\n", 900 (unsigned)data_offset, (unsigned)tx_size); 901 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, 902 ((char *)param) + data_offset, 903 tx_size, NULL, 0); 904 if (ret < 0) { 905 dev_err(ipc->dev, 906 "ipc: set large config fail, err: %d\n", ret); 907 return ret; 908 } 909 sz_remaining -= tx_size; 910 data_offset = msg->param_data_size - sz_remaining; 911 912 /* clear the fields */ 913 header.extension &= IPC_INITIAL_BLOCK_CLEAR; 914 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR; 915 /* fill the fields */ 916 header.extension |= IPC_INITIAL_BLOCK(0); 917 header.extension |= IPC_DATA_OFFSET_SZ(data_offset); 918 } 919 920 return ret; 921 } 922 EXPORT_SYMBOL_GPL(skl_ipc_set_large_config); 923 924 int skl_ipc_get_large_config(struct sst_generic_ipc *ipc, 925 struct skl_ipc_large_config_msg *msg, u32 *param) 926 { 927 struct skl_ipc_header header = {0}; 928 u64 *ipc_header = (u64 *)(&header); 929 int ret = 0; 930 size_t sz_remaining, rx_size, data_offset; 931 932 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG); 933 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 934 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_GET); 935 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id); 936 header.primary |= IPC_MOD_ID(msg->module_id); 937 938 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size); 939 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id); 940 header.extension |= IPC_FINAL_BLOCK(1); 941 header.extension |= IPC_INITIAL_BLOCK(1); 942 943 sz_remaining = msg->param_data_size; 944 data_offset = 0; 945 946 while (sz_remaining != 0) { 947 rx_size = sz_remaining > SKL_ADSP_W1_SZ 948 ? SKL_ADSP_W1_SZ : sz_remaining; 949 if (rx_size == sz_remaining) 950 header.extension |= IPC_FINAL_BLOCK(1); 951 952 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, 953 ((char *)param) + data_offset, 954 msg->param_data_size); 955 if (ret < 0) { 956 dev_err(ipc->dev, 957 "ipc: get large config fail, err: %d\n", ret); 958 return ret; 959 } 960 sz_remaining -= rx_size; 961 data_offset = msg->param_data_size - sz_remaining; 962 963 /* clear the fields */ 964 header.extension &= IPC_INITIAL_BLOCK_CLEAR; 965 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR; 966 /* fill the fields */ 967 header.extension |= IPC_INITIAL_BLOCK(1); 968 header.extension |= IPC_DATA_OFFSET_SZ(data_offset); 969 } 970 971 return ret; 972 } 973 EXPORT_SYMBOL_GPL(skl_ipc_get_large_config); 974 975 int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc, 976 u8 dma_id, u8 table_id, bool wait) 977 { 978 struct skl_ipc_header header = {0}; 979 u64 *ipc_header = (u64 *)(&header); 980 int ret = 0; 981 982 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG); 983 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 984 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_LIBRARY); 985 header.primary |= IPC_MOD_INSTANCE_ID(table_id); 986 header.primary |= IPC_MOD_ID(dma_id); 987 988 if (wait) 989 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, 990 NULL, 0, NULL, 0); 991 else 992 ret = sst_ipc_tx_message_nowait(ipc, *ipc_header, NULL, 0); 993 994 if (ret < 0) 995 dev_err(ipc->dev, "ipc: load lib failed\n"); 996 997 return ret; 998 } 999 EXPORT_SYMBOL_GPL(skl_sst_ipc_load_library); 1000 1001 int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc, struct skl_ipc_d0ix_msg *msg) 1002 { 1003 struct skl_ipc_header header = {0}; 1004 u64 *ipc_header = (u64 *)(&header); 1005 int ret; 1006 1007 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG); 1008 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST); 1009 header.primary |= IPC_GLB_TYPE(IPC_MOD_SET_D0IX); 1010 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id); 1011 header.primary |= IPC_MOD_ID(msg->module_id); 1012 1013 header.extension = IPC_D0IX_WAKE(msg->wake); 1014 header.extension |= IPC_D0IX_STREAMING(msg->streaming); 1015 1016 dev_dbg(ipc->dev, "In %s primary=%x ext=%x\n", __func__, 1017 header.primary, header.extension); 1018 1019 /* 1020 * Use the nopm IPC here as we dont want it checking for D0iX 1021 */ 1022 ret = sst_ipc_tx_message_nopm(ipc, *ipc_header, NULL, 0, NULL, 0); 1023 if (ret < 0) 1024 dev_err(ipc->dev, "ipc: set d0ix failed, err %d\n", ret); 1025 1026 return ret; 1027 } 1028 EXPORT_SYMBOL_GPL(skl_ipc_set_d0ix); 1029