1 /*
2  * Skylake SST DSP Support
3  *
4  * Copyright (C) 2014-15, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as version 2, as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  */
15 
16 #ifndef __SKL_SST_DSP_H__
17 #define __SKL_SST_DSP_H__
18 
19 #include <sound/memalloc.h>
20 
21 struct sst_dsp_device;
22 
23 /* Intel HD Audio General DSP Registers */
24 #define SKL_ADSP_GEN_BASE		0x0
25 #define SKL_ADSP_REG_ADSPCS		(SKL_ADSP_GEN_BASE + 0x04)
26 #define SKL_ADSP_REG_ADSPIC		(SKL_ADSP_GEN_BASE + 0x08)
27 #define SKL_ADSP_REG_ADSPIS		(SKL_ADSP_GEN_BASE + 0x0C)
28 #define SKL_ADSP_REG_ADSPIC2		(SKL_ADSP_GEN_BASE + 0x10)
29 #define SKL_ADSP_REG_ADSPIS2		(SKL_ADSP_GEN_BASE + 0x14)
30 
31 /* Intel HD Audio Inter-Processor Communication Registers */
32 #define SKL_ADSP_IPC_BASE		0x40
33 #define SKL_ADSP_REG_HIPCT		(SKL_ADSP_IPC_BASE + 0x00)
34 #define SKL_ADSP_REG_HIPCTE		(SKL_ADSP_IPC_BASE + 0x04)
35 #define SKL_ADSP_REG_HIPCI		(SKL_ADSP_IPC_BASE + 0x08)
36 #define SKL_ADSP_REG_HIPCIE		(SKL_ADSP_IPC_BASE + 0x0C)
37 #define SKL_ADSP_REG_HIPCCTL		(SKL_ADSP_IPC_BASE + 0x10)
38 
39 /*  HIPCI */
40 #define SKL_ADSP_REG_HIPCI_BUSY		BIT(31)
41 
42 /* HIPCIE */
43 #define SKL_ADSP_REG_HIPCIE_DONE	BIT(30)
44 
45 /* HIPCCTL */
46 #define SKL_ADSP_REG_HIPCCTL_DONE	BIT(1)
47 #define SKL_ADSP_REG_HIPCCTL_BUSY	BIT(0)
48 
49 /* HIPCT */
50 #define SKL_ADSP_REG_HIPCT_BUSY		BIT(31)
51 
52 /* Intel HD Audio SRAM Window 1 */
53 #define SKL_ADSP_SRAM1_BASE		0xA000
54 
55 #define SKL_ADSP_MMIO_LEN		0x10000
56 
57 #define SKL_ADSP_W0_STAT_SZ		0x800
58 
59 #define SKL_ADSP_W0_UP_SZ		0x800
60 
61 #define SKL_ADSP_W1_SZ			0x1000
62 
63 #define SKL_ADSPIC_IPC			1
64 #define SKL_ADSPIS_IPC			1
65 
66 /* ADSPCS - Audio DSP Control & Status */
67 #define SKL_DSP_CORES		1
68 #define SKL_DSP_CORE0_MASK	1
69 #define SKL_DSP_CORES_MASK	((1 << SKL_DSP_CORES) - 1)
70 
71 /* Core Reset - asserted high */
72 #define SKL_ADSPCS_CRST_SHIFT	0
73 #define SKL_ADSPCS_CRST_MASK	(SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT)
74 #define SKL_ADSPCS_CRST(x)	((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK)
75 
76 /* Core run/stall - when set to '1' core is stalled */
77 #define SKL_ADSPCS_CSTALL_SHIFT	8
78 #define SKL_ADSPCS_CSTALL_MASK	(SKL_DSP_CORES_MASK <<	\
79 					SKL_ADSPCS_CSTALL_SHIFT)
80 #define SKL_ADSPCS_CSTALL(x)	((x << SKL_ADSPCS_CSTALL_SHIFT) &	\
81 				SKL_ADSPCS_CSTALL_MASK)
82 
83 /* Set Power Active - when set to '1' turn cores on */
84 #define SKL_ADSPCS_SPA_SHIFT	16
85 #define SKL_ADSPCS_SPA_MASK	(SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT)
86 #define SKL_ADSPCS_SPA(x)	((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK)
87 
88 /* Current Power Active - power status of cores, set by hardware */
89 #define SKL_ADSPCS_CPA_SHIFT	24
90 #define SKL_ADSPCS_CPA_MASK	(SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT)
91 #define SKL_ADSPCS_CPA(x)	((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK)
92 
93 #define SST_DSP_POWER_D0	0x0  /* full On */
94 #define SST_DSP_POWER_D3	0x3  /* Off */
95 
96 enum skl_dsp_states {
97 	SKL_DSP_RUNNING = 1,
98 	SKL_DSP_RESET,
99 };
100 
101 struct skl_dsp_fw_ops {
102 	int (*load_fw)(struct sst_dsp  *ctx);
103 	/* FW module parser/loader */
104 	int (*parse_fw)(struct sst_dsp *ctx);
105 	int (*set_state_D0)(struct sst_dsp *ctx);
106 	int (*set_state_D3)(struct sst_dsp *ctx);
107 };
108 
109 struct skl_dsp_loader_ops {
110 	int (*alloc_dma_buf)(struct device *dev,
111 		struct snd_dma_buffer *dmab, size_t size);
112 	int (*free_dma_buf)(struct device *dev,
113 		struct snd_dma_buffer *dmab);
114 };
115 
116 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
117 struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
118 		struct sst_dsp_device *sst_dev, int irq);
119 int skl_dsp_disable_core(struct sst_dsp  *ctx);
120 bool is_skl_dsp_running(struct sst_dsp *ctx);
121 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
122 int skl_dsp_wake(struct sst_dsp *ctx);
123 int skl_dsp_sleep(struct sst_dsp *ctx);
124 void skl_dsp_free(struct sst_dsp *dsp);
125 
126 int skl_dsp_boot(struct sst_dsp *ctx);
127 
128 #endif /*__SKL_SST_DSP_H__*/
129