1 /* 2 * Skylake SST DSP Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_SST_DSP_H__ 17 #define __SKL_SST_DSP_H__ 18 19 #include <linux/interrupt.h> 20 #include <sound/memalloc.h> 21 #include "skl-sst-cldma.h" 22 #include "skl-tplg-interface.h" 23 24 struct sst_dsp; 25 struct skl_sst; 26 struct sst_dsp_device; 27 28 /* Intel HD Audio General DSP Registers */ 29 #define SKL_ADSP_GEN_BASE 0x0 30 #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 31 #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 32 #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 33 #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 34 #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 35 36 /* Intel HD Audio Inter-Processor Communication Registers */ 37 #define SKL_ADSP_IPC_BASE 0x40 38 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 39 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 40 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 41 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 42 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 43 44 /* HIPCI */ 45 #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 46 47 /* HIPCIE */ 48 #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 49 50 /* HIPCCTL */ 51 #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 52 #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 53 54 /* HIPCT */ 55 #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 56 57 /* FW base IDs */ 58 #define SKL_INSTANCE_ID 0 59 #define SKL_BASE_FW_MODULE_ID 0 60 61 /* Intel HD Audio SRAM Window 1 */ 62 #define SKL_ADSP_SRAM1_BASE 0xA000 63 64 #define SKL_ADSP_MMIO_LEN 0x10000 65 66 #define SKL_ADSP_W0_STAT_SZ 0x1000 67 68 #define SKL_ADSP_W0_UP_SZ 0x1000 69 70 #define SKL_ADSP_W1_SZ 0x1000 71 72 #define SKL_FW_STS_MASK 0xf 73 74 #define SKL_FW_INIT 0x1 75 #define SKL_FW_RFW_START 0xf 76 77 #define SKL_ADSPIC_IPC 1 78 #define SKL_ADSPIS_IPC 1 79 80 /* Core ID of core0 */ 81 #define SKL_DSP_CORE0_ID 0 82 83 /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 84 #define SKL_DSP_CORE_MASK(c) BIT(c) 85 86 /* 87 * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately 88 * since Core0 is primary core and it is used often 89 */ 90 #define SKL_DSP_CORE0_MASK BIT(0) 91 92 /* 93 * Mask for a given number of cores 94 * nc = number of supported cores 95 */ 96 #define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0) 97 98 /* ADSPCS - Audio DSP Control & Status */ 99 100 /* 101 * Core Reset - asserted high 102 * CRST Mask for a given core mask pattern, cm 103 */ 104 #define SKL_ADSPCS_CRST_SHIFT 0 105 #define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT) 106 107 /* 108 * Core run/stall - when set to '1' core is stalled 109 * CSTALL Mask for a given core mask pattern, cm 110 */ 111 #define SKL_ADSPCS_CSTALL_SHIFT 8 112 #define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT) 113 114 /* 115 * Set Power Active - when set to '1' turn cores on 116 * SPA Mask for a given core mask pattern, cm 117 */ 118 #define SKL_ADSPCS_SPA_SHIFT 16 119 #define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT) 120 121 /* 122 * Current Power Active - power status of cores, set by hardware 123 * CPA Mask for a given core mask pattern, cm 124 */ 125 #define SKL_ADSPCS_CPA_SHIFT 24 126 #define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT) 127 128 enum skl_dsp_states { 129 SKL_DSP_RUNNING = 1, 130 SKL_DSP_RESET, 131 }; 132 133 struct skl_dsp_fw_ops { 134 int (*load_fw)(struct sst_dsp *ctx); 135 /* FW module parser/loader */ 136 int (*parse_fw)(struct sst_dsp *ctx); 137 int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id); 138 int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id); 139 unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); 140 int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name); 141 int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); 142 143 }; 144 145 struct skl_dsp_loader_ops { 146 int stream_tag; 147 148 int (*alloc_dma_buf)(struct device *dev, 149 struct snd_dma_buffer *dmab, size_t size); 150 int (*free_dma_buf)(struct device *dev, 151 struct snd_dma_buffer *dmab); 152 int (*prepare)(struct device *dev, unsigned int format, 153 unsigned int byte_size, 154 struct snd_dma_buffer *bufp); 155 int (*trigger)(struct device *dev, bool start, int stream_tag); 156 157 int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab, 158 int stream_tag); 159 }; 160 161 struct skl_load_module_info { 162 u16 mod_id; 163 const struct firmware *fw; 164 }; 165 166 struct skl_module_table { 167 struct skl_load_module_info *mod_info; 168 unsigned int usage_cnt; 169 struct list_head list; 170 }; 171 172 void skl_cldma_process_intr(struct sst_dsp *ctx); 173 void skl_cldma_int_disable(struct sst_dsp *ctx); 174 int skl_cldma_prepare(struct sst_dsp *ctx); 175 176 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 177 struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 178 struct sst_dsp_device *sst_dev, int irq); 179 bool is_skl_dsp_running(struct sst_dsp *ctx); 180 181 unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx); 182 void skl_dsp_init_core_state(struct sst_dsp *ctx); 183 int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); 184 int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); 185 int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask); 186 int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask); 187 int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx, 188 unsigned int core_mask); 189 int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask); 190 191 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 192 int skl_dsp_wake(struct sst_dsp *ctx); 193 int skl_dsp_sleep(struct sst_dsp *ctx); 194 void skl_dsp_free(struct sst_dsp *dsp); 195 196 int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id); 197 int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id); 198 199 int skl_dsp_boot(struct sst_dsp *ctx); 200 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 201 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 202 struct skl_sst **dsp); 203 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 204 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 205 struct skl_sst **dsp); 206 int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx); 207 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx); 208 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 209 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 210 211 int snd_skl_get_module_info(struct skl_sst *ctx, u8 *uuid, 212 struct skl_dfw_module *dfw_config); 213 int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, 214 unsigned int offset, int index); 215 void skl_freeup_uuid_list(struct skl_sst *ctx); 216 217 int skl_dsp_strip_extended_manifest(struct firmware *fw); 218 219 #endif /*__SKL_SST_DSP_H__*/ 220