1 /* 2 * Skylake SST DSP Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_SST_DSP_H__ 17 #define __SKL_SST_DSP_H__ 18 19 #include <linux/interrupt.h> 20 #include <sound/memalloc.h> 21 #include "skl-sst-cldma.h" 22 23 struct sst_dsp; 24 struct skl_sst; 25 struct sst_dsp_device; 26 27 /* Intel HD Audio General DSP Registers */ 28 #define SKL_ADSP_GEN_BASE 0x0 29 #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 30 #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 31 #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 32 #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 33 #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 34 35 /* Intel HD Audio Inter-Processor Communication Registers */ 36 #define SKL_ADSP_IPC_BASE 0x40 37 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 38 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 39 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 40 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 41 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 42 43 /* HIPCI */ 44 #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 45 46 /* HIPCIE */ 47 #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 48 49 /* HIPCCTL */ 50 #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 51 #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 52 53 /* HIPCT */ 54 #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 55 56 /* Intel HD Audio SRAM Window 1 */ 57 #define SKL_ADSP_SRAM1_BASE 0xA000 58 59 #define SKL_ADSP_MMIO_LEN 0x10000 60 61 #define SKL_ADSP_W0_STAT_SZ 0x800 62 63 #define SKL_ADSP_W0_UP_SZ 0x800 64 65 #define SKL_ADSP_W1_SZ 0x1000 66 67 #define SKL_FW_STS_MASK 0xf 68 69 #define SKL_FW_INIT 0x1 70 #define SKL_FW_RFW_START 0xf 71 72 #define SKL_ADSPIC_IPC 1 73 #define SKL_ADSPIS_IPC 1 74 75 /* ADSPCS - Audio DSP Control & Status */ 76 #define SKL_DSP_CORES 1 77 #define SKL_DSP_CORE0_MASK 1 78 #define SKL_DSP_CORES_MASK ((1 << SKL_DSP_CORES) - 1) 79 80 /* Core Reset - asserted high */ 81 #define SKL_ADSPCS_CRST_SHIFT 0 82 #define SKL_ADSPCS_CRST_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT) 83 #define SKL_ADSPCS_CRST(x) ((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK) 84 85 /* Core run/stall - when set to '1' core is stalled */ 86 #define SKL_ADSPCS_CSTALL_SHIFT 8 87 #define SKL_ADSPCS_CSTALL_MASK (SKL_DSP_CORES_MASK << \ 88 SKL_ADSPCS_CSTALL_SHIFT) 89 #define SKL_ADSPCS_CSTALL(x) ((x << SKL_ADSPCS_CSTALL_SHIFT) & \ 90 SKL_ADSPCS_CSTALL_MASK) 91 92 /* Set Power Active - when set to '1' turn cores on */ 93 #define SKL_ADSPCS_SPA_SHIFT 16 94 #define SKL_ADSPCS_SPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT) 95 #define SKL_ADSPCS_SPA(x) ((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK) 96 97 /* Current Power Active - power status of cores, set by hardware */ 98 #define SKL_ADSPCS_CPA_SHIFT 24 99 #define SKL_ADSPCS_CPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT) 100 #define SKL_ADSPCS_CPA(x) ((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK) 101 102 #define SST_DSP_POWER_D0 0x0 /* full On */ 103 #define SST_DSP_POWER_D3 0x3 /* Off */ 104 105 enum skl_dsp_states { 106 SKL_DSP_RUNNING = 1, 107 SKL_DSP_RESET, 108 }; 109 110 struct skl_dsp_fw_ops { 111 int (*load_fw)(struct sst_dsp *ctx); 112 /* FW module parser/loader */ 113 int (*parse_fw)(struct sst_dsp *ctx); 114 int (*set_state_D0)(struct sst_dsp *ctx); 115 int (*set_state_D3)(struct sst_dsp *ctx); 116 unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); 117 }; 118 119 struct skl_dsp_loader_ops { 120 int (*alloc_dma_buf)(struct device *dev, 121 struct snd_dma_buffer *dmab, size_t size); 122 int (*free_dma_buf)(struct device *dev, 123 struct snd_dma_buffer *dmab); 124 }; 125 126 void skl_cldma_process_intr(struct sst_dsp *ctx); 127 void skl_cldma_int_disable(struct sst_dsp *ctx); 128 int skl_cldma_prepare(struct sst_dsp *ctx); 129 130 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 131 struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 132 struct sst_dsp_device *sst_dev, int irq); 133 int skl_dsp_disable_core(struct sst_dsp *ctx); 134 bool is_skl_dsp_running(struct sst_dsp *ctx); 135 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 136 int skl_dsp_wake(struct sst_dsp *ctx); 137 int skl_dsp_sleep(struct sst_dsp *ctx); 138 void skl_dsp_free(struct sst_dsp *dsp); 139 140 int skl_dsp_boot(struct sst_dsp *ctx); 141 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 142 struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp); 143 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 144 145 #endif /*__SKL_SST_DSP_H__*/ 146