1 /* 2 * Skylake SST DSP Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_SST_DSP_H__ 17 #define __SKL_SST_DSP_H__ 18 19 #include <linux/interrupt.h> 20 #include <sound/memalloc.h> 21 #include "skl-sst-cldma.h" 22 #include "skl-tplg-interface.h" 23 #include "skl-topology.h" 24 25 struct sst_dsp; 26 struct skl_sst; 27 struct sst_dsp_device; 28 29 /* Intel HD Audio General DSP Registers */ 30 #define SKL_ADSP_GEN_BASE 0x0 31 #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 32 #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 33 #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 34 #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 35 #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 36 37 /* Intel HD Audio Inter-Processor Communication Registers */ 38 #define SKL_ADSP_IPC_BASE 0x40 39 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 40 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 41 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 42 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 43 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 44 45 /* HIPCI */ 46 #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 47 48 /* HIPCIE */ 49 #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 50 51 /* HIPCCTL */ 52 #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 53 #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 54 55 /* HIPCT */ 56 #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 57 58 /* FW base IDs */ 59 #define SKL_INSTANCE_ID 0 60 #define SKL_BASE_FW_MODULE_ID 0 61 62 /* Intel HD Audio SRAM Window 1 */ 63 #define SKL_ADSP_SRAM1_BASE 0xA000 64 65 #define SKL_ADSP_MMIO_LEN 0x10000 66 67 #define SKL_ADSP_W0_STAT_SZ 0x1000 68 69 #define SKL_ADSP_W0_UP_SZ 0x1000 70 71 #define SKL_ADSP_W1_SZ 0x1000 72 73 #define SKL_FW_STS_MASK 0xf 74 75 #define SKL_FW_INIT 0x1 76 #define SKL_FW_RFW_START 0xf 77 78 #define SKL_ADSPIC_IPC 1 79 #define SKL_ADSPIS_IPC 1 80 81 /* Core ID of core0 */ 82 #define SKL_DSP_CORE0_ID 0 83 84 /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 85 #define SKL_DSP_CORE_MASK(c) BIT(c) 86 87 /* 88 * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately 89 * since Core0 is primary core and it is used often 90 */ 91 #define SKL_DSP_CORE0_MASK BIT(0) 92 93 /* 94 * Mask for a given number of cores 95 * nc = number of supported cores 96 */ 97 #define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0) 98 99 /* ADSPCS - Audio DSP Control & Status */ 100 101 /* 102 * Core Reset - asserted high 103 * CRST Mask for a given core mask pattern, cm 104 */ 105 #define SKL_ADSPCS_CRST_SHIFT 0 106 #define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT) 107 108 /* 109 * Core run/stall - when set to '1' core is stalled 110 * CSTALL Mask for a given core mask pattern, cm 111 */ 112 #define SKL_ADSPCS_CSTALL_SHIFT 8 113 #define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT) 114 115 /* 116 * Set Power Active - when set to '1' turn cores on 117 * SPA Mask for a given core mask pattern, cm 118 */ 119 #define SKL_ADSPCS_SPA_SHIFT 16 120 #define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT) 121 122 /* 123 * Current Power Active - power status of cores, set by hardware 124 * CPA Mask for a given core mask pattern, cm 125 */ 126 #define SKL_ADSPCS_CPA_SHIFT 24 127 #define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT) 128 129 /* DSP Core state */ 130 enum skl_dsp_states { 131 SKL_DSP_RUNNING = 1, 132 /* Running in D0i3 state; can be in streaming or non-streaming D0i3 */ 133 SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/ 134 SKL_DSP_RESET, 135 }; 136 137 /* D0i3 substates */ 138 enum skl_dsp_d0i3_states { 139 SKL_DSP_D0I3_NONE = -1, /* No D0i3 */ 140 SKL_DSP_D0I3_NON_STREAMING = 0, 141 SKL_DSP_D0I3_STREAMING = 1, 142 }; 143 144 struct skl_dsp_fw_ops { 145 int (*load_fw)(struct sst_dsp *ctx); 146 /* FW module parser/loader */ 147 int (*load_library)(struct sst_dsp *ctx, 148 struct skl_dfw_manifest *minfo); 149 int (*parse_fw)(struct sst_dsp *ctx); 150 int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id); 151 int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id); 152 int (*set_state_D0i3)(struct sst_dsp *ctx); 153 int (*set_state_D0i0)(struct sst_dsp *ctx); 154 unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); 155 int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name); 156 int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); 157 158 }; 159 160 struct skl_dsp_loader_ops { 161 int stream_tag; 162 163 int (*alloc_dma_buf)(struct device *dev, 164 struct snd_dma_buffer *dmab, size_t size); 165 int (*free_dma_buf)(struct device *dev, 166 struct snd_dma_buffer *dmab); 167 int (*prepare)(struct device *dev, unsigned int format, 168 unsigned int byte_size, 169 struct snd_dma_buffer *bufp); 170 int (*trigger)(struct device *dev, bool start, int stream_tag); 171 172 int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab, 173 int stream_tag); 174 }; 175 176 struct skl_load_module_info { 177 u16 mod_id; 178 const struct firmware *fw; 179 }; 180 181 struct skl_module_table { 182 struct skl_load_module_info *mod_info; 183 unsigned int usage_cnt; 184 struct list_head list; 185 }; 186 187 void skl_cldma_process_intr(struct sst_dsp *ctx); 188 void skl_cldma_int_disable(struct sst_dsp *ctx); 189 int skl_cldma_prepare(struct sst_dsp *ctx); 190 191 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 192 struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 193 struct sst_dsp_device *sst_dev, int irq); 194 bool is_skl_dsp_running(struct sst_dsp *ctx); 195 196 unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx); 197 void skl_dsp_init_core_state(struct sst_dsp *ctx); 198 int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); 199 int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); 200 int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask); 201 int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask); 202 int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx, 203 unsigned int core_mask); 204 int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask); 205 206 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 207 int skl_dsp_wake(struct sst_dsp *ctx); 208 int skl_dsp_sleep(struct sst_dsp *ctx); 209 void skl_dsp_free(struct sst_dsp *dsp); 210 211 int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id); 212 int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id); 213 214 int skl_dsp_boot(struct sst_dsp *ctx); 215 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 216 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 217 struct skl_sst **dsp); 218 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 219 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 220 struct skl_sst **dsp); 221 int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx); 222 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx); 223 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 224 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 225 226 int snd_skl_get_module_info(struct skl_sst *ctx, 227 struct skl_module_cfg *mconfig); 228 int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, 229 unsigned int offset, int index); 230 int skl_get_pvt_id(struct skl_sst *ctx, 231 struct skl_module_cfg *mconfig); 232 int skl_put_pvt_id(struct skl_sst *ctx, 233 struct skl_module_cfg *mconfig); 234 int skl_get_pvt_instance_id_map(struct skl_sst *ctx, 235 int module_id, int instance_id); 236 void skl_freeup_uuid_list(struct skl_sst *ctx); 237 238 int skl_dsp_strip_extended_manifest(struct firmware *fw); 239 240 #endif /*__SKL_SST_DSP_H__*/ 241