1 /* 2 * Skylake SST DSP Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_SST_DSP_H__ 17 #define __SKL_SST_DSP_H__ 18 19 #include <sound/memalloc.h> 20 #include "skl-sst-cldma.h" 21 22 struct sst_dsp; 23 struct sst_dsp_device; 24 25 /* Intel HD Audio General DSP Registers */ 26 #define SKL_ADSP_GEN_BASE 0x0 27 #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 28 #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 29 #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 30 #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 31 #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 32 33 /* Intel HD Audio Inter-Processor Communication Registers */ 34 #define SKL_ADSP_IPC_BASE 0x40 35 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 36 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 37 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 38 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 39 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 40 41 /* HIPCI */ 42 #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 43 44 /* HIPCIE */ 45 #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 46 47 /* HIPCCTL */ 48 #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 49 #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 50 51 /* HIPCT */ 52 #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 53 54 /* Intel HD Audio SRAM Window 1 */ 55 #define SKL_ADSP_SRAM1_BASE 0xA000 56 57 #define SKL_ADSP_MMIO_LEN 0x10000 58 59 #define SKL_ADSP_W0_STAT_SZ 0x800 60 61 #define SKL_ADSP_W0_UP_SZ 0x800 62 63 #define SKL_ADSP_W1_SZ 0x1000 64 65 #define SKL_ADSPIC_IPC 1 66 #define SKL_ADSPIS_IPC 1 67 68 /* ADSPCS - Audio DSP Control & Status */ 69 #define SKL_DSP_CORES 1 70 #define SKL_DSP_CORE0_MASK 1 71 #define SKL_DSP_CORES_MASK ((1 << SKL_DSP_CORES) - 1) 72 73 /* Core Reset - asserted high */ 74 #define SKL_ADSPCS_CRST_SHIFT 0 75 #define SKL_ADSPCS_CRST_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT) 76 #define SKL_ADSPCS_CRST(x) ((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK) 77 78 /* Core run/stall - when set to '1' core is stalled */ 79 #define SKL_ADSPCS_CSTALL_SHIFT 8 80 #define SKL_ADSPCS_CSTALL_MASK (SKL_DSP_CORES_MASK << \ 81 SKL_ADSPCS_CSTALL_SHIFT) 82 #define SKL_ADSPCS_CSTALL(x) ((x << SKL_ADSPCS_CSTALL_SHIFT) & \ 83 SKL_ADSPCS_CSTALL_MASK) 84 85 /* Set Power Active - when set to '1' turn cores on */ 86 #define SKL_ADSPCS_SPA_SHIFT 16 87 #define SKL_ADSPCS_SPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT) 88 #define SKL_ADSPCS_SPA(x) ((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK) 89 90 /* Current Power Active - power status of cores, set by hardware */ 91 #define SKL_ADSPCS_CPA_SHIFT 24 92 #define SKL_ADSPCS_CPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT) 93 #define SKL_ADSPCS_CPA(x) ((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK) 94 95 #define SST_DSP_POWER_D0 0x0 /* full On */ 96 #define SST_DSP_POWER_D3 0x3 /* Off */ 97 98 enum skl_dsp_states { 99 SKL_DSP_RUNNING = 1, 100 SKL_DSP_RESET, 101 }; 102 103 struct skl_dsp_fw_ops { 104 int (*load_fw)(struct sst_dsp *ctx); 105 /* FW module parser/loader */ 106 int (*parse_fw)(struct sst_dsp *ctx); 107 int (*set_state_D0)(struct sst_dsp *ctx); 108 int (*set_state_D3)(struct sst_dsp *ctx); 109 }; 110 111 struct skl_dsp_loader_ops { 112 int (*alloc_dma_buf)(struct device *dev, 113 struct snd_dma_buffer *dmab, size_t size); 114 int (*free_dma_buf)(struct device *dev, 115 struct snd_dma_buffer *dmab); 116 }; 117 118 void skl_cldma_process_intr(struct sst_dsp *ctx); 119 void skl_cldma_int_disable(struct sst_dsp *ctx); 120 int skl_cldma_prepare(struct sst_dsp *ctx); 121 122 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 123 struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 124 struct sst_dsp_device *sst_dev, int irq); 125 int skl_dsp_disable_core(struct sst_dsp *ctx); 126 bool is_skl_dsp_running(struct sst_dsp *ctx); 127 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 128 int skl_dsp_wake(struct sst_dsp *ctx); 129 int skl_dsp_sleep(struct sst_dsp *ctx); 130 void skl_dsp_free(struct sst_dsp *dsp); 131 132 int skl_dsp_boot(struct sst_dsp *ctx); 133 134 #endif /*__SKL_SST_DSP_H__*/ 135