1 /* 2 * Skylake SST DSP Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_SST_DSP_H__ 17 #define __SKL_SST_DSP_H__ 18 19 #include <linux/interrupt.h> 20 #include <sound/memalloc.h> 21 #include "skl-sst-cldma.h" 22 #include "skl-tplg-interface.h" 23 24 struct sst_dsp; 25 struct skl_sst; 26 struct sst_dsp_device; 27 28 /* Intel HD Audio General DSP Registers */ 29 #define SKL_ADSP_GEN_BASE 0x0 30 #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 31 #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 32 #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 33 #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 34 #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 35 36 /* Intel HD Audio Inter-Processor Communication Registers */ 37 #define SKL_ADSP_IPC_BASE 0x40 38 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 39 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 40 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 41 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 42 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 43 44 /* HIPCI */ 45 #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 46 47 /* HIPCIE */ 48 #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 49 50 /* HIPCCTL */ 51 #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 52 #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 53 54 /* HIPCT */ 55 #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 56 57 /* FW base IDs */ 58 #define SKL_INSTANCE_ID 0 59 #define SKL_BASE_FW_MODULE_ID 0 60 61 /* Intel HD Audio SRAM Window 1 */ 62 #define SKL_ADSP_SRAM1_BASE 0xA000 63 64 #define SKL_ADSP_MMIO_LEN 0x10000 65 66 #define SKL_ADSP_W0_STAT_SZ 0x1000 67 68 #define SKL_ADSP_W0_UP_SZ 0x1000 69 70 #define SKL_ADSP_W1_SZ 0x1000 71 72 #define SKL_FW_STS_MASK 0xf 73 74 #define SKL_FW_INIT 0x1 75 #define SKL_FW_RFW_START 0xf 76 77 #define SKL_ADSPIC_IPC 1 78 #define SKL_ADSPIS_IPC 1 79 80 /* ADSPCS - Audio DSP Control & Status */ 81 #define SKL_DSP_CORES 1 82 #define SKL_DSP_CORE0_MASK 1 83 #define SKL_DSP_CORES_MASK ((1 << SKL_DSP_CORES) - 1) 84 85 /* Core Reset - asserted high */ 86 #define SKL_ADSPCS_CRST_SHIFT 0 87 #define SKL_ADSPCS_CRST_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT) 88 #define SKL_ADSPCS_CRST(x) ((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK) 89 90 /* Core run/stall - when set to '1' core is stalled */ 91 #define SKL_ADSPCS_CSTALL_SHIFT 8 92 #define SKL_ADSPCS_CSTALL_MASK (SKL_DSP_CORES_MASK << \ 93 SKL_ADSPCS_CSTALL_SHIFT) 94 #define SKL_ADSPCS_CSTALL(x) ((x << SKL_ADSPCS_CSTALL_SHIFT) & \ 95 SKL_ADSPCS_CSTALL_MASK) 96 97 /* Set Power Active - when set to '1' turn cores on */ 98 #define SKL_ADSPCS_SPA_SHIFT 16 99 #define SKL_ADSPCS_SPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT) 100 #define SKL_ADSPCS_SPA(x) ((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK) 101 102 /* Current Power Active - power status of cores, set by hardware */ 103 #define SKL_ADSPCS_CPA_SHIFT 24 104 #define SKL_ADSPCS_CPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT) 105 #define SKL_ADSPCS_CPA(x) ((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK) 106 107 #define SST_DSP_POWER_D0 0x0 /* full On */ 108 #define SST_DSP_POWER_D3 0x3 /* Off */ 109 110 enum skl_dsp_states { 111 SKL_DSP_RUNNING = 1, 112 SKL_DSP_RESET, 113 }; 114 115 struct skl_dsp_fw_ops { 116 int (*load_fw)(struct sst_dsp *ctx); 117 /* FW module parser/loader */ 118 int (*parse_fw)(struct sst_dsp *ctx); 119 int (*set_state_D0)(struct sst_dsp *ctx); 120 int (*set_state_D3)(struct sst_dsp *ctx); 121 unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); 122 int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name); 123 int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); 124 125 }; 126 127 struct skl_dsp_loader_ops { 128 int stream_tag; 129 130 int (*alloc_dma_buf)(struct device *dev, 131 struct snd_dma_buffer *dmab, size_t size); 132 int (*free_dma_buf)(struct device *dev, 133 struct snd_dma_buffer *dmab); 134 int (*prepare)(struct device *dev, unsigned int format, 135 unsigned int byte_size, 136 struct snd_dma_buffer *bufp); 137 int (*trigger)(struct device *dev, bool start, int stream_tag); 138 139 int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab, 140 int stream_tag); 141 }; 142 143 struct skl_load_module_info { 144 u16 mod_id; 145 const struct firmware *fw; 146 }; 147 148 struct skl_module_table { 149 struct skl_load_module_info *mod_info; 150 unsigned int usage_cnt; 151 struct list_head list; 152 }; 153 154 void skl_cldma_process_intr(struct sst_dsp *ctx); 155 void skl_cldma_int_disable(struct sst_dsp *ctx); 156 int skl_cldma_prepare(struct sst_dsp *ctx); 157 158 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 159 struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 160 struct sst_dsp_device *sst_dev, int irq); 161 int skl_dsp_enable_core(struct sst_dsp *ctx); 162 int skl_dsp_disable_core(struct sst_dsp *ctx); 163 bool is_skl_dsp_running(struct sst_dsp *ctx); 164 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 165 int skl_dsp_wake(struct sst_dsp *ctx); 166 int skl_dsp_sleep(struct sst_dsp *ctx); 167 void skl_dsp_free(struct sst_dsp *dsp); 168 169 int skl_dsp_boot(struct sst_dsp *ctx); 170 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 171 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 172 struct skl_sst **dsp); 173 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 174 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 175 struct skl_sst **dsp); 176 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 177 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 178 179 int snd_skl_get_module_info(struct skl_sst *ctx, u8 *uuid, 180 struct skl_dfw_module *dfw_config); 181 int snd_skl_parse_uuids(struct sst_dsp *ctx, unsigned int offset); 182 void skl_freeup_uuid_list(struct skl_sst *ctx); 183 184 int skl_dsp_strip_extended_manifest(struct firmware *fw); 185 int skl_dsp_start_core(struct sst_dsp *ctx); 186 int skl_dsp_core_power_up(struct sst_dsp *ctx); 187 188 #endif /*__SKL_SST_DSP_H__*/ 189