1 /*
2  * Skylake SST DSP Support
3  *
4  * Copyright (C) 2014-15, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as version 2, as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  */
15 
16 #ifndef __SKL_SST_DSP_H__
17 #define __SKL_SST_DSP_H__
18 
19 #include <linux/interrupt.h>
20 #include <linux/uuid.h>
21 #include <linux/firmware.h>
22 #include <sound/memalloc.h>
23 #include "skl-sst-cldma.h"
24 
25 struct sst_dsp;
26 struct skl_sst;
27 struct sst_dsp_device;
28 struct skl_lib_info;
29 
30 /* Intel HD Audio General DSP Registers */
31 #define SKL_ADSP_GEN_BASE		0x0
32 #define SKL_ADSP_REG_ADSPCS		(SKL_ADSP_GEN_BASE + 0x04)
33 #define SKL_ADSP_REG_ADSPIC		(SKL_ADSP_GEN_BASE + 0x08)
34 #define SKL_ADSP_REG_ADSPIS		(SKL_ADSP_GEN_BASE + 0x0C)
35 #define SKL_ADSP_REG_ADSPIC2		(SKL_ADSP_GEN_BASE + 0x10)
36 #define SKL_ADSP_REG_ADSPIS2		(SKL_ADSP_GEN_BASE + 0x14)
37 
38 /* Intel HD Audio Inter-Processor Communication Registers */
39 #define SKL_ADSP_IPC_BASE		0x40
40 #define SKL_ADSP_REG_HIPCT		(SKL_ADSP_IPC_BASE + 0x00)
41 #define SKL_ADSP_REG_HIPCTE		(SKL_ADSP_IPC_BASE + 0x04)
42 #define SKL_ADSP_REG_HIPCI		(SKL_ADSP_IPC_BASE + 0x08)
43 #define SKL_ADSP_REG_HIPCIE		(SKL_ADSP_IPC_BASE + 0x0C)
44 #define SKL_ADSP_REG_HIPCCTL		(SKL_ADSP_IPC_BASE + 0x10)
45 
46 /*  HIPCI */
47 #define SKL_ADSP_REG_HIPCI_BUSY		BIT(31)
48 
49 /* HIPCIE */
50 #define SKL_ADSP_REG_HIPCIE_DONE	BIT(30)
51 
52 /* HIPCCTL */
53 #define SKL_ADSP_REG_HIPCCTL_DONE	BIT(1)
54 #define SKL_ADSP_REG_HIPCCTL_BUSY	BIT(0)
55 
56 /* HIPCT */
57 #define SKL_ADSP_REG_HIPCT_BUSY		BIT(31)
58 
59 /* FW base IDs */
60 #define SKL_INSTANCE_ID			0
61 #define SKL_BASE_FW_MODULE_ID		0
62 
63 /* Intel HD Audio SRAM Window 1 */
64 #define SKL_ADSP_SRAM1_BASE		0xA000
65 
66 #define SKL_ADSP_MMIO_LEN		0x10000
67 
68 #define SKL_ADSP_W0_STAT_SZ		0x1000
69 
70 #define SKL_ADSP_W0_UP_SZ		0x1000
71 
72 #define SKL_ADSP_W1_SZ			0x1000
73 
74 #define SKL_FW_STS_MASK			0xf
75 
76 #define SKL_FW_INIT			0x1
77 #define SKL_FW_RFW_START		0xf
78 
79 #define SKL_ADSPIC_IPC			1
80 #define SKL_ADSPIS_IPC			1
81 
82 /* Core ID of core0 */
83 #define SKL_DSP_CORE0_ID		0
84 
85 /* Mask for a given core index, c = 0.. number of supported cores - 1 */
86 #define SKL_DSP_CORE_MASK(c)		BIT(c)
87 
88 /*
89  * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately
90  * since Core0 is primary core and it is used often
91  */
92 #define SKL_DSP_CORE0_MASK		BIT(0)
93 
94 /*
95  * Mask for a given number of cores
96  * nc = number of supported cores
97  */
98 #define SKL_DSP_CORES_MASK(nc)	GENMASK((nc - 1), 0)
99 
100 /* ADSPCS - Audio DSP Control & Status */
101 
102 /*
103  * Core Reset - asserted high
104  * CRST Mask for a given core mask pattern, cm
105  */
106 #define SKL_ADSPCS_CRST_SHIFT		0
107 #define SKL_ADSPCS_CRST_MASK(cm)	((cm) << SKL_ADSPCS_CRST_SHIFT)
108 
109 /*
110  * Core run/stall - when set to '1' core is stalled
111  * CSTALL Mask for a given core mask pattern, cm
112  */
113 #define SKL_ADSPCS_CSTALL_SHIFT		8
114 #define SKL_ADSPCS_CSTALL_MASK(cm)	((cm) << SKL_ADSPCS_CSTALL_SHIFT)
115 
116 /*
117  * Set Power Active - when set to '1' turn cores on
118  * SPA Mask for a given core mask pattern, cm
119  */
120 #define SKL_ADSPCS_SPA_SHIFT		16
121 #define SKL_ADSPCS_SPA_MASK(cm)		((cm) << SKL_ADSPCS_SPA_SHIFT)
122 
123 /*
124  * Current Power Active - power status of cores, set by hardware
125  * CPA Mask for a given core mask pattern, cm
126  */
127 #define SKL_ADSPCS_CPA_SHIFT		24
128 #define SKL_ADSPCS_CPA_MASK(cm)		((cm) << SKL_ADSPCS_CPA_SHIFT)
129 
130 /* DSP Core state */
131 enum skl_dsp_states {
132 	SKL_DSP_RUNNING = 1,
133 	/* Running in D0i3 state; can be in streaming or non-streaming D0i3 */
134 	SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/
135 	SKL_DSP_RESET,
136 };
137 
138 /* D0i3 substates */
139 enum skl_dsp_d0i3_states {
140 	SKL_DSP_D0I3_NONE = -1, /* No D0i3 */
141 	SKL_DSP_D0I3_NON_STREAMING = 0,
142 	SKL_DSP_D0I3_STREAMING = 1,
143 };
144 
145 struct skl_dsp_fw_ops {
146 	int (*load_fw)(struct sst_dsp  *ctx);
147 	/* FW module parser/loader */
148 	int (*load_library)(struct sst_dsp *ctx,
149 		struct skl_lib_info *linfo, int lib_count);
150 	int (*parse_fw)(struct sst_dsp *ctx);
151 	int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id);
152 	int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id);
153 	int (*set_state_D0i3)(struct sst_dsp *ctx);
154 	int (*set_state_D0i0)(struct sst_dsp *ctx);
155 	unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
156 	int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
157 	int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
158 
159 };
160 
161 struct skl_dsp_loader_ops {
162 	int stream_tag;
163 
164 	int (*alloc_dma_buf)(struct device *dev,
165 		struct snd_dma_buffer *dmab, size_t size);
166 	int (*free_dma_buf)(struct device *dev,
167 		struct snd_dma_buffer *dmab);
168 	int (*prepare)(struct device *dev, unsigned int format,
169 				unsigned int byte_size,
170 				struct snd_dma_buffer *bufp);
171 	int (*trigger)(struct device *dev, bool start, int stream_tag);
172 
173 	int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
174 				 int stream_tag);
175 };
176 
177 #define MAX_INSTANCE_BUFF 2
178 
179 struct uuid_module {
180 	uuid_le uuid;
181 	int id;
182 	int is_loadable;
183 	int max_instance;
184 	u64 pvt_id[MAX_INSTANCE_BUFF];
185 	int *instance_id;
186 
187 	struct list_head list;
188 };
189 
190 struct skl_load_module_info {
191 	u16 mod_id;
192 	const struct firmware *fw;
193 };
194 
195 struct skl_module_table {
196 	struct skl_load_module_info *mod_info;
197 	unsigned int usage_cnt;
198 	struct list_head list;
199 };
200 
201 void skl_cldma_process_intr(struct sst_dsp *ctx);
202 void skl_cldma_int_disable(struct sst_dsp *ctx);
203 int skl_cldma_prepare(struct sst_dsp *ctx);
204 int skl_cldma_wait_interruptible(struct sst_dsp *ctx);
205 
206 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
207 struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
208 		struct sst_dsp_device *sst_dev, int irq);
209 int skl_dsp_acquire_irq(struct sst_dsp *sst);
210 bool is_skl_dsp_running(struct sst_dsp *ctx);
211 
212 unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx);
213 void skl_dsp_init_core_state(struct sst_dsp *ctx);
214 int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
215 int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
216 int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask);
217 int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask);
218 int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx,
219 					unsigned int core_mask);
220 int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask);
221 
222 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
223 int skl_dsp_wake(struct sst_dsp *ctx);
224 int skl_dsp_sleep(struct sst_dsp *ctx);
225 void skl_dsp_free(struct sst_dsp *dsp);
226 
227 int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id);
228 int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id);
229 
230 int skl_dsp_boot(struct sst_dsp *ctx);
231 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
232 		const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
233 		struct skl_sst **dsp);
234 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
235 		const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
236 		struct skl_sst **dsp);
237 int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx);
238 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx);
239 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
240 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
241 
242 int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw,
243 				unsigned int offset, int index);
244 int skl_get_pvt_id(struct skl_sst *ctx, uuid_le *uuid_mod, int instance_id);
245 int skl_put_pvt_id(struct skl_sst *ctx, uuid_le *uuid_mod, int *pvt_id);
246 int skl_get_pvt_instance_id_map(struct skl_sst *ctx,
247 				int module_id, int instance_id);
248 void skl_freeup_uuid_list(struct skl_sst *ctx);
249 
250 int skl_dsp_strip_extended_manifest(struct firmware *fw);
251 void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable);
252 
253 void skl_dsp_set_astate_cfg(struct skl_sst *ctx, u32 cnt, void *data);
254 
255 int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name,
256 		struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp,
257 		struct sst_dsp_device *skl_dev);
258 int skl_prepare_lib_load(struct skl_sst *skl, struct skl_lib_info *linfo,
259 			struct firmware *stripped_fw,
260 			unsigned int hdr_offset, int index);
261 void skl_release_library(struct skl_lib_info *linfo, int lib_count);
262 
263 #endif /*__SKL_SST_DSP_H__*/
264