13582f9aeSSubhransu S. Prusty /* 23582f9aeSSubhransu S. Prusty * Skylake SST DSP Support 33582f9aeSSubhransu S. Prusty * 43582f9aeSSubhransu S. Prusty * Copyright (C) 2014-15, Intel Corporation. 53582f9aeSSubhransu S. Prusty * 63582f9aeSSubhransu S. Prusty * This program is free software; you can redistribute it and/or modify 73582f9aeSSubhransu S. Prusty * it under the terms of the GNU General Public License as version 2, as 83582f9aeSSubhransu S. Prusty * published by the Free Software Foundation. 93582f9aeSSubhransu S. Prusty * 103582f9aeSSubhransu S. Prusty * This program is distributed in the hope that it will be useful, but 113582f9aeSSubhransu S. Prusty * WITHOUT ANY WARRANTY; without even the implied warranty of 123582f9aeSSubhransu S. Prusty * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 133582f9aeSSubhransu S. Prusty * General Public License for more details. 143582f9aeSSubhransu S. Prusty */ 153582f9aeSSubhransu S. Prusty 163582f9aeSSubhransu S. Prusty #ifndef __SKL_SST_DSP_H__ 173582f9aeSSubhransu S. Prusty #define __SKL_SST_DSP_H__ 183582f9aeSSubhransu S. Prusty 19a750ba5fSSubhransu S. Prusty #include <linux/interrupt.h> 20b6626802SSubhransu S. Prusty #include <sound/memalloc.h> 213e40a784SVinod Koul #include "skl-sst-cldma.h" 22ea6b3e94SShreyas NC #include "skl-tplg-interface.h" 230556ba46SDharageswari R #include "skl-topology.h" 24b6626802SSubhransu S. Prusty 253e40a784SVinod Koul struct sst_dsp; 26a750ba5fSSubhransu S. Prusty struct skl_sst; 27e973e31aSSubhransu S. Prusty struct sst_dsp_device; 28e973e31aSSubhransu S. Prusty 293582f9aeSSubhransu S. Prusty /* Intel HD Audio General DSP Registers */ 303582f9aeSSubhransu S. Prusty #define SKL_ADSP_GEN_BASE 0x0 313582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 323582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 333582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 343582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 353582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 363582f9aeSSubhransu S. Prusty 373582f9aeSSubhransu S. Prusty /* Intel HD Audio Inter-Processor Communication Registers */ 383582f9aeSSubhransu S. Prusty #define SKL_ADSP_IPC_BASE 0x40 393582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 403582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 413582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 423582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 433582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 443582f9aeSSubhransu S. Prusty 453582f9aeSSubhransu S. Prusty /* HIPCI */ 463582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 473582f9aeSSubhransu S. Prusty 483582f9aeSSubhransu S. Prusty /* HIPCIE */ 493582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 503582f9aeSSubhransu S. Prusty 513582f9aeSSubhransu S. Prusty /* HIPCCTL */ 523582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 533582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 543582f9aeSSubhransu S. Prusty 553582f9aeSSubhransu S. Prusty /* HIPCT */ 563582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 573582f9aeSSubhransu S. Prusty 5839fa37d5SVinod Koul /* FW base IDs */ 5939fa37d5SVinod Koul #define SKL_INSTANCE_ID 0 6039fa37d5SVinod Koul #define SKL_BASE_FW_MODULE_ID 0 6139fa37d5SVinod Koul 623582f9aeSSubhransu S. Prusty /* Intel HD Audio SRAM Window 1 */ 633582f9aeSSubhransu S. Prusty #define SKL_ADSP_SRAM1_BASE 0xA000 643582f9aeSSubhransu S. Prusty 653582f9aeSSubhransu S. Prusty #define SKL_ADSP_MMIO_LEN 0x10000 663582f9aeSSubhransu S. Prusty 67c99b8056SOmair M Abdullah #define SKL_ADSP_W0_STAT_SZ 0x1000 683582f9aeSSubhransu S. Prusty 69c99b8056SOmair M Abdullah #define SKL_ADSP_W0_UP_SZ 0x1000 703582f9aeSSubhransu S. Prusty 713582f9aeSSubhransu S. Prusty #define SKL_ADSP_W1_SZ 0x1000 723582f9aeSSubhransu S. Prusty 73a750ba5fSSubhransu S. Prusty #define SKL_FW_STS_MASK 0xf 74a750ba5fSSubhransu S. Prusty 75a750ba5fSSubhransu S. Prusty #define SKL_FW_INIT 0x1 76a750ba5fSSubhransu S. Prusty #define SKL_FW_RFW_START 0xf 77a750ba5fSSubhransu S. Prusty 783582f9aeSSubhransu S. Prusty #define SKL_ADSPIC_IPC 1 793582f9aeSSubhransu S. Prusty #define SKL_ADSPIS_IPC 1 803582f9aeSSubhransu S. Prusty 81052f103cSJayachandran B /* Core ID of core0 */ 82052f103cSJayachandran B #define SKL_DSP_CORE0_ID 0 83052f103cSJayachandran B 84052f103cSJayachandran B /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 85052f103cSJayachandran B #define SKL_DSP_CORE_MASK(c) BIT(c) 86052f103cSJayachandran B 87052f103cSJayachandran B /* 88052f103cSJayachandran B * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately 89052f103cSJayachandran B * since Core0 is primary core and it is used often 90052f103cSJayachandran B */ 91052f103cSJayachandran B #define SKL_DSP_CORE0_MASK BIT(0) 92052f103cSJayachandran B 93052f103cSJayachandran B /* 94052f103cSJayachandran B * Mask for a given number of cores 95052f103cSJayachandran B * nc = number of supported cores 96052f103cSJayachandran B */ 97052f103cSJayachandran B #define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0) 98052f103cSJayachandran B 99e973e31aSSubhransu S. Prusty /* ADSPCS - Audio DSP Control & Status */ 100e973e31aSSubhransu S. Prusty 101052f103cSJayachandran B /* 102052f103cSJayachandran B * Core Reset - asserted high 103052f103cSJayachandran B * CRST Mask for a given core mask pattern, cm 104052f103cSJayachandran B */ 105e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_CRST_SHIFT 0 106052f103cSJayachandran B #define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT) 107e973e31aSSubhransu S. Prusty 108052f103cSJayachandran B /* 109052f103cSJayachandran B * Core run/stall - when set to '1' core is stalled 110052f103cSJayachandran B * CSTALL Mask for a given core mask pattern, cm 111052f103cSJayachandran B */ 112e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_CSTALL_SHIFT 8 113052f103cSJayachandran B #define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT) 114e973e31aSSubhransu S. Prusty 115052f103cSJayachandran B /* 116052f103cSJayachandran B * Set Power Active - when set to '1' turn cores on 117052f103cSJayachandran B * SPA Mask for a given core mask pattern, cm 118052f103cSJayachandran B */ 119e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_SPA_SHIFT 16 120052f103cSJayachandran B #define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT) 121e973e31aSSubhransu S. Prusty 122052f103cSJayachandran B /* 123052f103cSJayachandran B * Current Power Active - power status of cores, set by hardware 124052f103cSJayachandran B * CPA Mask for a given core mask pattern, cm 125052f103cSJayachandran B */ 126e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_CPA_SHIFT 24 127052f103cSJayachandran B #define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT) 128e973e31aSSubhransu S. Prusty 129e973e31aSSubhransu S. Prusty enum skl_dsp_states { 130e973e31aSSubhransu S. Prusty SKL_DSP_RUNNING = 1, 131e973e31aSSubhransu S. Prusty SKL_DSP_RESET, 132e973e31aSSubhransu S. Prusty }; 133e973e31aSSubhransu S. Prusty 134e973e31aSSubhransu S. Prusty struct skl_dsp_fw_ops { 135e973e31aSSubhransu S. Prusty int (*load_fw)(struct sst_dsp *ctx); 136e973e31aSSubhransu S. Prusty /* FW module parser/loader */ 1371ef015e6SRamesh Babu int (*load_library)(struct sst_dsp *ctx, 1381ef015e6SRamesh Babu struct skl_dfw_manifest *minfo); 139e973e31aSSubhransu S. Prusty int (*parse_fw)(struct sst_dsp *ctx); 140052f103cSJayachandran B int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id); 141052f103cSJayachandran B int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id); 142a750ba5fSSubhransu S. Prusty unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); 14309305da9SShreyas NC int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name); 1446c5768b3SDharageswari R int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); 1456c5768b3SDharageswari R 146e973e31aSSubhransu S. Prusty }; 147e973e31aSSubhransu S. Prusty 148b6626802SSubhransu S. Prusty struct skl_dsp_loader_ops { 14992eb4f62SJeeja KP int stream_tag; 15092eb4f62SJeeja KP 151b6626802SSubhransu S. Prusty int (*alloc_dma_buf)(struct device *dev, 152b6626802SSubhransu S. Prusty struct snd_dma_buffer *dmab, size_t size); 153b6626802SSubhransu S. Prusty int (*free_dma_buf)(struct device *dev, 154b6626802SSubhransu S. Prusty struct snd_dma_buffer *dmab); 15592eb4f62SJeeja KP int (*prepare)(struct device *dev, unsigned int format, 15692eb4f62SJeeja KP unsigned int byte_size, 15792eb4f62SJeeja KP struct snd_dma_buffer *bufp); 15892eb4f62SJeeja KP int (*trigger)(struct device *dev, bool start, int stream_tag); 15992eb4f62SJeeja KP 16092eb4f62SJeeja KP int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab, 16192eb4f62SJeeja KP int stream_tag); 162b6626802SSubhransu S. Prusty }; 163b6626802SSubhransu S. Prusty 1646c5768b3SDharageswari R struct skl_load_module_info { 1656c5768b3SDharageswari R u16 mod_id; 1666c5768b3SDharageswari R const struct firmware *fw; 1676c5768b3SDharageswari R }; 1686c5768b3SDharageswari R 1696c5768b3SDharageswari R struct skl_module_table { 1706c5768b3SDharageswari R struct skl_load_module_info *mod_info; 1716c5768b3SDharageswari R unsigned int usage_cnt; 1726c5768b3SDharageswari R struct list_head list; 1736c5768b3SDharageswari R }; 1746c5768b3SDharageswari R 1753e40a784SVinod Koul void skl_cldma_process_intr(struct sst_dsp *ctx); 1763e40a784SVinod Koul void skl_cldma_int_disable(struct sst_dsp *ctx); 1773e40a784SVinod Koul int skl_cldma_prepare(struct sst_dsp *ctx); 1783e40a784SVinod Koul 179e973e31aSSubhransu S. Prusty void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 180e973e31aSSubhransu S. Prusty struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 181e973e31aSSubhransu S. Prusty struct sst_dsp_device *sst_dev, int irq); 182e973e31aSSubhransu S. Prusty bool is_skl_dsp_running(struct sst_dsp *ctx); 183052f103cSJayachandran B 184052f103cSJayachandran B unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx); 185052f103cSJayachandran B void skl_dsp_init_core_state(struct sst_dsp *ctx); 186052f103cSJayachandran B int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); 187052f103cSJayachandran B int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); 188052f103cSJayachandran B int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask); 189052f103cSJayachandran B int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask); 190052f103cSJayachandran B int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx, 191052f103cSJayachandran B unsigned int core_mask); 192052f103cSJayachandran B int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask); 193052f103cSJayachandran B 194e973e31aSSubhransu S. Prusty irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 195e973e31aSSubhransu S. Prusty int skl_dsp_wake(struct sst_dsp *ctx); 196e973e31aSSubhransu S. Prusty int skl_dsp_sleep(struct sst_dsp *ctx); 197e973e31aSSubhransu S. Prusty void skl_dsp_free(struct sst_dsp *dsp); 198e973e31aSSubhransu S. Prusty 199052f103cSJayachandran B int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id); 200052f103cSJayachandran B int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id); 201052f103cSJayachandran B 202e973e31aSSubhransu S. Prusty int skl_dsp_boot(struct sst_dsp *ctx); 203a750ba5fSSubhransu S. Prusty int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 204aecf6fd8SVinod Koul const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 205aecf6fd8SVinod Koul struct skl_sst **dsp); 20692eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 20792eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 20892eb4f62SJeeja KP struct skl_sst **dsp); 20978cdbbdaSVinod Koul int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx); 21078cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx); 211a750ba5fSSubhransu S. Prusty void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 21292eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); 213e973e31aSSubhransu S. Prusty 2140556ba46SDharageswari R int snd_skl_get_module_info(struct skl_sst *ctx, 2150556ba46SDharageswari R struct skl_module_cfg *mconfig); 216a8e2c19eSSenthilnathan Veppur int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, 217a8e2c19eSSenthilnathan Veppur unsigned int offset, int index); 218700a9a63SDharageswari R int skl_get_pvt_id(struct skl_sst *ctx, 219700a9a63SDharageswari R struct skl_module_cfg *mconfig); 220700a9a63SDharageswari R int skl_put_pvt_id(struct skl_sst *ctx, 221700a9a63SDharageswari R struct skl_module_cfg *mconfig); 22255a92ea9SDharageswari R int skl_get_pvt_instance_id_map(struct skl_sst *ctx, 22355a92ea9SDharageswari R int module_id, int instance_id); 224ea6b3e94SShreyas NC void skl_freeup_uuid_list(struct skl_sst *ctx); 225ea6b3e94SShreyas NC 2266eee8726SRamesh Babu int skl_dsp_strip_extended_manifest(struct firmware *fw); 2276eee8726SRamesh Babu 2283582f9aeSSubhransu S. Prusty #endif /*__SKL_SST_DSP_H__*/ 229