147d7195dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 23582f9aeSSubhransu S. Prusty /* 33582f9aeSSubhransu S. Prusty * Skylake SST DSP Support 43582f9aeSSubhransu S. Prusty * 53582f9aeSSubhransu S. Prusty * Copyright (C) 2014-15, Intel Corporation. 63582f9aeSSubhransu S. Prusty */ 73582f9aeSSubhransu S. Prusty 83582f9aeSSubhransu S. Prusty #ifndef __SKL_SST_DSP_H__ 93582f9aeSSubhransu S. Prusty #define __SKL_SST_DSP_H__ 103582f9aeSSubhransu S. Prusty 11a750ba5fSSubhransu S. Prusty #include <linux/interrupt.h> 12b26199eaSJeeja KP #include <linux/uuid.h> 13ebe89076SSubhransu S. Prusty #include <linux/firmware.h> 14b6626802SSubhransu S. Prusty #include <sound/memalloc.h> 153e40a784SVinod Koul #include "skl-sst-cldma.h" 16b6626802SSubhransu S. Prusty 173e40a784SVinod Koul struct sst_dsp; 18e973e31aSSubhransu S. Prusty struct sst_dsp_device; 19b26199eaSJeeja KP struct skl_lib_info; 20bcc2a2dcSCezary Rojewski struct skl_dev; 21e973e31aSSubhransu S. Prusty 223582f9aeSSubhransu S. Prusty /* Intel HD Audio General DSP Registers */ 233582f9aeSSubhransu S. Prusty #define SKL_ADSP_GEN_BASE 0x0 243582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) 253582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) 263582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) 273582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) 283582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) 293582f9aeSSubhransu S. Prusty 303582f9aeSSubhransu S. Prusty /* Intel HD Audio Inter-Processor Communication Registers */ 313582f9aeSSubhransu S. Prusty #define SKL_ADSP_IPC_BASE 0x40 323582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 333582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 343582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 353582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 363582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 373582f9aeSSubhransu S. Prusty 383582f9aeSSubhransu S. Prusty /* HIPCI */ 393582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) 403582f9aeSSubhransu S. Prusty 413582f9aeSSubhransu S. Prusty /* HIPCIE */ 423582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) 433582f9aeSSubhransu S. Prusty 443582f9aeSSubhransu S. Prusty /* HIPCCTL */ 453582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) 463582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) 473582f9aeSSubhransu S. Prusty 483582f9aeSSubhransu S. Prusty /* HIPCT */ 493582f9aeSSubhransu S. Prusty #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) 503582f9aeSSubhransu S. Prusty 5139fa37d5SVinod Koul /* FW base IDs */ 5239fa37d5SVinod Koul #define SKL_INSTANCE_ID 0 5339fa37d5SVinod Koul #define SKL_BASE_FW_MODULE_ID 0 5439fa37d5SVinod Koul 553582f9aeSSubhransu S. Prusty /* Intel HD Audio SRAM Window 1 */ 563582f9aeSSubhransu S. Prusty #define SKL_ADSP_SRAM1_BASE 0xA000 573582f9aeSSubhransu S. Prusty 583582f9aeSSubhransu S. Prusty #define SKL_ADSP_MMIO_LEN 0x10000 593582f9aeSSubhransu S. Prusty 60c99b8056SOmair M Abdullah #define SKL_ADSP_W0_STAT_SZ 0x1000 613582f9aeSSubhransu S. Prusty 62c99b8056SOmair M Abdullah #define SKL_ADSP_W0_UP_SZ 0x1000 633582f9aeSSubhransu S. Prusty 643582f9aeSSubhransu S. Prusty #define SKL_ADSP_W1_SZ 0x1000 653582f9aeSSubhransu S. Prusty 66a750ba5fSSubhransu S. Prusty #define SKL_FW_STS_MASK 0xf 67a750ba5fSSubhransu S. Prusty 68a750ba5fSSubhransu S. Prusty #define SKL_FW_INIT 0x1 69a750ba5fSSubhransu S. Prusty #define SKL_FW_RFW_START 0xf 70024aa45fSCezary Rojewski #define BXT_FW_ROM_INIT_RETRY 3 717693cadaSCezary Rojewski #define BXT_INIT_TIMEOUT 300 72a750ba5fSSubhransu S. Prusty 733582f9aeSSubhransu S. Prusty #define SKL_ADSPIC_IPC 1 743582f9aeSSubhransu S. Prusty #define SKL_ADSPIS_IPC 1 753582f9aeSSubhransu S. Prusty 76052f103cSJayachandran B /* Core ID of core0 */ 77052f103cSJayachandran B #define SKL_DSP_CORE0_ID 0 78052f103cSJayachandran B 79052f103cSJayachandran B /* Mask for a given core index, c = 0.. number of supported cores - 1 */ 80052f103cSJayachandran B #define SKL_DSP_CORE_MASK(c) BIT(c) 81052f103cSJayachandran B 82052f103cSJayachandran B /* 83052f103cSJayachandran B * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately 84052f103cSJayachandran B * since Core0 is primary core and it is used often 85052f103cSJayachandran B */ 86052f103cSJayachandran B #define SKL_DSP_CORE0_MASK BIT(0) 87052f103cSJayachandran B 88052f103cSJayachandran B /* 89052f103cSJayachandran B * Mask for a given number of cores 90052f103cSJayachandran B * nc = number of supported cores 91052f103cSJayachandran B */ 92052f103cSJayachandran B #define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0) 93052f103cSJayachandran B 94e973e31aSSubhransu S. Prusty /* ADSPCS - Audio DSP Control & Status */ 95e973e31aSSubhransu S. Prusty 96052f103cSJayachandran B /* 97052f103cSJayachandran B * Core Reset - asserted high 98052f103cSJayachandran B * CRST Mask for a given core mask pattern, cm 99052f103cSJayachandran B */ 100e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_CRST_SHIFT 0 101052f103cSJayachandran B #define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT) 102e973e31aSSubhransu S. Prusty 103052f103cSJayachandran B /* 104052f103cSJayachandran B * Core run/stall - when set to '1' core is stalled 105052f103cSJayachandran B * CSTALL Mask for a given core mask pattern, cm 106052f103cSJayachandran B */ 107e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_CSTALL_SHIFT 8 108052f103cSJayachandran B #define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT) 109e973e31aSSubhransu S. Prusty 110052f103cSJayachandran B /* 111052f103cSJayachandran B * Set Power Active - when set to '1' turn cores on 112052f103cSJayachandran B * SPA Mask for a given core mask pattern, cm 113052f103cSJayachandran B */ 114e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_SPA_SHIFT 16 115052f103cSJayachandran B #define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT) 116e973e31aSSubhransu S. Prusty 117052f103cSJayachandran B /* 118052f103cSJayachandran B * Current Power Active - power status of cores, set by hardware 119052f103cSJayachandran B * CPA Mask for a given core mask pattern, cm 120052f103cSJayachandran B */ 121e973e31aSSubhransu S. Prusty #define SKL_ADSPCS_CPA_SHIFT 24 122052f103cSJayachandran B #define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT) 123e973e31aSSubhransu S. Prusty 1245bb4cd46SJayachandran B /* DSP Core state */ 125e973e31aSSubhransu S. Prusty enum skl_dsp_states { 126e973e31aSSubhransu S. Prusty SKL_DSP_RUNNING = 1, 1275bb4cd46SJayachandran B /* Running in D0i3 state; can be in streaming or non-streaming D0i3 */ 1285bb4cd46SJayachandran B SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/ 129e973e31aSSubhransu S. Prusty SKL_DSP_RESET, 130e973e31aSSubhransu S. Prusty }; 131e973e31aSSubhransu S. Prusty 1325bb4cd46SJayachandran B /* D0i3 substates */ 1335bb4cd46SJayachandran B enum skl_dsp_d0i3_states { 1345bb4cd46SJayachandran B SKL_DSP_D0I3_NONE = -1, /* No D0i3 */ 1355bb4cd46SJayachandran B SKL_DSP_D0I3_NON_STREAMING = 0, 1365bb4cd46SJayachandran B SKL_DSP_D0I3_STREAMING = 1, 1375bb4cd46SJayachandran B }; 1385bb4cd46SJayachandran B 139e973e31aSSubhransu S. Prusty struct skl_dsp_fw_ops { 140e973e31aSSubhransu S. Prusty int (*load_fw)(struct sst_dsp *ctx); 141e973e31aSSubhransu S. Prusty /* FW module parser/loader */ 1421ef015e6SRamesh Babu int (*load_library)(struct sst_dsp *ctx, 143ebe89076SSubhransu S. Prusty struct skl_lib_info *linfo, int lib_count); 144e973e31aSSubhransu S. Prusty int (*parse_fw)(struct sst_dsp *ctx); 145052f103cSJayachandran B int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id); 146052f103cSJayachandran B int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id); 1475bb4cd46SJayachandran B int (*set_state_D0i3)(struct sst_dsp *ctx); 1485bb4cd46SJayachandran B int (*set_state_D0i0)(struct sst_dsp *ctx); 149a750ba5fSSubhransu S. Prusty unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); 15009305da9SShreyas NC int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name); 1516c5768b3SDharageswari R int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); 1526c5768b3SDharageswari R 153e973e31aSSubhransu S. Prusty }; 154e973e31aSSubhransu S. Prusty 155b6626802SSubhransu S. Prusty struct skl_dsp_loader_ops { 15692eb4f62SJeeja KP int stream_tag; 15792eb4f62SJeeja KP 158b6626802SSubhransu S. Prusty int (*alloc_dma_buf)(struct device *dev, 159b6626802SSubhransu S. Prusty struct snd_dma_buffer *dmab, size_t size); 160b6626802SSubhransu S. Prusty int (*free_dma_buf)(struct device *dev, 161b6626802SSubhransu S. Prusty struct snd_dma_buffer *dmab); 16292eb4f62SJeeja KP int (*prepare)(struct device *dev, unsigned int format, 16392eb4f62SJeeja KP unsigned int byte_size, 16492eb4f62SJeeja KP struct snd_dma_buffer *bufp); 16592eb4f62SJeeja KP int (*trigger)(struct device *dev, bool start, int stream_tag); 16692eb4f62SJeeja KP 16792eb4f62SJeeja KP int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab, 16892eb4f62SJeeja KP int stream_tag); 169b6626802SSubhransu S. Prusty }; 170b6626802SSubhransu S. Prusty 171b26199eaSJeeja KP #define MAX_INSTANCE_BUFF 2 172b26199eaSJeeja KP 173b26199eaSJeeja KP struct uuid_module { 1749e0784d0SAndy Shevchenko guid_t uuid; 175b26199eaSJeeja KP int id; 176b26199eaSJeeja KP int is_loadable; 177b26199eaSJeeja KP int max_instance; 178b26199eaSJeeja KP u64 pvt_id[MAX_INSTANCE_BUFF]; 179b26199eaSJeeja KP int *instance_id; 180b26199eaSJeeja KP 181b26199eaSJeeja KP struct list_head list; 182b26199eaSJeeja KP }; 183b26199eaSJeeja KP 1846c5768b3SDharageswari R struct skl_load_module_info { 1856c5768b3SDharageswari R u16 mod_id; 1866c5768b3SDharageswari R const struct firmware *fw; 1876c5768b3SDharageswari R }; 1886c5768b3SDharageswari R 1896c5768b3SDharageswari R struct skl_module_table { 1906c5768b3SDharageswari R struct skl_load_module_info *mod_info; 1916c5768b3SDharageswari R unsigned int usage_cnt; 1926c5768b3SDharageswari R struct list_head list; 1936c5768b3SDharageswari R }; 1946c5768b3SDharageswari R 1953e40a784SVinod Koul void skl_cldma_process_intr(struct sst_dsp *ctx); 1963e40a784SVinod Koul void skl_cldma_int_disable(struct sst_dsp *ctx); 1973e40a784SVinod Koul int skl_cldma_prepare(struct sst_dsp *ctx); 198b7d0254cSJeeja KP int skl_cldma_wait_interruptible(struct sst_dsp *ctx); 1993e40a784SVinod Koul 200e973e31aSSubhransu S. Prusty void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); 201e973e31aSSubhransu S. Prusty struct sst_dsp *skl_dsp_ctx_init(struct device *dev, 202e973e31aSSubhransu S. Prusty struct sst_dsp_device *sst_dev, int irq); 2038e9d8e19SSubhransu S. Prusty int skl_dsp_acquire_irq(struct sst_dsp *sst); 204e973e31aSSubhransu S. Prusty bool is_skl_dsp_running(struct sst_dsp *ctx); 205052f103cSJayachandran B 206052f103cSJayachandran B unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx); 207052f103cSJayachandran B void skl_dsp_init_core_state(struct sst_dsp *ctx); 208052f103cSJayachandran B int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); 209052f103cSJayachandran B int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); 210052f103cSJayachandran B int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask); 211052f103cSJayachandran B int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask); 212052f103cSJayachandran B int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx, 213052f103cSJayachandran B unsigned int core_mask); 214052f103cSJayachandran B int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask); 215052f103cSJayachandran B 216e973e31aSSubhransu S. Prusty irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); 217e973e31aSSubhransu S. Prusty int skl_dsp_wake(struct sst_dsp *ctx); 218e973e31aSSubhransu S. Prusty int skl_dsp_sleep(struct sst_dsp *ctx); 219e973e31aSSubhransu S. Prusty void skl_dsp_free(struct sst_dsp *dsp); 220e973e31aSSubhransu S. Prusty 221052f103cSJayachandran B int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id); 222052f103cSJayachandran B int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id); 223052f103cSJayachandran B 224e973e31aSSubhransu S. Prusty int skl_dsp_boot(struct sst_dsp *ctx); 225a750ba5fSSubhransu S. Prusty int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 226aecf6fd8SVinod Koul const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 227bcc2a2dcSCezary Rojewski struct skl_dev **dsp); 22892eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 22992eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 230bcc2a2dcSCezary Rojewski struct skl_dev **dsp); 231bcc2a2dcSCezary Rojewski int skl_sst_init_fw(struct device *dev, struct skl_dev *skl); 232bcc2a2dcSCezary Rojewski int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl); 233bcc2a2dcSCezary Rojewski void skl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); 234bcc2a2dcSCezary Rojewski void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); 235e973e31aSSubhransu S. Prusty 236a8e2c19eSSenthilnathan Veppur int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, 237a8e2c19eSSenthilnathan Veppur unsigned int offset, int index); 238bcc2a2dcSCezary Rojewski int skl_get_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int instance_id); 239bcc2a2dcSCezary Rojewski int skl_put_pvt_id(struct skl_dev *skl, guid_t *uuid_mod, int *pvt_id); 240bcc2a2dcSCezary Rojewski int skl_get_pvt_instance_id_map(struct skl_dev *skl, 24155a92ea9SDharageswari R int module_id, int instance_id); 242bcc2a2dcSCezary Rojewski void skl_freeup_uuid_list(struct skl_dev *skl); 243ea6b3e94SShreyas NC 2446eee8726SRamesh Babu int skl_dsp_strip_extended_manifest(struct firmware *fw); 2459452314dSPradeep Tewani 246bcc2a2dcSCezary Rojewski void skl_dsp_set_astate_cfg(struct skl_dev *skl, u32 cnt, void *data); 2479452314dSPradeep Tewani 2489fe9c711SG Kranthi int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name, 249bcc2a2dcSCezary Rojewski struct skl_dsp_loader_ops dsp_ops, struct skl_dev **dsp, 2509fe9c711SG Kranthi struct sst_dsp_device *skl_dev); 251bcc2a2dcSCezary Rojewski int skl_prepare_lib_load(struct skl_dev *skl, struct skl_lib_info *linfo, 252ebe89076SSubhransu S. Prusty struct firmware *stripped_fw, 253ebe89076SSubhransu S. Prusty unsigned int hdr_offset, int index); 254ebe89076SSubhransu S. Prusty void skl_release_library(struct skl_lib_info *linfo, int lib_count); 255cb729d80SG Kranthi 2563582f9aeSSubhransu S. Prusty #endif /*__SKL_SST_DSP_H__*/ 257