18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2bc2bd45bSSriram Periyasamy /* 3bc2bd45bSSriram Periyasamy * skl-ssp-clk.h - Skylake ssp clock information and ipc structure 4bc2bd45bSSriram Periyasamy * 5bc2bd45bSSriram Periyasamy * Copyright (C) 2017 Intel Corp 6bc2bd45bSSriram Periyasamy * Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com> 7bc2bd45bSSriram Periyasamy * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com> 8bc2bd45bSSriram Periyasamy * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9bc2bd45bSSriram Periyasamy * 10bc2bd45bSSriram Periyasamy * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11bc2bd45bSSriram Periyasamy */ 12bc2bd45bSSriram Periyasamy 13bc2bd45bSSriram Periyasamy #ifndef SOUND_SOC_SKL_SSP_CLK_H 14bc2bd45bSSriram Periyasamy #define SOUND_SOC_SKL_SSP_CLK_H 15bc2bd45bSSriram Periyasamy 16bc2bd45bSSriram Periyasamy #define SKL_MAX_SSP 6 17bc2bd45bSSriram Periyasamy /* xtal/cardinal/pll, parent of ssp clocks and mclk */ 18bc2bd45bSSriram Periyasamy #define SKL_MAX_CLK_SRC 3 19bc2bd45bSSriram Periyasamy #define SKL_MAX_SSP_CLK_TYPES 3 /* mclk, sclk, sclkfs */ 20bc2bd45bSSriram Periyasamy 21bc2bd45bSSriram Periyasamy #define SKL_MAX_CLK_CNT (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES) 22bc2bd45bSSriram Periyasamy 23bc2bd45bSSriram Periyasamy /* Max number of configurations supported for each clock */ 24bc2bd45bSSriram Periyasamy #define SKL_MAX_CLK_RATES 10 25bc2bd45bSSriram Periyasamy 26bc2bd45bSSriram Periyasamy #define SKL_SCLK_OFS SKL_MAX_SSP 27bc2bd45bSSriram Periyasamy #define SKL_SCLKFS_OFS (SKL_SCLK_OFS + SKL_MAX_SSP) 28bc2bd45bSSriram Periyasamy 29bc2bd45bSSriram Periyasamy enum skl_clk_type { 30bc2bd45bSSriram Periyasamy SKL_MCLK, 31bc2bd45bSSriram Periyasamy SKL_SCLK, 32bc2bd45bSSriram Periyasamy SKL_SCLK_FS, 33bc2bd45bSSriram Periyasamy }; 34bc2bd45bSSriram Periyasamy 35bc2bd45bSSriram Periyasamy enum skl_clk_src_type { 36bc2bd45bSSriram Periyasamy SKL_XTAL, 37bc2bd45bSSriram Periyasamy SKL_CARDINAL, 38bc2bd45bSSriram Periyasamy SKL_PLL, 39bc2bd45bSSriram Periyasamy }; 40bc2bd45bSSriram Periyasamy 41bc2bd45bSSriram Periyasamy struct skl_clk_parent_src { 42bc2bd45bSSriram Periyasamy u8 clk_id; 43bc2bd45bSSriram Periyasamy const char *name; 44bc2bd45bSSriram Periyasamy unsigned long rate; 45bc2bd45bSSriram Periyasamy const char *parent_name; 46bc2bd45bSSriram Periyasamy }; 47bc2bd45bSSriram Periyasamy 4801f50d69SSriram Periyasamy struct skl_tlv_hdr { 4901f50d69SSriram Periyasamy u32 type; 5001f50d69SSriram Periyasamy u32 size; 5101f50d69SSriram Periyasamy }; 5201f50d69SSriram Periyasamy 5301f50d69SSriram Periyasamy struct skl_dmactrl_mclk_cfg { 5401f50d69SSriram Periyasamy struct skl_tlv_hdr hdr; 5501f50d69SSriram Periyasamy /* DMA Clk TLV params */ 5601f50d69SSriram Periyasamy u32 clk_warm_up:16; 5701f50d69SSriram Periyasamy u32 mclk:1; 5801f50d69SSriram Periyasamy u32 warm_up_over:1; 5901f50d69SSriram Periyasamy u32 rsvd0:14; 6001f50d69SSriram Periyasamy u32 clk_stop_delay:16; 6101f50d69SSriram Periyasamy u32 keep_running:1; 6201f50d69SSriram Periyasamy u32 clk_stop_over:1; 6301f50d69SSriram Periyasamy u32 rsvd1:14; 6401f50d69SSriram Periyasamy }; 6501f50d69SSriram Periyasamy 6601f50d69SSriram Periyasamy struct skl_dmactrl_sclkfs_cfg { 6701f50d69SSriram Periyasamy struct skl_tlv_hdr hdr; 6801f50d69SSriram Periyasamy /* DMA SClk&FS TLV params */ 6901f50d69SSriram Periyasamy u32 sampling_frequency; 7001f50d69SSriram Periyasamy u32 bit_depth; 7101f50d69SSriram Periyasamy u32 channel_map; 7201f50d69SSriram Periyasamy u32 channel_config; 7301f50d69SSriram Periyasamy u32 interleaving_style; 7401f50d69SSriram Periyasamy u32 number_of_channels : 8; 7501f50d69SSriram Periyasamy u32 valid_bit_depth : 8; 7601f50d69SSriram Periyasamy u32 sample_type : 8; 7701f50d69SSriram Periyasamy u32 reserved : 8; 7801f50d69SSriram Periyasamy }; 7901f50d69SSriram Periyasamy 8001f50d69SSriram Periyasamy union skl_clk_ctrl_ipc { 8101f50d69SSriram Periyasamy struct skl_dmactrl_mclk_cfg mclk; 8201f50d69SSriram Periyasamy struct skl_dmactrl_sclkfs_cfg sclk_fs; 8301f50d69SSriram Periyasamy }; 8401f50d69SSriram Periyasamy 85bc2bd45bSSriram Periyasamy struct skl_clk_rate_cfg_table { 86bc2bd45bSSriram Periyasamy unsigned long rate; 8701f50d69SSriram Periyasamy union skl_clk_ctrl_ipc dma_ctl_ipc; 88bc2bd45bSSriram Periyasamy void *config; 89bc2bd45bSSriram Periyasamy }; 90bc2bd45bSSriram Periyasamy 91bc2bd45bSSriram Periyasamy /* 92bc2bd45bSSriram Periyasamy * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store 93bc2bd45bSSriram Periyasamy * all possible clocks ssp can generate for that platform. 94bc2bd45bSSriram Periyasamy */ 95bc2bd45bSSriram Periyasamy struct skl_ssp_clk { 96bc2bd45bSSriram Periyasamy const char *name; 97bc2bd45bSSriram Periyasamy const char *parent_name; 98bc2bd45bSSriram Periyasamy struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES]; 99bc2bd45bSSriram Periyasamy }; 100bc2bd45bSSriram Periyasamy 101bc2bd45bSSriram Periyasamy struct skl_clk_pdata { 102bc2bd45bSSriram Periyasamy struct skl_clk_parent_src *parent_clks; 103bc2bd45bSSriram Periyasamy int num_clks; 104bc2bd45bSSriram Periyasamy struct skl_ssp_clk *ssp_clks; 105bc2bd45bSSriram Periyasamy void *pvt_data; 106bc2bd45bSSriram Periyasamy }; 107bc2bd45bSSriram Periyasamy 108bc2bd45bSSriram Periyasamy #endif /* SOUND_SOC_SKL_SSP_CLK_H */ 109