1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Cannonlake SST DSP Support
4  *
5  * Copyright (C) 2016-17, Intel Corporation.
6  */
7 
8 #ifndef __CNL_SST_DSP_H__
9 #define __CNL_SST_DSP_H__
10 
11 struct sst_dsp;
12 struct skl_sst;
13 struct sst_dsp_device;
14 struct sst_generic_ipc;
15 
16 /* Intel HD Audio General DSP Registers */
17 #define CNL_ADSP_GEN_BASE		0x0
18 #define CNL_ADSP_REG_ADSPCS		(CNL_ADSP_GEN_BASE + 0x04)
19 #define CNL_ADSP_REG_ADSPIC		(CNL_ADSP_GEN_BASE + 0x08)
20 #define CNL_ADSP_REG_ADSPIS		(CNL_ADSP_GEN_BASE + 0x0c)
21 
22 /* Intel HD Audio Inter-Processor Communication Registers */
23 #define CNL_ADSP_IPC_BASE               0xc0
24 #define CNL_ADSP_REG_HIPCTDR            (CNL_ADSP_IPC_BASE + 0x00)
25 #define CNL_ADSP_REG_HIPCTDA            (CNL_ADSP_IPC_BASE + 0x04)
26 #define CNL_ADSP_REG_HIPCTDD            (CNL_ADSP_IPC_BASE + 0x08)
27 #define CNL_ADSP_REG_HIPCIDR            (CNL_ADSP_IPC_BASE + 0x10)
28 #define CNL_ADSP_REG_HIPCIDA            (CNL_ADSP_IPC_BASE + 0x14)
29 #define CNL_ADSP_REG_HIPCIDD            (CNL_ADSP_IPC_BASE + 0x18)
30 #define CNL_ADSP_REG_HIPCCTL            (CNL_ADSP_IPC_BASE + 0x28)
31 
32 /* HIPCTDR */
33 #define CNL_ADSP_REG_HIPCTDR_BUSY	BIT(31)
34 
35 /* HIPCTDA */
36 #define CNL_ADSP_REG_HIPCTDA_DONE	BIT(31)
37 
38 /* HIPCIDR */
39 #define CNL_ADSP_REG_HIPCIDR_BUSY	BIT(31)
40 
41 /* HIPCIDA */
42 #define CNL_ADSP_REG_HIPCIDA_DONE	BIT(31)
43 
44 /* CNL HIPCCTL */
45 #define CNL_ADSP_REG_HIPCCTL_DONE	BIT(1)
46 #define CNL_ADSP_REG_HIPCCTL_BUSY	BIT(0)
47 
48 /* CNL HIPCT */
49 #define CNL_ADSP_REG_HIPCT_BUSY		BIT(31)
50 
51 /* Intel HD Audio SRAM Window 1 */
52 #define CNL_ADSP_SRAM1_BASE		0xa0000
53 
54 #define CNL_ADSP_MMIO_LEN		0x10000
55 
56 #define CNL_ADSP_W0_STAT_SZ		0x1000
57 
58 #define CNL_ADSP_W0_UP_SZ		0x1000
59 
60 #define CNL_ADSP_W1_SZ			0x1000
61 
62 #define CNL_FW_STS_MASK			0xf
63 
64 #define CNL_ADSPIC_IPC			0x1
65 #define CNL_ADSPIS_IPC			0x1
66 
67 #define CNL_DSP_CORES		4
68 #define CNL_DSP_CORES_MASK	((1 << CNL_DSP_CORES) - 1)
69 
70 /* core reset - asserted high */
71 #define CNL_ADSPCS_CRST_SHIFT	0
72 #define CNL_ADSPCS_CRST(x)	(x << CNL_ADSPCS_CRST_SHIFT)
73 
74 /* core run/stall - when set to 1 core is stalled */
75 #define CNL_ADSPCS_CSTALL_SHIFT	8
76 #define CNL_ADSPCS_CSTALL(x)	(x << CNL_ADSPCS_CSTALL_SHIFT)
77 
78 /* set power active - when set to 1 turn core on */
79 #define CNL_ADSPCS_SPA_SHIFT	16
80 #define CNL_ADSPCS_SPA(x)	(x << CNL_ADSPCS_SPA_SHIFT)
81 
82 /* current power active - power status of cores, set by hardware */
83 #define CNL_ADSPCS_CPA_SHIFT	24
84 #define CNL_ADSPCS_CPA(x)	(x << CNL_ADSPCS_CPA_SHIFT)
85 
86 int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core);
87 int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core);
88 irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id);
89 void cnl_dsp_free(struct sst_dsp *dsp);
90 
91 void cnl_ipc_int_enable(struct sst_dsp *ctx);
92 void cnl_ipc_int_disable(struct sst_dsp *ctx);
93 void cnl_ipc_op_int_enable(struct sst_dsp *ctx);
94 void cnl_ipc_op_int_disable(struct sst_dsp *ctx);
95 bool cnl_ipc_int_status(struct sst_dsp *ctx);
96 void cnl_ipc_free(struct sst_generic_ipc *ipc);
97 
98 int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
99 		     const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
100 		     struct skl_sst **dsp);
101 int cnl_sst_init_fw(struct device *dev, struct skl_sst *ctx);
102 void cnl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
103 
104 #endif /*__CNL_SST_DSP_H__*/
105