147d7195dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2a838dcc2SGuneshwor Singh /* 3a838dcc2SGuneshwor Singh * Cannonlake SST DSP Support 4a838dcc2SGuneshwor Singh * 5a838dcc2SGuneshwor Singh * Copyright (C) 2016-17, Intel Corporation. 6a838dcc2SGuneshwor Singh */ 7a838dcc2SGuneshwor Singh 8a838dcc2SGuneshwor Singh #ifndef __CNL_SST_DSP_H__ 9a838dcc2SGuneshwor Singh #define __CNL_SST_DSP_H__ 10a838dcc2SGuneshwor Singh 11a838dcc2SGuneshwor Singh struct sst_dsp; 12a838dcc2SGuneshwor Singh struct sst_dsp_device; 13a838dcc2SGuneshwor Singh struct sst_generic_ipc; 14a838dcc2SGuneshwor Singh 15a838dcc2SGuneshwor Singh /* Intel HD Audio General DSP Registers */ 16a838dcc2SGuneshwor Singh #define CNL_ADSP_GEN_BASE 0x0 17a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_ADSPCS (CNL_ADSP_GEN_BASE + 0x04) 18a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_ADSPIC (CNL_ADSP_GEN_BASE + 0x08) 19a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_ADSPIS (CNL_ADSP_GEN_BASE + 0x0c) 20a838dcc2SGuneshwor Singh 21a838dcc2SGuneshwor Singh /* Intel HD Audio Inter-Processor Communication Registers */ 22a838dcc2SGuneshwor Singh #define CNL_ADSP_IPC_BASE 0xc0 23a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00) 24a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04) 25a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08) 26a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10) 27a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14) 28a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18) 29a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28) 30a838dcc2SGuneshwor Singh 31a838dcc2SGuneshwor Singh /* HIPCTDR */ 32a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCTDR_BUSY BIT(31) 33a838dcc2SGuneshwor Singh 34a838dcc2SGuneshwor Singh /* HIPCTDA */ 35a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCTDA_DONE BIT(31) 36a838dcc2SGuneshwor Singh 37a838dcc2SGuneshwor Singh /* HIPCIDR */ 38a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCIDR_BUSY BIT(31) 39a838dcc2SGuneshwor Singh 40a838dcc2SGuneshwor Singh /* HIPCIDA */ 41a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCIDA_DONE BIT(31) 42a838dcc2SGuneshwor Singh 43a838dcc2SGuneshwor Singh /* CNL HIPCCTL */ 44a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCCTL_DONE BIT(1) 45a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCCTL_BUSY BIT(0) 46a838dcc2SGuneshwor Singh 47a838dcc2SGuneshwor Singh /* CNL HIPCT */ 48a838dcc2SGuneshwor Singh #define CNL_ADSP_REG_HIPCT_BUSY BIT(31) 49a838dcc2SGuneshwor Singh 50a838dcc2SGuneshwor Singh /* Intel HD Audio SRAM Window 1 */ 51a838dcc2SGuneshwor Singh #define CNL_ADSP_SRAM1_BASE 0xa0000 52a838dcc2SGuneshwor Singh 53a838dcc2SGuneshwor Singh #define CNL_ADSP_MMIO_LEN 0x10000 54a838dcc2SGuneshwor Singh 55a838dcc2SGuneshwor Singh #define CNL_ADSP_W0_STAT_SZ 0x1000 56a838dcc2SGuneshwor Singh 57a838dcc2SGuneshwor Singh #define CNL_ADSP_W0_UP_SZ 0x1000 58a838dcc2SGuneshwor Singh 59a838dcc2SGuneshwor Singh #define CNL_ADSP_W1_SZ 0x1000 60a838dcc2SGuneshwor Singh 61a838dcc2SGuneshwor Singh #define CNL_FW_STS_MASK 0xf 62a838dcc2SGuneshwor Singh 63a838dcc2SGuneshwor Singh #define CNL_ADSPIC_IPC 0x1 64a838dcc2SGuneshwor Singh #define CNL_ADSPIS_IPC 0x1 65a838dcc2SGuneshwor Singh 66a838dcc2SGuneshwor Singh #define CNL_DSP_CORES 4 67a838dcc2SGuneshwor Singh #define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1) 68a838dcc2SGuneshwor Singh 69a838dcc2SGuneshwor Singh /* core reset - asserted high */ 70a838dcc2SGuneshwor Singh #define CNL_ADSPCS_CRST_SHIFT 0 71a838dcc2SGuneshwor Singh #define CNL_ADSPCS_CRST(x) (x << CNL_ADSPCS_CRST_SHIFT) 72a838dcc2SGuneshwor Singh 73a838dcc2SGuneshwor Singh /* core run/stall - when set to 1 core is stalled */ 74a838dcc2SGuneshwor Singh #define CNL_ADSPCS_CSTALL_SHIFT 8 75a838dcc2SGuneshwor Singh #define CNL_ADSPCS_CSTALL(x) (x << CNL_ADSPCS_CSTALL_SHIFT) 76a838dcc2SGuneshwor Singh 77a838dcc2SGuneshwor Singh /* set power active - when set to 1 turn core on */ 78a838dcc2SGuneshwor Singh #define CNL_ADSPCS_SPA_SHIFT 16 79a838dcc2SGuneshwor Singh #define CNL_ADSPCS_SPA(x) (x << CNL_ADSPCS_SPA_SHIFT) 80a838dcc2SGuneshwor Singh 81a838dcc2SGuneshwor Singh /* current power active - power status of cores, set by hardware */ 82a838dcc2SGuneshwor Singh #define CNL_ADSPCS_CPA_SHIFT 24 83a838dcc2SGuneshwor Singh #define CNL_ADSPCS_CPA(x) (x << CNL_ADSPCS_CPA_SHIFT) 84a838dcc2SGuneshwor Singh 858f0ccd59SPierre-Louis Bossart int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); 868f0ccd59SPierre-Louis Bossart int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); 87a838dcc2SGuneshwor Singh irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id); 88a838dcc2SGuneshwor Singh void cnl_dsp_free(struct sst_dsp *dsp); 89a838dcc2SGuneshwor Singh 90a838dcc2SGuneshwor Singh void cnl_ipc_int_enable(struct sst_dsp *ctx); 91a838dcc2SGuneshwor Singh void cnl_ipc_int_disable(struct sst_dsp *ctx); 92a838dcc2SGuneshwor Singh void cnl_ipc_op_int_enable(struct sst_dsp *ctx); 93a838dcc2SGuneshwor Singh void cnl_ipc_op_int_disable(struct sst_dsp *ctx); 94a838dcc2SGuneshwor Singh bool cnl_ipc_int_status(struct sst_dsp *ctx); 95a838dcc2SGuneshwor Singh void cnl_ipc_free(struct sst_generic_ipc *ipc); 96a838dcc2SGuneshwor Singh 97cb6a5528SGuneshwor Singh int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 98cb6a5528SGuneshwor Singh const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 99bcc2a2dcSCezary Rojewski struct skl_dev **dsp); 100bcc2a2dcSCezary Rojewski int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl); 101bcc2a2dcSCezary Rojewski void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); 102cb6a5528SGuneshwor Singh 103a838dcc2SGuneshwor Singh #endif /*__CNL_SST_DSP_H__*/ 104