1 /* 2 * bxt-sst.c - DSP library functions for BXT platform 3 * 4 * Copyright (C) 2015-16 Intel Corp 5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 6 * Jeeja KP <jeeja.kp@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/delay.h> 20 #include <linux/firmware.h> 21 #include <linux/device.h> 22 23 #include "../common/sst-dsp.h" 24 #include "../common/sst-dsp-priv.h" 25 #include "skl-sst-ipc.h" 26 #include "skl-tplg-interface.h" 27 28 #define BXT_BASEFW_TIMEOUT 3000 29 #define BXT_INIT_TIMEOUT 500 30 #define BXT_IPC_PURGE_FW 0x01004000 31 32 #define BXT_ROM_INIT 0x5 33 #define BXT_ADSP_SRAM0_BASE 0x80000 34 35 /* Firmware status window */ 36 #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 37 #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 38 39 #define BXT_ADSP_SRAM1_BASE 0xA0000 40 41 #define BXT_INSTANCE_ID 0 42 #define BXT_BASE_FW_MODULE_ID 0 43 44 #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 45 46 /* Delay before scheduling D0i3 entry */ 47 #define BXT_D0I3_DELAY 5000 48 49 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 50 { 51 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 52 } 53 54 static int 55 bxt_load_library(struct sst_dsp *ctx, struct skl_dfw_manifest *minfo) 56 { 57 struct snd_dma_buffer dmab; 58 struct skl_sst *skl = ctx->thread_context; 59 const struct firmware *fw = NULL; 60 struct firmware stripped_fw; 61 int ret = 0, i, dma_id, stream_tag; 62 63 /* library indices start from 1 to N. 0 represents base FW */ 64 for (i = 1; i < minfo->lib_count; i++) { 65 ret = request_firmware(&fw, minfo->lib[i].name, ctx->dev); 66 if (ret < 0) { 67 dev_err(ctx->dev, "Request lib %s failed:%d\n", 68 minfo->lib[i].name, ret); 69 return ret; 70 } 71 72 if (skl->is_first_boot) { 73 ret = snd_skl_parse_uuids(ctx, fw, 74 BXT_ADSP_FW_BIN_HDR_OFFSET, i); 75 if (ret < 0) 76 goto load_library_failed; 77 } 78 79 stripped_fw.data = fw->data; 80 stripped_fw.size = fw->size; 81 skl_dsp_strip_extended_manifest(&stripped_fw); 82 83 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 84 stripped_fw.size, &dmab); 85 if (stream_tag <= 0) { 86 dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 87 stream_tag); 88 ret = stream_tag; 89 goto load_library_failed; 90 } 91 92 dma_id = stream_tag - 1; 93 memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 94 95 ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 96 ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 97 if (ret < 0) 98 dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 99 minfo->lib[i].name, ret); 100 101 ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 102 ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 103 release_firmware(fw); 104 fw = NULL; 105 } 106 107 return ret; 108 109 load_library_failed: 110 release_firmware(fw); 111 return ret; 112 } 113 114 /* 115 * First boot sequence has some extra steps. Core 0 waits for power 116 * status on core 1, so power up core 1 also momentarily, keep it in 117 * reset/stall and then turn it off 118 */ 119 static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 120 const void *fwdata, u32 fwsize) 121 { 122 int stream_tag, ret, i; 123 u32 reg; 124 125 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 126 if (stream_tag <= 0) { 127 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 128 stream_tag); 129 return stream_tag; 130 } 131 132 ctx->dsp_ops.stream_tag = stream_tag; 133 memcpy(ctx->dmab.area, fwdata, fwsize); 134 135 /* Step 1: Power up core 0 and core1 */ 136 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 137 SKL_DSP_CORE_MASK(1)); 138 if (ret < 0) { 139 dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 140 goto base_fw_load_failed; 141 } 142 143 /* Step 2: Purge FW request */ 144 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 145 (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 146 147 /* Step 3: Unset core0 reset state & unstall/run core0 */ 148 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 149 if (ret < 0) { 150 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 151 ret = -EIO; 152 goto base_fw_load_failed; 153 } 154 155 /* Step 4: Wait for DONE Bit */ 156 for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 157 reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE); 158 159 if (reg & SKL_ADSP_REG_HIPCIE_DONE) { 160 sst_dsp_shim_update_bits_forced(ctx, 161 SKL_ADSP_REG_HIPCIE, 162 SKL_ADSP_REG_HIPCIE_DONE, 163 SKL_ADSP_REG_HIPCIE_DONE); 164 break; 165 } 166 mdelay(1); 167 } 168 if (!i) { 169 dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg); 170 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE, 171 SKL_ADSP_REG_HIPCIE_DONE, 172 SKL_ADSP_REG_HIPCIE_DONE); 173 } 174 175 /* Step 5: power down core1 */ 176 ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 177 if (ret < 0) { 178 dev_err(ctx->dev, "dsp core1 power down failed\n"); 179 goto base_fw_load_failed; 180 } 181 182 /* Step 6: Enable Interrupt */ 183 skl_ipc_int_enable(ctx); 184 skl_ipc_op_int_enable(ctx); 185 186 /* Step 7: Wait for ROM init */ 187 for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 188 if (SKL_FW_INIT == 189 (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) & 190 SKL_FW_STS_MASK)) { 191 192 dev_info(ctx->dev, "ROM loaded, continue FW loading\n"); 193 break; 194 } 195 mdelay(1); 196 } 197 if (!i) { 198 dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg); 199 ret = -EIO; 200 goto base_fw_load_failed; 201 } 202 203 return ret; 204 205 base_fw_load_failed: 206 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 207 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 208 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 209 return ret; 210 } 211 212 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 213 { 214 int ret; 215 216 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 217 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 218 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 219 220 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 221 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 222 223 return ret; 224 } 225 226 static int bxt_load_base_firmware(struct sst_dsp *ctx) 227 { 228 struct firmware stripped_fw; 229 struct skl_sst *skl = ctx->thread_context; 230 int ret; 231 232 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 233 if (ret < 0) { 234 dev_err(ctx->dev, "Request firmware failed %d\n", ret); 235 goto sst_load_base_firmware_failed; 236 } 237 238 /* check for extended manifest */ 239 if (ctx->fw == NULL) 240 goto sst_load_base_firmware_failed; 241 242 /* prase uuids on first boot */ 243 if (skl->is_first_boot) { 244 ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 245 if (ret < 0) 246 goto sst_load_base_firmware_failed; 247 } 248 249 stripped_fw.data = ctx->fw->data; 250 stripped_fw.size = ctx->fw->size; 251 skl_dsp_strip_extended_manifest(&stripped_fw); 252 253 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 254 /* Retry Enabling core and ROM load. Retry seemed to help */ 255 if (ret < 0) { 256 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 257 if (ret < 0) { 258 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 259 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 260 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 261 262 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 263 goto sst_load_base_firmware_failed; 264 } 265 } 266 267 ret = sst_transfer_fw_host_dma(ctx); 268 if (ret < 0) { 269 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 270 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 271 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 272 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 273 274 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 275 } else { 276 dev_dbg(ctx->dev, "Firmware download successful\n"); 277 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 278 msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 279 if (ret == 0) { 280 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 281 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 282 ret = -EIO; 283 } else { 284 ret = 0; 285 skl->fw_loaded = true; 286 } 287 } 288 289 sst_load_base_firmware_failed: 290 release_firmware(ctx->fw); 291 return ret; 292 } 293 294 /* 295 * Decide the D0i3 state that can be targeted based on the usecase 296 * ref counts and DSP state 297 * 298 * Decision Matrix: (X= dont care; state = target state) 299 * 300 * DSP state != SKL_DSP_RUNNING ; state = no d0i3 301 * 302 * DSP state == SKL_DSP_RUNNING , the following matrix applies 303 * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 304 * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 305 * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 306 * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 307 */ 308 static int bxt_d0i3_target_state(struct sst_dsp *ctx) 309 { 310 struct skl_sst *skl = ctx->thread_context; 311 struct skl_d0i3_data *d0i3 = &skl->d0i3; 312 313 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 314 return SKL_DSP_D0I3_NONE; 315 316 if (d0i3->non_d0i3) 317 return SKL_DSP_D0I3_NONE; 318 else if (d0i3->streaming) 319 return SKL_DSP_D0I3_STREAMING; 320 else if (d0i3->non_streaming) 321 return SKL_DSP_D0I3_NON_STREAMING; 322 else 323 return SKL_DSP_D0I3_NONE; 324 } 325 326 static void bxt_set_dsp_D0i3(struct work_struct *work) 327 { 328 int ret; 329 struct skl_ipc_d0ix_msg msg; 330 struct skl_sst *skl = container_of(work, 331 struct skl_sst, d0i3.work.work); 332 struct sst_dsp *ctx = skl->dsp; 333 struct skl_d0i3_data *d0i3 = &skl->d0i3; 334 int target_state; 335 336 dev_dbg(ctx->dev, "In %s:\n", __func__); 337 338 /* D0i3 entry allowed only if core 0 alone is running */ 339 if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 340 dev_warn(ctx->dev, 341 "D0i3 allowed when only core0 running:Exit\n"); 342 return; 343 } 344 345 target_state = bxt_d0i3_target_state(ctx); 346 if (target_state == SKL_DSP_D0I3_NONE) 347 return; 348 349 msg.instance_id = 0; 350 msg.module_id = 0; 351 msg.wake = 1; 352 msg.streaming = 0; 353 if (target_state == SKL_DSP_D0I3_STREAMING) 354 msg.streaming = 1; 355 356 ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 357 358 if (ret < 0) { 359 dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 360 return; 361 } 362 363 /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 364 if (skl->update_d0i3c) 365 skl->update_d0i3c(skl->dev, true); 366 367 d0i3->state = target_state; 368 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 369 } 370 371 static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 372 { 373 struct skl_sst *skl = ctx->thread_context; 374 struct skl_d0i3_data *d0i3 = &skl->d0i3; 375 376 /* Schedule D0i3 only if the usecase ref counts are appropriate */ 377 if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 378 379 dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 380 381 schedule_delayed_work(&d0i3->work, 382 msecs_to_jiffies(BXT_D0I3_DELAY)); 383 } 384 385 return 0; 386 } 387 388 static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 389 { 390 int ret; 391 struct skl_ipc_d0ix_msg msg; 392 struct skl_sst *skl = ctx->thread_context; 393 394 dev_dbg(ctx->dev, "In %s:\n", __func__); 395 396 /* First Cancel any pending attempt to put DSP to D0i3 */ 397 cancel_delayed_work_sync(&skl->d0i3.work); 398 399 /* If DSP is currently in D0i3, bring it to D0i0 */ 400 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 401 return 0; 402 403 dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 404 405 msg.instance_id = 0; 406 msg.module_id = 0; 407 msg.streaming = 0; 408 msg.wake = 0; 409 410 if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 411 msg.streaming = 1; 412 413 /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 414 if (skl->update_d0i3c) 415 skl->update_d0i3c(skl->dev, false); 416 417 ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 418 if (ret < 0) { 419 dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 420 return ret; 421 } 422 423 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 424 skl->d0i3.state = SKL_DSP_D0I3_NONE; 425 426 return 0; 427 } 428 429 static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 430 { 431 struct skl_sst *skl = ctx->thread_context; 432 int ret; 433 struct skl_ipc_dxstate_info dx; 434 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 435 struct skl_dfw_manifest *minfo = &skl->manifest; 436 437 if (skl->fw_loaded == false) { 438 skl->boot_complete = false; 439 ret = bxt_load_base_firmware(ctx); 440 if (ret < 0) { 441 dev_err(ctx->dev, "reload fw failed: %d\n", ret); 442 return ret; 443 } 444 445 if (minfo->lib_count > 1) { 446 ret = bxt_load_library(ctx, minfo); 447 if (ret < 0) { 448 dev_err(ctx->dev, "reload libs failed: %d\n", ret); 449 return ret; 450 } 451 } 452 return ret; 453 } 454 455 /* If core 0 is being turned on, turn on core 1 as well */ 456 if (core_id == SKL_DSP_CORE0_ID) 457 ret = skl_dsp_core_power_up(ctx, core_mask | 458 SKL_DSP_CORE_MASK(1)); 459 else 460 ret = skl_dsp_core_power_up(ctx, core_mask); 461 462 if (ret < 0) 463 goto err; 464 465 if (core_id == SKL_DSP_CORE0_ID) { 466 467 /* 468 * Enable interrupt after SPA is set and before 469 * DSP is unstalled 470 */ 471 skl_ipc_int_enable(ctx); 472 skl_ipc_op_int_enable(ctx); 473 skl->boot_complete = false; 474 } 475 476 ret = skl_dsp_start_core(ctx, core_mask); 477 if (ret < 0) 478 goto err; 479 480 if (core_id == SKL_DSP_CORE0_ID) { 481 ret = wait_event_timeout(skl->boot_wait, 482 skl->boot_complete, 483 msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 484 485 /* If core 1 was turned on for booting core 0, turn it off */ 486 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 487 if (ret == 0) { 488 dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 489 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 490 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 491 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 492 dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 493 ret = -EIO; 494 goto err; 495 } 496 } 497 498 /* Tell FW if additional core in now On */ 499 500 if (core_id != SKL_DSP_CORE0_ID) { 501 dx.core_mask = core_mask; 502 dx.dx_mask = core_mask; 503 504 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 505 BXT_BASE_FW_MODULE_ID, &dx); 506 if (ret < 0) { 507 dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 508 core_id, ret); 509 goto err; 510 } 511 } 512 513 skl->cores.state[core_id] = SKL_DSP_RUNNING; 514 return 0; 515 err: 516 if (core_id == SKL_DSP_CORE0_ID) 517 core_mask |= SKL_DSP_CORE_MASK(1); 518 skl_dsp_disable_core(ctx, core_mask); 519 520 return ret; 521 } 522 523 static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 524 { 525 int ret; 526 struct skl_ipc_dxstate_info dx; 527 struct skl_sst *skl = ctx->thread_context; 528 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 529 530 dx.core_mask = core_mask; 531 dx.dx_mask = SKL_IPC_D3_MASK; 532 533 dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 534 dx.core_mask, dx.dx_mask); 535 536 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 537 BXT_BASE_FW_MODULE_ID, &dx); 538 if (ret < 0) 539 dev_err(ctx->dev, 540 "Failed to set DSP to D3:core id = %d;Continue reset\n", 541 core_id); 542 543 ret = skl_dsp_disable_core(ctx, core_mask); 544 if (ret < 0) { 545 dev_err(ctx->dev, "Failed to disable core %d\n", ret); 546 return ret; 547 } 548 skl->cores.state[core_id] = SKL_DSP_RESET; 549 return 0; 550 } 551 552 static struct skl_dsp_fw_ops bxt_fw_ops = { 553 .set_state_D0 = bxt_set_dsp_D0, 554 .set_state_D3 = bxt_set_dsp_D3, 555 .set_state_D0i3 = bxt_schedule_dsp_D0i3, 556 .set_state_D0i0 = bxt_set_dsp_D0i0, 557 .load_fw = bxt_load_base_firmware, 558 .get_fw_errcode = bxt_get_errorcode, 559 .load_library = bxt_load_library, 560 }; 561 562 static struct sst_ops skl_ops = { 563 .irq_handler = skl_dsp_sst_interrupt, 564 .write = sst_shim32_write, 565 .read = sst_shim32_read, 566 .ram_read = sst_memcpy_fromio_32, 567 .ram_write = sst_memcpy_toio_32, 568 .free = skl_dsp_free, 569 }; 570 571 static struct sst_dsp_device skl_dev = { 572 .thread = skl_dsp_irq_thread_handler, 573 .ops = &skl_ops, 574 }; 575 576 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 577 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 578 struct skl_sst **dsp) 579 { 580 struct skl_sst *skl; 581 struct sst_dsp *sst; 582 int ret; 583 584 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 585 if (skl == NULL) 586 return -ENOMEM; 587 588 skl->dev = dev; 589 skl_dev.thread_context = skl; 590 INIT_LIST_HEAD(&skl->uuid_list); 591 592 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 593 if (!skl->dsp) { 594 dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 595 return -ENODEV; 596 } 597 598 sst = skl->dsp; 599 sst->fw_name = fw_name; 600 sst->dsp_ops = dsp_ops; 601 sst->fw_ops = bxt_fw_ops; 602 sst->addr.lpe = mmio_base; 603 sst->addr.shim = mmio_base; 604 605 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 606 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 607 608 INIT_LIST_HEAD(&sst->module_list); 609 ret = skl_ipc_init(dev, skl); 610 if (ret) 611 return ret; 612 613 /* set the D0i3 check */ 614 skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 615 616 skl->cores.count = 2; 617 skl->boot_complete = false; 618 init_waitqueue_head(&skl->boot_wait); 619 skl->is_first_boot = true; 620 INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 621 skl->d0i3.state = SKL_DSP_D0I3_NONE; 622 623 if (dsp) 624 *dsp = skl; 625 626 return 0; 627 } 628 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 629 630 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 631 { 632 int ret; 633 struct sst_dsp *sst = ctx->dsp; 634 635 ret = sst->fw_ops.load_fw(sst); 636 if (ret < 0) { 637 dev_err(dev, "Load base fw failed: %x\n", ret); 638 return ret; 639 } 640 641 skl_dsp_init_core_state(sst); 642 643 if (ctx->manifest.lib_count > 1) { 644 ret = sst->fw_ops.load_library(sst, &ctx->manifest); 645 if (ret < 0) { 646 dev_err(dev, "Load Library failed : %x\n", ret); 647 return ret; 648 } 649 } 650 ctx->is_first_boot = false; 651 652 return 0; 653 } 654 EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 655 656 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 657 { 658 skl_freeup_uuid_list(ctx); 659 skl_ipc_free(&ctx->ipc); 660 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 661 662 if (ctx->dsp->addr.lpe) 663 iounmap(ctx->dsp->addr.lpe); 664 665 ctx->dsp->ops->free(ctx->dsp); 666 } 667 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 668 669 MODULE_LICENSE("GPL v2"); 670 MODULE_DESCRIPTION("Intel Broxton IPC driver"); 671