1 /* 2 * bxt-sst.c - DSP library functions for BXT platform 3 * 4 * Copyright (C) 2015-16 Intel Corp 5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 6 * Jeeja KP <jeeja.kp@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/delay.h> 20 #include <linux/firmware.h> 21 #include <linux/device.h> 22 23 #include "../common/sst-dsp.h" 24 #include "../common/sst-dsp-priv.h" 25 #include "skl-sst-ipc.h" 26 27 #define BXT_BASEFW_TIMEOUT 3000 28 #define BXT_INIT_TIMEOUT 300 29 #define BXT_ROM_INIT_TIMEOUT 70 30 #define BXT_IPC_PURGE_FW 0x01004000 31 32 #define BXT_ROM_INIT 0x5 33 #define BXT_ADSP_SRAM0_BASE 0x80000 34 35 /* Firmware status window */ 36 #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 37 #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 38 39 #define BXT_ADSP_SRAM1_BASE 0xA0000 40 41 #define BXT_INSTANCE_ID 0 42 #define BXT_BASE_FW_MODULE_ID 0 43 44 #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 45 46 /* Delay before scheduling D0i3 entry */ 47 #define BXT_D0I3_DELAY 5000 48 49 #define BXT_FW_ROM_INIT_RETRY 3 50 51 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 52 { 53 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 54 } 55 56 static void sst_bxt_release_library(struct skl_lib_info *linfo, int lib_count) 57 { 58 int i; 59 60 for (i = 1; i < lib_count; i++) { 61 if (linfo[i].fw) { 62 release_firmware(linfo[i].fw); 63 linfo[i].fw = NULL; 64 } 65 } 66 } 67 68 static int 69 bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count) 70 { 71 struct snd_dma_buffer dmab; 72 struct skl_sst *skl = ctx->thread_context; 73 struct firmware stripped_fw; 74 int ret = 0, i, dma_id, stream_tag; 75 76 /* library indices start from 1 to N. 0 represents base FW */ 77 for (i = 1; i < lib_count; i++) { 78 if (linfo[i].fw == NULL) { 79 ret = request_firmware(&linfo[i].fw, linfo[i].name, 80 ctx->dev); 81 if (ret < 0) { 82 dev_err(ctx->dev, "Request lib %s failed:%d\n", 83 linfo[i].name, ret); 84 goto load_library_failed; 85 } 86 } 87 88 if (skl->is_first_boot) { 89 ret = snd_skl_parse_uuids(ctx, linfo[i].fw, 90 BXT_ADSP_FW_BIN_HDR_OFFSET, i); 91 if (ret < 0) 92 goto load_library_failed; 93 } 94 95 stripped_fw.data = linfo[i].fw->data; 96 stripped_fw.size = linfo[i].fw->size; 97 skl_dsp_strip_extended_manifest(&stripped_fw); 98 99 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 100 stripped_fw.size, &dmab); 101 if (stream_tag <= 0) { 102 dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 103 stream_tag); 104 ret = stream_tag; 105 goto load_library_failed; 106 } 107 108 dma_id = stream_tag - 1; 109 memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 110 111 ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 112 ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 113 if (ret < 0) 114 dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 115 linfo[i].name, ret); 116 117 ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 118 ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 119 } 120 121 return ret; 122 123 load_library_failed: 124 sst_bxt_release_library(linfo, lib_count); 125 return ret; 126 } 127 128 /* 129 * First boot sequence has some extra steps. Core 0 waits for power 130 * status on core 1, so power up core 1 also momentarily, keep it in 131 * reset/stall and then turn it off 132 */ 133 static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 134 const void *fwdata, u32 fwsize) 135 { 136 int stream_tag, ret; 137 138 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 139 if (stream_tag <= 0) { 140 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 141 stream_tag); 142 return stream_tag; 143 } 144 145 ctx->dsp_ops.stream_tag = stream_tag; 146 memcpy(ctx->dmab.area, fwdata, fwsize); 147 148 /* Step 1: Power up core 0 and core1 */ 149 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 150 SKL_DSP_CORE_MASK(1)); 151 if (ret < 0) { 152 dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 153 goto base_fw_load_failed; 154 } 155 156 /* Step 2: Purge FW request */ 157 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 158 (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 159 160 /* Step 3: Unset core0 reset state & unstall/run core0 */ 161 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 162 if (ret < 0) { 163 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 164 ret = -EIO; 165 goto base_fw_load_failed; 166 } 167 168 /* Step 4: Wait for DONE Bit */ 169 ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE, 170 SKL_ADSP_REG_HIPCIE_DONE, 171 SKL_ADSP_REG_HIPCIE_DONE, 172 BXT_INIT_TIMEOUT, "HIPCIE Done"); 173 if (ret < 0) { 174 dev_err(ctx->dev, "Timout for Purge Request%d\n", ret); 175 goto base_fw_load_failed; 176 } 177 178 /* Step 5: power down core1 */ 179 ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 180 if (ret < 0) { 181 dev_err(ctx->dev, "dsp core1 power down failed\n"); 182 goto base_fw_load_failed; 183 } 184 185 /* Step 6: Enable Interrupt */ 186 skl_ipc_int_enable(ctx); 187 skl_ipc_op_int_enable(ctx); 188 189 /* Step 7: Wait for ROM init */ 190 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 191 SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load"); 192 if (ret < 0) { 193 dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret); 194 goto base_fw_load_failed; 195 } 196 197 return ret; 198 199 base_fw_load_failed: 200 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 201 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 202 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 203 return ret; 204 } 205 206 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 207 { 208 int ret; 209 210 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 211 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 212 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 213 214 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 215 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 216 217 return ret; 218 } 219 220 static int bxt_load_base_firmware(struct sst_dsp *ctx) 221 { 222 struct firmware stripped_fw; 223 struct skl_sst *skl = ctx->thread_context; 224 int ret, i; 225 226 if (ctx->fw == NULL) { 227 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 228 if (ret < 0) { 229 dev_err(ctx->dev, "Request firmware failed %d\n", ret); 230 return ret; 231 } 232 } 233 234 /* prase uuids on first boot */ 235 if (skl->is_first_boot) { 236 ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 237 if (ret < 0) 238 goto sst_load_base_firmware_failed; 239 } 240 241 stripped_fw.data = ctx->fw->data; 242 stripped_fw.size = ctx->fw->size; 243 skl_dsp_strip_extended_manifest(&stripped_fw); 244 245 246 for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) { 247 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 248 if (ret == 0) 249 break; 250 } 251 252 if (ret < 0) { 253 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 254 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 255 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 256 257 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 258 goto sst_load_base_firmware_failed; 259 } 260 261 ret = sst_transfer_fw_host_dma(ctx); 262 if (ret < 0) { 263 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 264 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 265 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 266 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 267 268 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 269 } else { 270 dev_dbg(ctx->dev, "Firmware download successful\n"); 271 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 272 msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 273 if (ret == 0) { 274 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 275 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 276 ret = -EIO; 277 } else { 278 ret = 0; 279 skl->fw_loaded = true; 280 } 281 } 282 283 return ret; 284 285 sst_load_base_firmware_failed: 286 release_firmware(ctx->fw); 287 ctx->fw = NULL; 288 return ret; 289 } 290 291 /* 292 * Decide the D0i3 state that can be targeted based on the usecase 293 * ref counts and DSP state 294 * 295 * Decision Matrix: (X= dont care; state = target state) 296 * 297 * DSP state != SKL_DSP_RUNNING ; state = no d0i3 298 * 299 * DSP state == SKL_DSP_RUNNING , the following matrix applies 300 * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 301 * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 302 * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 303 * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 304 */ 305 static int bxt_d0i3_target_state(struct sst_dsp *ctx) 306 { 307 struct skl_sst *skl = ctx->thread_context; 308 struct skl_d0i3_data *d0i3 = &skl->d0i3; 309 310 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 311 return SKL_DSP_D0I3_NONE; 312 313 if (d0i3->non_d0i3) 314 return SKL_DSP_D0I3_NONE; 315 else if (d0i3->streaming) 316 return SKL_DSP_D0I3_STREAMING; 317 else if (d0i3->non_streaming) 318 return SKL_DSP_D0I3_NON_STREAMING; 319 else 320 return SKL_DSP_D0I3_NONE; 321 } 322 323 static void bxt_set_dsp_D0i3(struct work_struct *work) 324 { 325 int ret; 326 struct skl_ipc_d0ix_msg msg; 327 struct skl_sst *skl = container_of(work, 328 struct skl_sst, d0i3.work.work); 329 struct sst_dsp *ctx = skl->dsp; 330 struct skl_d0i3_data *d0i3 = &skl->d0i3; 331 int target_state; 332 333 dev_dbg(ctx->dev, "In %s:\n", __func__); 334 335 /* D0i3 entry allowed only if core 0 alone is running */ 336 if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 337 dev_warn(ctx->dev, 338 "D0i3 allowed when only core0 running:Exit\n"); 339 return; 340 } 341 342 target_state = bxt_d0i3_target_state(ctx); 343 if (target_state == SKL_DSP_D0I3_NONE) 344 return; 345 346 msg.instance_id = 0; 347 msg.module_id = 0; 348 msg.wake = 1; 349 msg.streaming = 0; 350 if (target_state == SKL_DSP_D0I3_STREAMING) 351 msg.streaming = 1; 352 353 ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 354 355 if (ret < 0) { 356 dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 357 return; 358 } 359 360 /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 361 if (skl->update_d0i3c) 362 skl->update_d0i3c(skl->dev, true); 363 364 d0i3->state = target_state; 365 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 366 } 367 368 static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 369 { 370 struct skl_sst *skl = ctx->thread_context; 371 struct skl_d0i3_data *d0i3 = &skl->d0i3; 372 373 /* Schedule D0i3 only if the usecase ref counts are appropriate */ 374 if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 375 376 dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 377 378 schedule_delayed_work(&d0i3->work, 379 msecs_to_jiffies(BXT_D0I3_DELAY)); 380 } 381 382 return 0; 383 } 384 385 static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 386 { 387 int ret; 388 struct skl_ipc_d0ix_msg msg; 389 struct skl_sst *skl = ctx->thread_context; 390 391 dev_dbg(ctx->dev, "In %s:\n", __func__); 392 393 /* First Cancel any pending attempt to put DSP to D0i3 */ 394 cancel_delayed_work_sync(&skl->d0i3.work); 395 396 /* If DSP is currently in D0i3, bring it to D0i0 */ 397 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 398 return 0; 399 400 dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 401 402 msg.instance_id = 0; 403 msg.module_id = 0; 404 msg.streaming = 0; 405 msg.wake = 0; 406 407 if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 408 msg.streaming = 1; 409 410 /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 411 if (skl->update_d0i3c) 412 skl->update_d0i3c(skl->dev, false); 413 414 ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 415 if (ret < 0) { 416 dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 417 return ret; 418 } 419 420 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 421 skl->d0i3.state = SKL_DSP_D0I3_NONE; 422 423 return 0; 424 } 425 426 static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 427 { 428 struct skl_sst *skl = ctx->thread_context; 429 int ret; 430 struct skl_ipc_dxstate_info dx; 431 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 432 433 if (skl->fw_loaded == false) { 434 skl->boot_complete = false; 435 ret = bxt_load_base_firmware(ctx); 436 if (ret < 0) { 437 dev_err(ctx->dev, "reload fw failed: %d\n", ret); 438 return ret; 439 } 440 441 if (skl->lib_count > 1) { 442 ret = bxt_load_library(ctx, skl->lib_info, 443 skl->lib_count); 444 if (ret < 0) { 445 dev_err(ctx->dev, "reload libs failed: %d\n", ret); 446 return ret; 447 } 448 } 449 return ret; 450 } 451 452 /* If core 0 is being turned on, turn on core 1 as well */ 453 if (core_id == SKL_DSP_CORE0_ID) 454 ret = skl_dsp_core_power_up(ctx, core_mask | 455 SKL_DSP_CORE_MASK(1)); 456 else 457 ret = skl_dsp_core_power_up(ctx, core_mask); 458 459 if (ret < 0) 460 goto err; 461 462 if (core_id == SKL_DSP_CORE0_ID) { 463 464 /* 465 * Enable interrupt after SPA is set and before 466 * DSP is unstalled 467 */ 468 skl_ipc_int_enable(ctx); 469 skl_ipc_op_int_enable(ctx); 470 skl->boot_complete = false; 471 } 472 473 ret = skl_dsp_start_core(ctx, core_mask); 474 if (ret < 0) 475 goto err; 476 477 if (core_id == SKL_DSP_CORE0_ID) { 478 ret = wait_event_timeout(skl->boot_wait, 479 skl->boot_complete, 480 msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 481 482 /* If core 1 was turned on for booting core 0, turn it off */ 483 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 484 if (ret == 0) { 485 dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 486 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 487 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 488 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 489 dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 490 ret = -EIO; 491 goto err; 492 } 493 } 494 495 /* Tell FW if additional core in now On */ 496 497 if (core_id != SKL_DSP_CORE0_ID) { 498 dx.core_mask = core_mask; 499 dx.dx_mask = core_mask; 500 501 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 502 BXT_BASE_FW_MODULE_ID, &dx); 503 if (ret < 0) { 504 dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 505 core_id, ret); 506 goto err; 507 } 508 } 509 510 skl->cores.state[core_id] = SKL_DSP_RUNNING; 511 return 0; 512 err: 513 if (core_id == SKL_DSP_CORE0_ID) 514 core_mask |= SKL_DSP_CORE_MASK(1); 515 skl_dsp_disable_core(ctx, core_mask); 516 517 return ret; 518 } 519 520 static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 521 { 522 int ret; 523 struct skl_ipc_dxstate_info dx; 524 struct skl_sst *skl = ctx->thread_context; 525 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 526 527 dx.core_mask = core_mask; 528 dx.dx_mask = SKL_IPC_D3_MASK; 529 530 dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 531 dx.core_mask, dx.dx_mask); 532 533 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 534 BXT_BASE_FW_MODULE_ID, &dx); 535 if (ret < 0) 536 dev_err(ctx->dev, 537 "Failed to set DSP to D3:core id = %d;Continue reset\n", 538 core_id); 539 540 ret = skl_dsp_disable_core(ctx, core_mask); 541 if (ret < 0) { 542 dev_err(ctx->dev, "Failed to disable core %d\n", ret); 543 return ret; 544 } 545 skl->cores.state[core_id] = SKL_DSP_RESET; 546 return 0; 547 } 548 549 static struct skl_dsp_fw_ops bxt_fw_ops = { 550 .set_state_D0 = bxt_set_dsp_D0, 551 .set_state_D3 = bxt_set_dsp_D3, 552 .set_state_D0i3 = bxt_schedule_dsp_D0i3, 553 .set_state_D0i0 = bxt_set_dsp_D0i0, 554 .load_fw = bxt_load_base_firmware, 555 .get_fw_errcode = bxt_get_errorcode, 556 .load_library = bxt_load_library, 557 }; 558 559 static struct sst_ops skl_ops = { 560 .irq_handler = skl_dsp_sst_interrupt, 561 .write = sst_shim32_write, 562 .read = sst_shim32_read, 563 .ram_read = sst_memcpy_fromio_32, 564 .ram_write = sst_memcpy_toio_32, 565 .free = skl_dsp_free, 566 }; 567 568 static struct sst_dsp_device skl_dev = { 569 .thread = skl_dsp_irq_thread_handler, 570 .ops = &skl_ops, 571 }; 572 573 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 574 const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 575 struct skl_sst **dsp) 576 { 577 struct skl_sst *skl; 578 struct sst_dsp *sst; 579 int ret; 580 581 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 582 if (skl == NULL) 583 return -ENOMEM; 584 585 skl->dev = dev; 586 skl_dev.thread_context = skl; 587 INIT_LIST_HEAD(&skl->uuid_list); 588 589 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 590 if (!skl->dsp) { 591 dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 592 return -ENODEV; 593 } 594 595 sst = skl->dsp; 596 sst->fw_name = fw_name; 597 sst->dsp_ops = dsp_ops; 598 sst->fw_ops = bxt_fw_ops; 599 sst->addr.lpe = mmio_base; 600 sst->addr.shim = mmio_base; 601 602 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 603 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 604 605 INIT_LIST_HEAD(&sst->module_list); 606 ret = skl_ipc_init(dev, skl); 607 if (ret) 608 return ret; 609 610 /* set the D0i3 check */ 611 skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 612 613 skl->cores.count = 2; 614 skl->boot_complete = false; 615 init_waitqueue_head(&skl->boot_wait); 616 skl->is_first_boot = true; 617 INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 618 skl->d0i3.state = SKL_DSP_D0I3_NONE; 619 620 if (dsp) 621 *dsp = skl; 622 623 return 0; 624 } 625 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 626 627 int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 628 { 629 int ret; 630 struct sst_dsp *sst = ctx->dsp; 631 632 ret = sst->fw_ops.load_fw(sst); 633 if (ret < 0) { 634 dev_err(dev, "Load base fw failed: %x\n", ret); 635 return ret; 636 } 637 638 skl_dsp_init_core_state(sst); 639 640 if (ctx->lib_count > 1) { 641 ret = sst->fw_ops.load_library(sst, ctx->lib_info, 642 ctx->lib_count); 643 if (ret < 0) { 644 dev_err(dev, "Load Library failed : %x\n", ret); 645 return ret; 646 } 647 } 648 ctx->is_first_boot = false; 649 650 return 0; 651 } 652 EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 653 654 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 655 { 656 657 sst_bxt_release_library(ctx->lib_info, ctx->lib_count); 658 if (ctx->dsp->fw) 659 release_firmware(ctx->dsp->fw); 660 skl_freeup_uuid_list(ctx); 661 skl_ipc_free(&ctx->ipc); 662 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 663 664 if (ctx->dsp->addr.lpe) 665 iounmap(ctx->dsp->addr.lpe); 666 667 ctx->dsp->ops->free(ctx->dsp); 668 } 669 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 670 671 MODULE_LICENSE("GPL v2"); 672 MODULE_DESCRIPTION("Intel Broxton IPC driver"); 673