192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 2892eb4f62SJeeja KP #define BXT_INIT_TIMEOUT 500 2992eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3092eb4f62SJeeja KP 3192eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3292eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3392eb4f62SJeeja KP 3492eb4f62SJeeja KP /* Firmware status window */ 3592eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3692eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3792eb4f62SJeeja KP 3892eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 3992eb4f62SJeeja KP 4092eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 4192eb4f62SJeeja KP { 4292eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 4392eb4f62SJeeja KP } 4492eb4f62SJeeja KP 4592eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 4692eb4f62SJeeja KP const void *fwdata, u32 fwsize) 4792eb4f62SJeeja KP { 4892eb4f62SJeeja KP int stream_tag, ret, i; 4992eb4f62SJeeja KP u32 reg; 5092eb4f62SJeeja KP 5192eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 5292eb4f62SJeeja KP if (stream_tag < 0) { 5392eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 5492eb4f62SJeeja KP stream_tag); 5592eb4f62SJeeja KP return stream_tag; 5692eb4f62SJeeja KP } 5792eb4f62SJeeja KP 5892eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 5992eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 6092eb4f62SJeeja KP 6192eb4f62SJeeja KP /* Purge FW request */ 6292eb4f62SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 6392eb4f62SJeeja KP BXT_IPC_PURGE_FW | (stream_tag - 1)); 6492eb4f62SJeeja KP 6592eb4f62SJeeja KP ret = skl_dsp_enable_core(ctx); 6692eb4f62SJeeja KP if (ret < 0) { 6792eb4f62SJeeja KP dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret); 6892eb4f62SJeeja KP ret = -EIO; 6992eb4f62SJeeja KP goto base_fw_load_failed; 7092eb4f62SJeeja KP } 7192eb4f62SJeeja KP 7292eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 7392eb4f62SJeeja KP reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE); 7492eb4f62SJeeja KP 7592eb4f62SJeeja KP if (reg & SKL_ADSP_REG_HIPCIE_DONE) { 7692eb4f62SJeeja KP sst_dsp_shim_update_bits_forced(ctx, 7792eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE, 7892eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 7992eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 8092eb4f62SJeeja KP break; 8192eb4f62SJeeja KP } 8292eb4f62SJeeja KP mdelay(1); 8392eb4f62SJeeja KP } 8492eb4f62SJeeja KP if (!i) { 8592eb4f62SJeeja KP dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg); 8692eb4f62SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE, 8792eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 8892eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 8992eb4f62SJeeja KP } 9092eb4f62SJeeja KP 9192eb4f62SJeeja KP /* enable Interrupt */ 9292eb4f62SJeeja KP skl_ipc_int_enable(ctx); 9392eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 9492eb4f62SJeeja KP 9592eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 9692eb4f62SJeeja KP if (SKL_FW_INIT == 9792eb4f62SJeeja KP (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) & 9892eb4f62SJeeja KP SKL_FW_STS_MASK)) { 9992eb4f62SJeeja KP 10092eb4f62SJeeja KP dev_info(ctx->dev, "ROM loaded, continue FW loading\n"); 10192eb4f62SJeeja KP break; 10292eb4f62SJeeja KP } 10392eb4f62SJeeja KP mdelay(1); 10492eb4f62SJeeja KP } 10592eb4f62SJeeja KP if (!i) { 10692eb4f62SJeeja KP dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg); 10792eb4f62SJeeja KP ret = -EIO; 10892eb4f62SJeeja KP goto base_fw_load_failed; 10992eb4f62SJeeja KP } 11092eb4f62SJeeja KP 11192eb4f62SJeeja KP return ret; 11292eb4f62SJeeja KP 11392eb4f62SJeeja KP base_fw_load_failed: 11492eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 11592eb4f62SJeeja KP skl_dsp_disable_core(ctx); 11692eb4f62SJeeja KP return ret; 11792eb4f62SJeeja KP } 11892eb4f62SJeeja KP 11992eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 12092eb4f62SJeeja KP { 12192eb4f62SJeeja KP int ret; 12292eb4f62SJeeja KP 12392eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 12492eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 12592eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 12692eb4f62SJeeja KP 12792eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 12892eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 12992eb4f62SJeeja KP 13092eb4f62SJeeja KP return ret; 13192eb4f62SJeeja KP } 13292eb4f62SJeeja KP 13392eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 13492eb4f62SJeeja KP { 13592eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 13692eb4f62SJeeja KP int ret; 13792eb4f62SJeeja KP 138fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 13992eb4f62SJeeja KP if (ret < 0) { 14092eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 14192eb4f62SJeeja KP goto sst_load_base_firmware_failed; 14292eb4f62SJeeja KP } 14392eb4f62SJeeja KP 144fdfa82eeSVinod Koul ret = sst_bxt_prepare_fw(ctx, ctx->fw->data, ctx->fw->size); 14592eb4f62SJeeja KP /* Retry Enabling core and ROM load. Retry seemed to help */ 14692eb4f62SJeeja KP if (ret < 0) { 147fdfa82eeSVinod Koul ret = sst_bxt_prepare_fw(ctx, ctx->fw->data, ctx->fw->size); 14892eb4f62SJeeja KP if (ret < 0) { 14992eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 15092eb4f62SJeeja KP goto sst_load_base_firmware_failed; 15192eb4f62SJeeja KP } 15292eb4f62SJeeja KP } 15392eb4f62SJeeja KP 15492eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 15592eb4f62SJeeja KP if (ret < 0) { 15692eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 15792eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 15892eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 15992eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 16092eb4f62SJeeja KP 16192eb4f62SJeeja KP skl_dsp_disable_core(ctx); 16292eb4f62SJeeja KP } else { 16392eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 16492eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 16592eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 16692eb4f62SJeeja KP if (ret == 0) { 16792eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 16892eb4f62SJeeja KP skl_dsp_disable_core(ctx); 16992eb4f62SJeeja KP ret = -EIO; 17092eb4f62SJeeja KP } else { 17192eb4f62SJeeja KP skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 17292eb4f62SJeeja KP ret = 0; 17392eb4f62SJeeja KP } 17492eb4f62SJeeja KP } 17592eb4f62SJeeja KP 17692eb4f62SJeeja KP sst_load_base_firmware_failed: 177fdfa82eeSVinod Koul release_firmware(ctx->fw); 17892eb4f62SJeeja KP return ret; 17992eb4f62SJeeja KP } 18092eb4f62SJeeja KP 18192eb4f62SJeeja KP static int bxt_set_dsp_D0(struct sst_dsp *ctx) 18292eb4f62SJeeja KP { 18392eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 18492eb4f62SJeeja KP int ret; 18592eb4f62SJeeja KP 18692eb4f62SJeeja KP skl->boot_complete = false; 18792eb4f62SJeeja KP 18892eb4f62SJeeja KP ret = skl_dsp_enable_core(ctx); 18992eb4f62SJeeja KP if (ret < 0) { 19092eb4f62SJeeja KP dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret); 19192eb4f62SJeeja KP return ret; 19292eb4f62SJeeja KP } 19392eb4f62SJeeja KP 19492eb4f62SJeeja KP /* enable interrupt */ 19592eb4f62SJeeja KP skl_ipc_int_enable(ctx); 19692eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 19792eb4f62SJeeja KP 19892eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 19992eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 20092eb4f62SJeeja KP if (ret == 0) { 20192eb4f62SJeeja KP dev_err(ctx->dev, "ipc: error DSP boot timeout\n"); 20292eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 20392eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 20492eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 20592eb4f62SJeeja KP return -EIO; 20692eb4f62SJeeja KP } 20792eb4f62SJeeja KP 20892eb4f62SJeeja KP skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 20992eb4f62SJeeja KP return 0; 21092eb4f62SJeeja KP } 21192eb4f62SJeeja KP 21292eb4f62SJeeja KP static int bxt_set_dsp_D3(struct sst_dsp *ctx) 21392eb4f62SJeeja KP { 21492eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 21592eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 21692eb4f62SJeeja KP int ret = 0; 21792eb4f62SJeeja KP 21892eb4f62SJeeja KP if (!is_skl_dsp_running(ctx)) 21992eb4f62SJeeja KP return ret; 22092eb4f62SJeeja KP 22192eb4f62SJeeja KP dx.core_mask = SKL_DSP_CORE0_MASK; 22292eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 22392eb4f62SJeeja KP 22492eb4f62SJeeja KP ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, 22592eb4f62SJeeja KP SKL_BASE_FW_MODULE_ID, &dx); 22692eb4f62SJeeja KP if (ret < 0) { 22792eb4f62SJeeja KP dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret); 22892eb4f62SJeeja KP return ret; 22992eb4f62SJeeja KP } 23092eb4f62SJeeja KP 23192eb4f62SJeeja KP ret = skl_dsp_disable_core(ctx); 23292eb4f62SJeeja KP if (ret < 0) { 23392eb4f62SJeeja KP dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret); 23492eb4f62SJeeja KP ret = -EIO; 23592eb4f62SJeeja KP } 23692eb4f62SJeeja KP 23792eb4f62SJeeja KP skl_dsp_set_state_locked(ctx, SKL_DSP_RESET); 23892eb4f62SJeeja KP return 0; 23992eb4f62SJeeja KP } 24092eb4f62SJeeja KP 24192eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 24292eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 24392eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 24492eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 24592eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 24692eb4f62SJeeja KP }; 24792eb4f62SJeeja KP 24892eb4f62SJeeja KP static struct sst_ops skl_ops = { 24992eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 25092eb4f62SJeeja KP .write = sst_shim32_write, 25192eb4f62SJeeja KP .read = sst_shim32_read, 25292eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 25392eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 25492eb4f62SJeeja KP .free = skl_dsp_free, 25592eb4f62SJeeja KP }; 25692eb4f62SJeeja KP 25792eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 25892eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 25992eb4f62SJeeja KP .ops = &skl_ops, 26092eb4f62SJeeja KP }; 26192eb4f62SJeeja KP 26292eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 26392eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 26492eb4f62SJeeja KP struct skl_sst **dsp) 26592eb4f62SJeeja KP { 26692eb4f62SJeeja KP struct skl_sst *skl; 26792eb4f62SJeeja KP struct sst_dsp *sst; 26892eb4f62SJeeja KP int ret; 26992eb4f62SJeeja KP 27092eb4f62SJeeja KP skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 27192eb4f62SJeeja KP if (skl == NULL) 27292eb4f62SJeeja KP return -ENOMEM; 27392eb4f62SJeeja KP 27492eb4f62SJeeja KP skl->dev = dev; 27592eb4f62SJeeja KP skl_dev.thread_context = skl; 27692eb4f62SJeeja KP 27792eb4f62SJeeja KP skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 27892eb4f62SJeeja KP if (!skl->dsp) { 27992eb4f62SJeeja KP dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 28092eb4f62SJeeja KP return -ENODEV; 28192eb4f62SJeeja KP } 28292eb4f62SJeeja KP 28392eb4f62SJeeja KP sst = skl->dsp; 28492eb4f62SJeeja KP sst->fw_name = fw_name; 28592eb4f62SJeeja KP sst->dsp_ops = dsp_ops; 28692eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 28792eb4f62SJeeja KP sst->addr.lpe = mmio_base; 28892eb4f62SJeeja KP sst->addr.shim = mmio_base; 28992eb4f62SJeeja KP 29092eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 29192eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 29292eb4f62SJeeja KP 29392eb4f62SJeeja KP ret = skl_ipc_init(dev, skl); 29492eb4f62SJeeja KP if (ret) 29592eb4f62SJeeja KP return ret; 29692eb4f62SJeeja KP 29792eb4f62SJeeja KP skl->boot_complete = false; 29892eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 29992eb4f62SJeeja KP 30092eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 30192eb4f62SJeeja KP if (ret < 0) { 30292eb4f62SJeeja KP dev_err(dev, "Load base fw failed: %x", ret); 30392eb4f62SJeeja KP return ret; 30492eb4f62SJeeja KP } 30592eb4f62SJeeja KP 30692eb4f62SJeeja KP if (dsp) 30792eb4f62SJeeja KP *dsp = skl; 30892eb4f62SJeeja KP 30992eb4f62SJeeja KP return 0; 31092eb4f62SJeeja KP } 31192eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 31292eb4f62SJeeja KP 31392eb4f62SJeeja KP 31492eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 31592eb4f62SJeeja KP { 31692eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 31792eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 31892eb4f62SJeeja KP 31992eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 32092eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 32192eb4f62SJeeja KP 32292eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 32392eb4f62SJeeja KP } 32492eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 32592eb4f62SJeeja KP 32692eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 32792eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 328