192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 261ef015e6SRamesh Babu #include "skl-tplg-interface.h" 2792eb4f62SJeeja KP 2892eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 2992eb4f62SJeeja KP #define BXT_INIT_TIMEOUT 500 3092eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3192eb4f62SJeeja KP 3292eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3392eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3492eb4f62SJeeja KP 3592eb4f62SJeeja KP /* Firmware status window */ 3692eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3792eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3892eb4f62SJeeja KP 3992eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 4092eb4f62SJeeja KP 41e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 42e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 43e68aca08SJayachandran B 441ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 451ef015e6SRamesh Babu 4692eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 4792eb4f62SJeeja KP { 4892eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 4992eb4f62SJeeja KP } 5092eb4f62SJeeja KP 511ef015e6SRamesh Babu static int 521ef015e6SRamesh Babu bxt_load_library(struct sst_dsp *ctx, struct skl_dfw_manifest *minfo) 531ef015e6SRamesh Babu { 541ef015e6SRamesh Babu struct snd_dma_buffer dmab; 551ef015e6SRamesh Babu struct skl_sst *skl = ctx->thread_context; 561ef015e6SRamesh Babu const struct firmware *fw = NULL; 571ef015e6SRamesh Babu struct firmware stripped_fw; 581ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 591ef015e6SRamesh Babu 601ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 611ef015e6SRamesh Babu for (i = 1; i < minfo->lib_count; i++) { 621ef015e6SRamesh Babu ret = request_firmware(&fw, minfo->lib[i].name, ctx->dev); 631ef015e6SRamesh Babu if (ret < 0) { 641ef015e6SRamesh Babu dev_err(ctx->dev, "Request lib %s failed:%d\n", 651ef015e6SRamesh Babu minfo->lib[i].name, ret); 661ef015e6SRamesh Babu return ret; 671ef015e6SRamesh Babu } 681ef015e6SRamesh Babu 691ef015e6SRamesh Babu if (skl->is_first_boot) { 701ef015e6SRamesh Babu ret = snd_skl_parse_uuids(ctx, fw, 711ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 721ef015e6SRamesh Babu if (ret < 0) 731ef015e6SRamesh Babu goto load_library_failed; 741ef015e6SRamesh Babu } 751ef015e6SRamesh Babu 761ef015e6SRamesh Babu stripped_fw.data = fw->data; 771ef015e6SRamesh Babu stripped_fw.size = fw->size; 781ef015e6SRamesh Babu skl_dsp_strip_extended_manifest(&stripped_fw); 791ef015e6SRamesh Babu 801ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 811ef015e6SRamesh Babu stripped_fw.size, &dmab); 821ef015e6SRamesh Babu if (stream_tag <= 0) { 831ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 841ef015e6SRamesh Babu stream_tag); 851ef015e6SRamesh Babu ret = stream_tag; 861ef015e6SRamesh Babu goto load_library_failed; 871ef015e6SRamesh Babu } 881ef015e6SRamesh Babu 891ef015e6SRamesh Babu dma_id = stream_tag - 1; 901ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 911ef015e6SRamesh Babu 921ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 931ef015e6SRamesh Babu ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 941ef015e6SRamesh Babu if (ret < 0) 951ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 961ef015e6SRamesh Babu minfo->lib[i].name, ret); 971ef015e6SRamesh Babu 981ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 991ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 1001ef015e6SRamesh Babu release_firmware(fw); 1011ef015e6SRamesh Babu fw = NULL; 1021ef015e6SRamesh Babu } 1031ef015e6SRamesh Babu 1041ef015e6SRamesh Babu return ret; 1051ef015e6SRamesh Babu 1061ef015e6SRamesh Babu load_library_failed: 1071ef015e6SRamesh Babu release_firmware(fw); 1081ef015e6SRamesh Babu return ret; 1091ef015e6SRamesh Babu } 1101ef015e6SRamesh Babu 111e68aca08SJayachandran B /* 112e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 113e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 114e68aca08SJayachandran B * reset/stall and then turn it off 115e68aca08SJayachandran B */ 11692eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 11792eb4f62SJeeja KP const void *fwdata, u32 fwsize) 11892eb4f62SJeeja KP { 11992eb4f62SJeeja KP int stream_tag, ret, i; 12092eb4f62SJeeja KP u32 reg; 12192eb4f62SJeeja KP 12292eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 123e68aca08SJayachandran B if (stream_tag <= 0) { 12492eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 12592eb4f62SJeeja KP stream_tag); 12692eb4f62SJeeja KP return stream_tag; 12792eb4f62SJeeja KP } 12892eb4f62SJeeja KP 12992eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 13092eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 13192eb4f62SJeeja KP 132e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 133e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 134e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 13592eb4f62SJeeja KP if (ret < 0) { 136e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1372023576dSSenthilnathan Veppur goto base_fw_load_failed; 1382023576dSSenthilnathan Veppur } 1392023576dSSenthilnathan Veppur 140e68aca08SJayachandran B /* Step 2: Purge FW request */ 1412023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1422023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1432023576dSSenthilnathan Veppur 144e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 145052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1462023576dSSenthilnathan Veppur if (ret < 0) { 1472023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 14892eb4f62SJeeja KP ret = -EIO; 14992eb4f62SJeeja KP goto base_fw_load_failed; 15092eb4f62SJeeja KP } 15192eb4f62SJeeja KP 152e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 15392eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 15492eb4f62SJeeja KP reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE); 15592eb4f62SJeeja KP 15692eb4f62SJeeja KP if (reg & SKL_ADSP_REG_HIPCIE_DONE) { 15792eb4f62SJeeja KP sst_dsp_shim_update_bits_forced(ctx, 15892eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE, 15992eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 16092eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 16192eb4f62SJeeja KP break; 16292eb4f62SJeeja KP } 16392eb4f62SJeeja KP mdelay(1); 16492eb4f62SJeeja KP } 16592eb4f62SJeeja KP if (!i) { 16692eb4f62SJeeja KP dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg); 16792eb4f62SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE, 16892eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 16992eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 17092eb4f62SJeeja KP } 17192eb4f62SJeeja KP 172e68aca08SJayachandran B /* Step 5: power down core1 */ 173e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 174e68aca08SJayachandran B if (ret < 0) { 175e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 176e68aca08SJayachandran B goto base_fw_load_failed; 177e68aca08SJayachandran B } 178e68aca08SJayachandran B 179e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 18092eb4f62SJeeja KP skl_ipc_int_enable(ctx); 18192eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 18292eb4f62SJeeja KP 183e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 18492eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 18592eb4f62SJeeja KP if (SKL_FW_INIT == 18692eb4f62SJeeja KP (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) & 18792eb4f62SJeeja KP SKL_FW_STS_MASK)) { 18892eb4f62SJeeja KP 18992eb4f62SJeeja KP dev_info(ctx->dev, "ROM loaded, continue FW loading\n"); 19092eb4f62SJeeja KP break; 19192eb4f62SJeeja KP } 19292eb4f62SJeeja KP mdelay(1); 19392eb4f62SJeeja KP } 19492eb4f62SJeeja KP if (!i) { 19592eb4f62SJeeja KP dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg); 19692eb4f62SJeeja KP ret = -EIO; 19792eb4f62SJeeja KP goto base_fw_load_failed; 19892eb4f62SJeeja KP } 19992eb4f62SJeeja KP 20092eb4f62SJeeja KP return ret; 20192eb4f62SJeeja KP 20292eb4f62SJeeja KP base_fw_load_failed: 20392eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 204052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 205c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 20692eb4f62SJeeja KP return ret; 20792eb4f62SJeeja KP } 20892eb4f62SJeeja KP 20992eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 21092eb4f62SJeeja KP { 21192eb4f62SJeeja KP int ret; 21292eb4f62SJeeja KP 21392eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 21492eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 21592eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 21692eb4f62SJeeja KP 21792eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 21892eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 21992eb4f62SJeeja KP 22092eb4f62SJeeja KP return ret; 22192eb4f62SJeeja KP } 22292eb4f62SJeeja KP 22392eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 22492eb4f62SJeeja KP { 225bf242d19SVinod Koul struct firmware stripped_fw; 22692eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 22792eb4f62SJeeja KP int ret; 22892eb4f62SJeeja KP 229fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 23092eb4f62SJeeja KP if (ret < 0) { 23192eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 23292eb4f62SJeeja KP goto sst_load_base_firmware_failed; 23392eb4f62SJeeja KP } 23492eb4f62SJeeja KP 235bf242d19SVinod Koul /* check for extended manifest */ 236bf242d19SVinod Koul if (ctx->fw == NULL) 237bf242d19SVinod Koul goto sst_load_base_firmware_failed; 238bf242d19SVinod Koul 2390bdd6d8bSVinod Koul /* prase uuids on first boot */ 2400bdd6d8bSVinod Koul if (skl->is_first_boot) { 241a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2423467a64dSVinod Koul if (ret < 0) 2433467a64dSVinod Koul goto sst_load_base_firmware_failed; 2440bdd6d8bSVinod Koul } 245bf242d19SVinod Koul 246bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 247bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 248bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 249bf242d19SVinod Koul 250bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 25192eb4f62SJeeja KP /* Retry Enabling core and ROM load. Retry seemed to help */ 25292eb4f62SJeeja KP if (ret < 0) { 253bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 25492eb4f62SJeeja KP if (ret < 0) { 2552023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2562023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2572023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2582023576dSSenthilnathan Veppur 25992eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 26092eb4f62SJeeja KP goto sst_load_base_firmware_failed; 26192eb4f62SJeeja KP } 26292eb4f62SJeeja KP } 26392eb4f62SJeeja KP 26492eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 26592eb4f62SJeeja KP if (ret < 0) { 26692eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 26792eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 26892eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 26992eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 27092eb4f62SJeeja KP 271052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 27292eb4f62SJeeja KP } else { 27392eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 27492eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 27592eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 27692eb4f62SJeeja KP if (ret == 0) { 27792eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 278052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 27992eb4f62SJeeja KP ret = -EIO; 28092eb4f62SJeeja KP } else { 28192eb4f62SJeeja KP ret = 0; 2821665c177SJayachandran B skl->fw_loaded = true; 28392eb4f62SJeeja KP } 28492eb4f62SJeeja KP } 28592eb4f62SJeeja KP 28692eb4f62SJeeja KP sst_load_base_firmware_failed: 287fdfa82eeSVinod Koul release_firmware(ctx->fw); 28892eb4f62SJeeja KP return ret; 28992eb4f62SJeeja KP } 29092eb4f62SJeeja KP 291052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 29292eb4f62SJeeja KP { 29392eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 29492eb4f62SJeeja KP int ret; 295e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 296e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 2971ef015e6SRamesh Babu struct skl_dfw_manifest *minfo = &skl->manifest; 29892eb4f62SJeeja KP 2991665c177SJayachandran B if (skl->fw_loaded == false) { 30092eb4f62SJeeja KP skl->boot_complete = false; 3011665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 3021ef015e6SRamesh Babu if (ret < 0) { 3031665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 30492eb4f62SJeeja KP return ret; 30592eb4f62SJeeja KP } 30692eb4f62SJeeja KP 3071ef015e6SRamesh Babu if (minfo->lib_count > 1) { 3081ef015e6SRamesh Babu ret = bxt_load_library(ctx, minfo); 3091ef015e6SRamesh Babu if (ret < 0) { 3101ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 3111ef015e6SRamesh Babu return ret; 3121ef015e6SRamesh Babu } 3131ef015e6SRamesh Babu } 3141ef015e6SRamesh Babu return ret; 3151ef015e6SRamesh Babu } 3161ef015e6SRamesh Babu 317e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 318e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 319e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 320e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 321e68aca08SJayachandran B else 322e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 32392eb4f62SJeeja KP 324e68aca08SJayachandran B if (ret < 0) 325e68aca08SJayachandran B goto err; 326e68aca08SJayachandran B 327e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 328e68aca08SJayachandran B 329e68aca08SJayachandran B /* 330e68aca08SJayachandran B * Enable interrupt after SPA is set and before 331e68aca08SJayachandran B * DSP is unstalled 332e68aca08SJayachandran B */ 33392eb4f62SJeeja KP skl_ipc_int_enable(ctx); 33492eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 335e68aca08SJayachandran B skl->boot_complete = false; 336e68aca08SJayachandran B } 33792eb4f62SJeeja KP 338e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 339e68aca08SJayachandran B if (ret < 0) 340e68aca08SJayachandran B goto err; 341e68aca08SJayachandran B 342e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 343e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 344e68aca08SJayachandran B skl->boot_complete, 34592eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 346e68aca08SJayachandran B 347e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 348e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 34992eb4f62SJeeja KP if (ret == 0) { 350e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 35192eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 35292eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 35392eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 354e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 355e68aca08SJayachandran B ret = -EIO; 356e68aca08SJayachandran B goto err; 357e68aca08SJayachandran B } 35892eb4f62SJeeja KP } 35992eb4f62SJeeja KP 360e68aca08SJayachandran B /* Tell FW if additional core in now On */ 361e68aca08SJayachandran B 362e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 363e68aca08SJayachandran B dx.core_mask = core_mask; 364e68aca08SJayachandran B dx.dx_mask = core_mask; 365e68aca08SJayachandran B 366e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 367e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 368e68aca08SJayachandran B if (ret < 0) { 369e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 370e68aca08SJayachandran B core_id, ret); 371e68aca08SJayachandran B goto err; 372e68aca08SJayachandran B } 373e68aca08SJayachandran B } 374e68aca08SJayachandran B 375e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 37692eb4f62SJeeja KP return 0; 377e68aca08SJayachandran B err: 378e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 379e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 380e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 381e68aca08SJayachandran B 382e68aca08SJayachandran B return ret; 38392eb4f62SJeeja KP } 38492eb4f62SJeeja KP 385052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 38692eb4f62SJeeja KP { 387e68aca08SJayachandran B int ret; 38892eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 38992eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 390e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 39192eb4f62SJeeja KP 392e68aca08SJayachandran B dx.core_mask = core_mask; 39392eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 39492eb4f62SJeeja KP 395e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 396e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 397e68aca08SJayachandran B 398e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 399e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 400e68aca08SJayachandran B if (ret < 0) 401e68aca08SJayachandran B dev_err(ctx->dev, 402e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 403e68aca08SJayachandran B core_id); 404e68aca08SJayachandran B 405e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 40692eb4f62SJeeja KP if (ret < 0) { 407ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 40892eb4f62SJeeja KP return ret; 40992eb4f62SJeeja KP } 410e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 41192eb4f62SJeeja KP return 0; 41292eb4f62SJeeja KP } 41392eb4f62SJeeja KP 41492eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 41592eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 41692eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 41792eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 41892eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 4191ef015e6SRamesh Babu .load_library = bxt_load_library, 42092eb4f62SJeeja KP }; 42192eb4f62SJeeja KP 42292eb4f62SJeeja KP static struct sst_ops skl_ops = { 42392eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 42492eb4f62SJeeja KP .write = sst_shim32_write, 42592eb4f62SJeeja KP .read = sst_shim32_read, 42692eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 42792eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 42892eb4f62SJeeja KP .free = skl_dsp_free, 42992eb4f62SJeeja KP }; 43092eb4f62SJeeja KP 43192eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 43292eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 43392eb4f62SJeeja KP .ops = &skl_ops, 43492eb4f62SJeeja KP }; 43592eb4f62SJeeja KP 43692eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 43792eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 43892eb4f62SJeeja KP struct skl_sst **dsp) 43992eb4f62SJeeja KP { 44092eb4f62SJeeja KP struct skl_sst *skl; 44192eb4f62SJeeja KP struct sst_dsp *sst; 44292eb4f62SJeeja KP int ret; 44392eb4f62SJeeja KP 44492eb4f62SJeeja KP skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 44592eb4f62SJeeja KP if (skl == NULL) 44692eb4f62SJeeja KP return -ENOMEM; 44792eb4f62SJeeja KP 44892eb4f62SJeeja KP skl->dev = dev; 44992eb4f62SJeeja KP skl_dev.thread_context = skl; 4503467a64dSVinod Koul INIT_LIST_HEAD(&skl->uuid_list); 45192eb4f62SJeeja KP 45292eb4f62SJeeja KP skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 45392eb4f62SJeeja KP if (!skl->dsp) { 45492eb4f62SJeeja KP dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 45592eb4f62SJeeja KP return -ENODEV; 45692eb4f62SJeeja KP } 45792eb4f62SJeeja KP 45892eb4f62SJeeja KP sst = skl->dsp; 45992eb4f62SJeeja KP sst->fw_name = fw_name; 46092eb4f62SJeeja KP sst->dsp_ops = dsp_ops; 46192eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 46292eb4f62SJeeja KP sst->addr.lpe = mmio_base; 46392eb4f62SJeeja KP sst->addr.shim = mmio_base; 46492eb4f62SJeeja KP 46592eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 46692eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 46792eb4f62SJeeja KP 468b914bb55SVinod Koul INIT_LIST_HEAD(&sst->module_list); 46992eb4f62SJeeja KP ret = skl_ipc_init(dev, skl); 47092eb4f62SJeeja KP if (ret) 47192eb4f62SJeeja KP return ret; 47292eb4f62SJeeja KP 473052f103cSJayachandran B skl->cores.count = 2; 47492eb4f62SJeeja KP skl->boot_complete = false; 47592eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 47678cdbbdaSVinod Koul skl->is_first_boot = true; 47778cdbbdaSVinod Koul 47878cdbbdaSVinod Koul if (dsp) 47978cdbbdaSVinod Koul *dsp = skl; 48078cdbbdaSVinod Koul 48178cdbbdaSVinod Koul return 0; 48278cdbbdaSVinod Koul } 48378cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 48478cdbbdaSVinod Koul 48578cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 48678cdbbdaSVinod Koul { 48778cdbbdaSVinod Koul int ret; 48878cdbbdaSVinod Koul struct sst_dsp *sst = ctx->dsp; 48992eb4f62SJeeja KP 49092eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 49192eb4f62SJeeja KP if (ret < 0) { 492ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 49392eb4f62SJeeja KP return ret; 49492eb4f62SJeeja KP } 49592eb4f62SJeeja KP 496052f103cSJayachandran B skl_dsp_init_core_state(sst); 497052f103cSJayachandran B 4981ef015e6SRamesh Babu if (ctx->manifest.lib_count > 1) { 4991ef015e6SRamesh Babu ret = sst->fw_ops.load_library(sst, &ctx->manifest); 5001ef015e6SRamesh Babu if (ret < 0) { 501ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 5021ef015e6SRamesh Babu return ret; 5031ef015e6SRamesh Babu } 5041ef015e6SRamesh Babu } 50578cdbbdaSVinod Koul ctx->is_first_boot = false; 50692eb4f62SJeeja KP 50792eb4f62SJeeja KP return 0; 50892eb4f62SJeeja KP } 50978cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 51092eb4f62SJeeja KP 51192eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 51292eb4f62SJeeja KP { 5133467a64dSVinod Koul skl_freeup_uuid_list(ctx); 51492eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 51592eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 51692eb4f62SJeeja KP 51792eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 51892eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 51992eb4f62SJeeja KP 52092eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 52192eb4f62SJeeja KP } 52292eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 52392eb4f62SJeeja KP 52492eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 52592eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 526