192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 287d3f91dcSJeeja KP #define BXT_INIT_TIMEOUT 300 297d3f91dcSJeeja KP #define BXT_ROM_INIT_TIMEOUT 70 3092eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3192eb4f62SJeeja KP 3292eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3392eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3492eb4f62SJeeja KP 3592eb4f62SJeeja KP /* Firmware status window */ 3692eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3792eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3892eb4f62SJeeja KP 3992eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 4092eb4f62SJeeja KP 41e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 42e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 43e68aca08SJayachandran B 441ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 451ef015e6SRamesh Babu 465bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */ 475bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000 485bb4cd46SJayachandran B 497d3f91dcSJeeja KP #define BXT_FW_ROM_INIT_RETRY 3 507d3f91dcSJeeja KP 5192eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 5292eb4f62SJeeja KP { 5392eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 5492eb4f62SJeeja KP } 5592eb4f62SJeeja KP 561ef015e6SRamesh Babu static int 57eee0e16fSJeeja KP bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count) 581ef015e6SRamesh Babu { 591ef015e6SRamesh Babu struct snd_dma_buffer dmab; 601ef015e6SRamesh Babu struct skl_sst *skl = ctx->thread_context; 611ef015e6SRamesh Babu struct firmware stripped_fw; 621ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 631ef015e6SRamesh Babu 641ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 65eee0e16fSJeeja KP for (i = 1; i < lib_count; i++) { 66ebe89076SSubhransu S. Prusty ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw, 671ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 681ef015e6SRamesh Babu if (ret < 0) 691ef015e6SRamesh Babu goto load_library_failed; 701ef015e6SRamesh Babu 711ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 721ef015e6SRamesh Babu stripped_fw.size, &dmab); 731ef015e6SRamesh Babu if (stream_tag <= 0) { 741ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 751ef015e6SRamesh Babu stream_tag); 761ef015e6SRamesh Babu ret = stream_tag; 771ef015e6SRamesh Babu goto load_library_failed; 781ef015e6SRamesh Babu } 791ef015e6SRamesh Babu 801ef015e6SRamesh Babu dma_id = stream_tag - 1; 811ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 821ef015e6SRamesh Babu 831ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 841ef015e6SRamesh Babu ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 851ef015e6SRamesh Babu if (ret < 0) 861ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 87eee0e16fSJeeja KP linfo[i].name, ret); 881ef015e6SRamesh Babu 891ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 901ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 911ef015e6SRamesh Babu } 921ef015e6SRamesh Babu 931ef015e6SRamesh Babu return ret; 941ef015e6SRamesh Babu 951ef015e6SRamesh Babu load_library_failed: 96ebe89076SSubhransu S. Prusty skl_release_library(linfo, lib_count); 971ef015e6SRamesh Babu return ret; 981ef015e6SRamesh Babu } 991ef015e6SRamesh Babu 100e68aca08SJayachandran B /* 101e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 102e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 103e68aca08SJayachandran B * reset/stall and then turn it off 104e68aca08SJayachandran B */ 10592eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 10692eb4f62SJeeja KP const void *fwdata, u32 fwsize) 10792eb4f62SJeeja KP { 108eee0e16fSJeeja KP int stream_tag, ret; 10992eb4f62SJeeja KP 11092eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 111e68aca08SJayachandran B if (stream_tag <= 0) { 11292eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 11392eb4f62SJeeja KP stream_tag); 11492eb4f62SJeeja KP return stream_tag; 11592eb4f62SJeeja KP } 11692eb4f62SJeeja KP 11792eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 11892eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 11992eb4f62SJeeja KP 120e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 121e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 122e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 12392eb4f62SJeeja KP if (ret < 0) { 124e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1252023576dSSenthilnathan Veppur goto base_fw_load_failed; 1262023576dSSenthilnathan Veppur } 1272023576dSSenthilnathan Veppur 128e68aca08SJayachandran B /* Step 2: Purge FW request */ 1292023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1302023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1312023576dSSenthilnathan Veppur 132e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 133052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1342023576dSSenthilnathan Veppur if (ret < 0) { 1352023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 13692eb4f62SJeeja KP ret = -EIO; 13792eb4f62SJeeja KP goto base_fw_load_failed; 13892eb4f62SJeeja KP } 13992eb4f62SJeeja KP 140e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 1411448099dSJeeja KP ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE, 14292eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 14392eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 1441448099dSJeeja KP BXT_INIT_TIMEOUT, "HIPCIE Done"); 1451448099dSJeeja KP if (ret < 0) { 1465f75b19eSColin Ian King dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret); 1471448099dSJeeja KP goto base_fw_load_failed; 14892eb4f62SJeeja KP } 14992eb4f62SJeeja KP 150e68aca08SJayachandran B /* Step 5: power down core1 */ 151e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 152e68aca08SJayachandran B if (ret < 0) { 153e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 154e68aca08SJayachandran B goto base_fw_load_failed; 155e68aca08SJayachandran B } 156e68aca08SJayachandran B 157e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 15892eb4f62SJeeja KP skl_ipc_int_enable(ctx); 15992eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 16092eb4f62SJeeja KP 161e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 1621448099dSJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 1637d3f91dcSJeeja KP SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load"); 1641448099dSJeeja KP if (ret < 0) { 1651448099dSJeeja KP dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret); 16692eb4f62SJeeja KP goto base_fw_load_failed; 16792eb4f62SJeeja KP } 16892eb4f62SJeeja KP 16992eb4f62SJeeja KP return ret; 17092eb4f62SJeeja KP 17192eb4f62SJeeja KP base_fw_load_failed: 17292eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 173052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 174c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 17592eb4f62SJeeja KP return ret; 17692eb4f62SJeeja KP } 17792eb4f62SJeeja KP 17892eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 17992eb4f62SJeeja KP { 18092eb4f62SJeeja KP int ret; 18192eb4f62SJeeja KP 18292eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 18392eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 18492eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 18592eb4f62SJeeja KP 18692eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 18792eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 18892eb4f62SJeeja KP 18992eb4f62SJeeja KP return ret; 19092eb4f62SJeeja KP } 19192eb4f62SJeeja KP 19292eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 19392eb4f62SJeeja KP { 194bf242d19SVinod Koul struct firmware stripped_fw; 19592eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 1967d3f91dcSJeeja KP int ret, i; 19792eb4f62SJeeja KP 19831d648f0SJeeja KP if (ctx->fw == NULL) { 199fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 20092eb4f62SJeeja KP if (ret < 0) { 20192eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 20231d648f0SJeeja KP return ret; 20392eb4f62SJeeja KP } 20431d648f0SJeeja KP } 205bf242d19SVinod Koul 2060bdd6d8bSVinod Koul /* prase uuids on first boot */ 2070bdd6d8bSVinod Koul if (skl->is_first_boot) { 208a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2093467a64dSVinod Koul if (ret < 0) 2103467a64dSVinod Koul goto sst_load_base_firmware_failed; 2110bdd6d8bSVinod Koul } 212bf242d19SVinod Koul 213bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 214bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 215bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 216bf242d19SVinod Koul 2177d3f91dcSJeeja KP 2187d3f91dcSJeeja KP for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) { 219bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 2207d3f91dcSJeeja KP if (ret == 0) 2217d3f91dcSJeeja KP break; 2227d3f91dcSJeeja KP } 2237d3f91dcSJeeja KP 22492eb4f62SJeeja KP if (ret < 0) { 2252023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2262023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2272023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2282023576dSSenthilnathan Veppur 22992eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 23092eb4f62SJeeja KP goto sst_load_base_firmware_failed; 23192eb4f62SJeeja KP } 23292eb4f62SJeeja KP 23392eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 23492eb4f62SJeeja KP if (ret < 0) { 23592eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 23692eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 23792eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 23892eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 23992eb4f62SJeeja KP 240052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 24192eb4f62SJeeja KP } else { 24292eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 24392eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 24492eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 24592eb4f62SJeeja KP if (ret == 0) { 24692eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 247052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 24892eb4f62SJeeja KP ret = -EIO; 24992eb4f62SJeeja KP } else { 25092eb4f62SJeeja KP ret = 0; 2511665c177SJayachandran B skl->fw_loaded = true; 25292eb4f62SJeeja KP } 25392eb4f62SJeeja KP } 25492eb4f62SJeeja KP 25531d648f0SJeeja KP return ret; 25631d648f0SJeeja KP 25792eb4f62SJeeja KP sst_load_base_firmware_failed: 258fdfa82eeSVinod Koul release_firmware(ctx->fw); 25931d648f0SJeeja KP ctx->fw = NULL; 26092eb4f62SJeeja KP return ret; 26192eb4f62SJeeja KP } 26292eb4f62SJeeja KP 2635bb4cd46SJayachandran B /* 2645bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase 2655bb4cd46SJayachandran B * ref counts and DSP state 2665bb4cd46SJayachandran B * 2675bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state) 2685bb4cd46SJayachandran B * 2695bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3 2705bb4cd46SJayachandran B * 2715bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies 2725bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 2735bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 2745bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 2755bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 2765bb4cd46SJayachandran B */ 2775bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx) 2785bb4cd46SJayachandran B { 2795bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 2805bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 2815bb4cd46SJayachandran B 2825bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 2835bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2845bb4cd46SJayachandran B 2855bb4cd46SJayachandran B if (d0i3->non_d0i3) 2865bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2875bb4cd46SJayachandran B else if (d0i3->streaming) 2885bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING; 2895bb4cd46SJayachandran B else if (d0i3->non_streaming) 2905bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING; 2915bb4cd46SJayachandran B else 2925bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2935bb4cd46SJayachandran B } 2945bb4cd46SJayachandran B 2955bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work) 2965bb4cd46SJayachandran B { 2975bb4cd46SJayachandran B int ret; 2985bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 2995bb4cd46SJayachandran B struct skl_sst *skl = container_of(work, 3005bb4cd46SJayachandran B struct skl_sst, d0i3.work.work); 3015bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp; 3025bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3035bb4cd46SJayachandran B int target_state; 3045bb4cd46SJayachandran B 3055bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3065bb4cd46SJayachandran B 3075bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */ 3085bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 3095bb4cd46SJayachandran B dev_warn(ctx->dev, 3105bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n"); 3115bb4cd46SJayachandran B return; 3125bb4cd46SJayachandran B } 3135bb4cd46SJayachandran B 3145bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx); 3155bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE) 3165bb4cd46SJayachandran B return; 3175bb4cd46SJayachandran B 3185bb4cd46SJayachandran B msg.instance_id = 0; 3195bb4cd46SJayachandran B msg.module_id = 0; 3205bb4cd46SJayachandran B msg.wake = 1; 3215bb4cd46SJayachandran B msg.streaming = 0; 3225bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING) 3235bb4cd46SJayachandran B msg.streaming = 1; 3245bb4cd46SJayachandran B 3255bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3265bb4cd46SJayachandran B 3275bb4cd46SJayachandran B if (ret < 0) { 3285bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 3295bb4cd46SJayachandran B return; 3305bb4cd46SJayachandran B } 3315bb4cd46SJayachandran B 3325bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 3335bb4cd46SJayachandran B if (skl->update_d0i3c) 3345bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true); 3355bb4cd46SJayachandran B 3365bb4cd46SJayachandran B d0i3->state = target_state; 3375bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 3385bb4cd46SJayachandran B } 3395bb4cd46SJayachandran B 3405bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 3415bb4cd46SJayachandran B { 3425bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3435bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3445bb4cd46SJayachandran B 3455bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */ 3465bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 3475bb4cd46SJayachandran B 3485bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 3495bb4cd46SJayachandran B 3505bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work, 3515bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY)); 3525bb4cd46SJayachandran B } 3535bb4cd46SJayachandran B 3545bb4cd46SJayachandran B return 0; 3555bb4cd46SJayachandran B } 3565bb4cd46SJayachandran B 3575bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 3585bb4cd46SJayachandran B { 3595bb4cd46SJayachandran B int ret; 3605bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3615bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3625bb4cd46SJayachandran B 3635bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3645bb4cd46SJayachandran B 3655bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */ 3665bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work); 3675bb4cd46SJayachandran B 3685bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */ 3695bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 3705bb4cd46SJayachandran B return 0; 3715bb4cd46SJayachandran B 3725bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 3735bb4cd46SJayachandran B 3745bb4cd46SJayachandran B msg.instance_id = 0; 3755bb4cd46SJayachandran B msg.module_id = 0; 3765bb4cd46SJayachandran B msg.streaming = 0; 3775bb4cd46SJayachandran B msg.wake = 0; 3785bb4cd46SJayachandran B 3795bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 3805bb4cd46SJayachandran B msg.streaming = 1; 3815bb4cd46SJayachandran B 3825bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 3835bb4cd46SJayachandran B if (skl->update_d0i3c) 3845bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false); 3855bb4cd46SJayachandran B 3865bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3875bb4cd46SJayachandran B if (ret < 0) { 3885bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 3895bb4cd46SJayachandran B return ret; 3905bb4cd46SJayachandran B } 3915bb4cd46SJayachandran B 3925bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 3935bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE; 3945bb4cd46SJayachandran B 3955bb4cd46SJayachandran B return 0; 3965bb4cd46SJayachandran B } 3975bb4cd46SJayachandran B 398052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 39992eb4f62SJeeja KP { 40092eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 40192eb4f62SJeeja KP int ret; 402e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 403e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 40492eb4f62SJeeja KP 4051665c177SJayachandran B if (skl->fw_loaded == false) { 40692eb4f62SJeeja KP skl->boot_complete = false; 4071665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 4081ef015e6SRamesh Babu if (ret < 0) { 4091665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 41092eb4f62SJeeja KP return ret; 41192eb4f62SJeeja KP } 41292eb4f62SJeeja KP 413eee0e16fSJeeja KP if (skl->lib_count > 1) { 414eee0e16fSJeeja KP ret = bxt_load_library(ctx, skl->lib_info, 415eee0e16fSJeeja KP skl->lib_count); 4161ef015e6SRamesh Babu if (ret < 0) { 4171ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 4181ef015e6SRamesh Babu return ret; 4191ef015e6SRamesh Babu } 4201ef015e6SRamesh Babu } 4211fb344a3SJeeja KP skl->cores.state[core_id] = SKL_DSP_RUNNING; 4221ef015e6SRamesh Babu return ret; 4231ef015e6SRamesh Babu } 4241ef015e6SRamesh Babu 425e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 426e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 427e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 428e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 429e68aca08SJayachandran B else 430e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 43192eb4f62SJeeja KP 432e68aca08SJayachandran B if (ret < 0) 433e68aca08SJayachandran B goto err; 434e68aca08SJayachandran B 435e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 436e68aca08SJayachandran B 437e68aca08SJayachandran B /* 438e68aca08SJayachandran B * Enable interrupt after SPA is set and before 439e68aca08SJayachandran B * DSP is unstalled 440e68aca08SJayachandran B */ 44192eb4f62SJeeja KP skl_ipc_int_enable(ctx); 44292eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 443e68aca08SJayachandran B skl->boot_complete = false; 444e68aca08SJayachandran B } 44592eb4f62SJeeja KP 446e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 447e68aca08SJayachandran B if (ret < 0) 448e68aca08SJayachandran B goto err; 449e68aca08SJayachandran B 450e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 451e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 452e68aca08SJayachandran B skl->boot_complete, 45392eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 454e68aca08SJayachandran B 455e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 456e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 45792eb4f62SJeeja KP if (ret == 0) { 458e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 45992eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 46092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 46192eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 462e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 463e68aca08SJayachandran B ret = -EIO; 464e68aca08SJayachandran B goto err; 465e68aca08SJayachandran B } 46692eb4f62SJeeja KP } 46792eb4f62SJeeja KP 468e68aca08SJayachandran B /* Tell FW if additional core in now On */ 469e68aca08SJayachandran B 470e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 471e68aca08SJayachandran B dx.core_mask = core_mask; 472e68aca08SJayachandran B dx.dx_mask = core_mask; 473e68aca08SJayachandran B 474e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 475e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 476e68aca08SJayachandran B if (ret < 0) { 477e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 478e68aca08SJayachandran B core_id, ret); 479e68aca08SJayachandran B goto err; 480e68aca08SJayachandran B } 481e68aca08SJayachandran B } 482e68aca08SJayachandran B 483e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 48492eb4f62SJeeja KP return 0; 485e68aca08SJayachandran B err: 486e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 487e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 488e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 489e68aca08SJayachandran B 490e68aca08SJayachandran B return ret; 49192eb4f62SJeeja KP } 49292eb4f62SJeeja KP 493052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 49492eb4f62SJeeja KP { 495e68aca08SJayachandran B int ret; 49692eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 49792eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 498e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 49992eb4f62SJeeja KP 500e68aca08SJayachandran B dx.core_mask = core_mask; 50192eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 50292eb4f62SJeeja KP 503e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 504e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 505e68aca08SJayachandran B 506e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 507e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 50803de8c2eSJeeja KP if (ret < 0) { 509e68aca08SJayachandran B dev_err(ctx->dev, 510e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 511e68aca08SJayachandran B core_id); 51203de8c2eSJeeja KP /* 51303de8c2eSJeeja KP * In case of D3 failure, re-download the firmware, so set 51403de8c2eSJeeja KP * fw_loaded to false. 51503de8c2eSJeeja KP */ 51603de8c2eSJeeja KP skl->fw_loaded = false; 51703de8c2eSJeeja KP } 518e68aca08SJayachandran B 5195518af9fSJeeja KP if (core_id == SKL_DSP_CORE0_ID) { 5205518af9fSJeeja KP /* disable Interrupt */ 5215518af9fSJeeja KP skl_ipc_op_int_disable(ctx); 5225518af9fSJeeja KP skl_ipc_int_disable(ctx); 5235518af9fSJeeja KP } 524e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 52592eb4f62SJeeja KP if (ret < 0) { 526ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 52792eb4f62SJeeja KP return ret; 52892eb4f62SJeeja KP } 529e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 53092eb4f62SJeeja KP return 0; 53192eb4f62SJeeja KP } 53292eb4f62SJeeja KP 53392eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 53492eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 53592eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 5365bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3, 5375bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0, 53892eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 53992eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 5401ef015e6SRamesh Babu .load_library = bxt_load_library, 54192eb4f62SJeeja KP }; 54292eb4f62SJeeja KP 54392eb4f62SJeeja KP static struct sst_ops skl_ops = { 54492eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 54592eb4f62SJeeja KP .write = sst_shim32_write, 54692eb4f62SJeeja KP .read = sst_shim32_read, 54792eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 54892eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 54992eb4f62SJeeja KP .free = skl_dsp_free, 55092eb4f62SJeeja KP }; 55192eb4f62SJeeja KP 55292eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 55392eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 55492eb4f62SJeeja KP .ops = &skl_ops, 55592eb4f62SJeeja KP }; 55692eb4f62SJeeja KP 55792eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 55892eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 55992eb4f62SJeeja KP struct skl_sst **dsp) 56092eb4f62SJeeja KP { 56192eb4f62SJeeja KP struct skl_sst *skl; 56292eb4f62SJeeja KP struct sst_dsp *sst; 56392eb4f62SJeeja KP int ret; 56492eb4f62SJeeja KP 5659fe9c711SG Kranthi ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev); 5669fe9c711SG Kranthi if (ret < 0) { 5679fe9c711SG Kranthi dev_err(skl->dev, "%s: no device\n", __func__); 5689fe9c711SG Kranthi return ret; 56992eb4f62SJeeja KP } 57092eb4f62SJeeja KP 5719fe9c711SG Kranthi skl = *dsp; 57292eb4f62SJeeja KP sst = skl->dsp; 57392eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 57492eb4f62SJeeja KP sst->addr.lpe = mmio_base; 57592eb4f62SJeeja KP sst->addr.shim = mmio_base; 57692eb4f62SJeeja KP 57792eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 57892eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 57992eb4f62SJeeja KP 580a83e3b4cSVinod Koul /* set the D0i3 check */ 581a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 582a83e3b4cSVinod Koul 583052f103cSJayachandran B skl->cores.count = 2; 58492eb4f62SJeeja KP skl->boot_complete = false; 58592eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 586a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 587a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE; 58878cdbbdaSVinod Koul 58978cdbbdaSVinod Koul return 0; 59078cdbbdaSVinod Koul } 59178cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 59278cdbbdaSVinod Koul 59378cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 59478cdbbdaSVinod Koul { 59578cdbbdaSVinod Koul int ret; 59678cdbbdaSVinod Koul struct sst_dsp *sst = ctx->dsp; 59792eb4f62SJeeja KP 59892eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 59992eb4f62SJeeja KP if (ret < 0) { 600ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 60192eb4f62SJeeja KP return ret; 60292eb4f62SJeeja KP } 60392eb4f62SJeeja KP 604052f103cSJayachandran B skl_dsp_init_core_state(sst); 605052f103cSJayachandran B 606eee0e16fSJeeja KP if (ctx->lib_count > 1) { 607eee0e16fSJeeja KP ret = sst->fw_ops.load_library(sst, ctx->lib_info, 608eee0e16fSJeeja KP ctx->lib_count); 6091ef015e6SRamesh Babu if (ret < 0) { 610ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 6111ef015e6SRamesh Babu return ret; 6121ef015e6SRamesh Babu } 6131ef015e6SRamesh Babu } 61478cdbbdaSVinod Koul ctx->is_first_boot = false; 61592eb4f62SJeeja KP 61692eb4f62SJeeja KP return 0; 61792eb4f62SJeeja KP } 61878cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 61992eb4f62SJeeja KP 62092eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 62192eb4f62SJeeja KP { 62231d648f0SJeeja KP 623ebe89076SSubhransu S. Prusty skl_release_library(ctx->lib_info, ctx->lib_count); 62431d648f0SJeeja KP if (ctx->dsp->fw) 62531d648f0SJeeja KP release_firmware(ctx->dsp->fw); 6263467a64dSVinod Koul skl_freeup_uuid_list(ctx); 62792eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 62892eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 62992eb4f62SJeeja KP 63092eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 63192eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 63292eb4f62SJeeja KP 63392eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 63492eb4f62SJeeja KP } 63592eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 63692eb4f62SJeeja KP 63792eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 63892eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 639