18e8e69d6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 292eb4f62SJeeja KP /* 392eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 492eb4f62SJeeja KP * 592eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 692eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 792eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 892eb4f62SJeeja KP */ 992eb4f62SJeeja KP 1092eb4f62SJeeja KP #include <linux/module.h> 1192eb4f62SJeeja KP #include <linux/delay.h> 1292eb4f62SJeeja KP #include <linux/firmware.h> 1392eb4f62SJeeja KP #include <linux/device.h> 1492eb4f62SJeeja KP 1592eb4f62SJeeja KP #include "../common/sst-dsp.h" 1692eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 17bcc2a2dcSCezary Rojewski #include "skl.h" 1892eb4f62SJeeja KP 1992eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 207d3f91dcSJeeja KP #define BXT_INIT_TIMEOUT 300 217d3f91dcSJeeja KP #define BXT_ROM_INIT_TIMEOUT 70 2292eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 2392eb4f62SJeeja KP 2492eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 2592eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP /* Firmware status window */ 2892eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 2992eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3092eb4f62SJeeja KP 3192eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 3292eb4f62SJeeja KP 33e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 34e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 35e68aca08SJayachandran B 361ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 371ef015e6SRamesh Babu 385bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */ 395bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000 405bb4cd46SJayachandran B 417d3f91dcSJeeja KP #define BXT_FW_ROM_INIT_RETRY 3 427d3f91dcSJeeja KP 4392eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 4492eb4f62SJeeja KP { 4592eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 4692eb4f62SJeeja KP } 4792eb4f62SJeeja KP 481ef015e6SRamesh Babu static int 49eee0e16fSJeeja KP bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count) 501ef015e6SRamesh Babu { 511ef015e6SRamesh Babu struct snd_dma_buffer dmab; 52bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 531ef015e6SRamesh Babu struct firmware stripped_fw; 541ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 551ef015e6SRamesh Babu 561ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 57eee0e16fSJeeja KP for (i = 1; i < lib_count; i++) { 58ebe89076SSubhransu S. Prusty ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw, 591ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 601ef015e6SRamesh Babu if (ret < 0) 611ef015e6SRamesh Babu goto load_library_failed; 621ef015e6SRamesh Babu 631ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 641ef015e6SRamesh Babu stripped_fw.size, &dmab); 651ef015e6SRamesh Babu if (stream_tag <= 0) { 661ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 671ef015e6SRamesh Babu stream_tag); 681ef015e6SRamesh Babu ret = stream_tag; 691ef015e6SRamesh Babu goto load_library_failed; 701ef015e6SRamesh Babu } 711ef015e6SRamesh Babu 721ef015e6SRamesh Babu dma_id = stream_tag - 1; 731ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 741ef015e6SRamesh Babu 751ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 76100e7f39SSubhransu S. Prusty ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true); 771ef015e6SRamesh Babu if (ret < 0) 781ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 79eee0e16fSJeeja KP linfo[i].name, ret); 801ef015e6SRamesh Babu 811ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 821ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 831ef015e6SRamesh Babu } 841ef015e6SRamesh Babu 851ef015e6SRamesh Babu return ret; 861ef015e6SRamesh Babu 871ef015e6SRamesh Babu load_library_failed: 88ebe89076SSubhransu S. Prusty skl_release_library(linfo, lib_count); 891ef015e6SRamesh Babu return ret; 901ef015e6SRamesh Babu } 911ef015e6SRamesh Babu 92e68aca08SJayachandran B /* 93e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 94e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 95e68aca08SJayachandran B * reset/stall and then turn it off 96e68aca08SJayachandran B */ 9792eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 9892eb4f62SJeeja KP const void *fwdata, u32 fwsize) 9992eb4f62SJeeja KP { 100eee0e16fSJeeja KP int stream_tag, ret; 10192eb4f62SJeeja KP 10292eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 103e68aca08SJayachandran B if (stream_tag <= 0) { 10492eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 10592eb4f62SJeeja KP stream_tag); 10692eb4f62SJeeja KP return stream_tag; 10792eb4f62SJeeja KP } 10892eb4f62SJeeja KP 10992eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 11092eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 11192eb4f62SJeeja KP 112e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 113e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 114e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 11592eb4f62SJeeja KP if (ret < 0) { 116e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1172023576dSSenthilnathan Veppur goto base_fw_load_failed; 1182023576dSSenthilnathan Veppur } 1192023576dSSenthilnathan Veppur 120e68aca08SJayachandran B /* Step 2: Purge FW request */ 1212023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1222023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1232023576dSSenthilnathan Veppur 124e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 125052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1262023576dSSenthilnathan Veppur if (ret < 0) { 1272023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 12892eb4f62SJeeja KP ret = -EIO; 12992eb4f62SJeeja KP goto base_fw_load_failed; 13092eb4f62SJeeja KP } 13192eb4f62SJeeja KP 132e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 1331448099dSJeeja KP ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE, 13492eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 13592eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 1361448099dSJeeja KP BXT_INIT_TIMEOUT, "HIPCIE Done"); 1371448099dSJeeja KP if (ret < 0) { 1385f75b19eSColin Ian King dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret); 1391448099dSJeeja KP goto base_fw_load_failed; 14092eb4f62SJeeja KP } 14192eb4f62SJeeja KP 142e68aca08SJayachandran B /* Step 5: power down core1 */ 143e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 144e68aca08SJayachandran B if (ret < 0) { 145e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 146e68aca08SJayachandran B goto base_fw_load_failed; 147e68aca08SJayachandran B } 148e68aca08SJayachandran B 149e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 15092eb4f62SJeeja KP skl_ipc_int_enable(ctx); 15192eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 15292eb4f62SJeeja KP 153e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 1541448099dSJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 1557d3f91dcSJeeja KP SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load"); 1561448099dSJeeja KP if (ret < 0) { 1571448099dSJeeja KP dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret); 15892eb4f62SJeeja KP goto base_fw_load_failed; 15992eb4f62SJeeja KP } 16092eb4f62SJeeja KP 16192eb4f62SJeeja KP return ret; 16292eb4f62SJeeja KP 16392eb4f62SJeeja KP base_fw_load_failed: 16492eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 165052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 166c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 16792eb4f62SJeeja KP return ret; 16892eb4f62SJeeja KP } 16992eb4f62SJeeja KP 17092eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 17192eb4f62SJeeja KP { 17292eb4f62SJeeja KP int ret; 17392eb4f62SJeeja KP 17492eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 17592eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 17692eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 17792eb4f62SJeeja KP 17892eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 17992eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 18092eb4f62SJeeja KP 18192eb4f62SJeeja KP return ret; 18292eb4f62SJeeja KP } 18392eb4f62SJeeja KP 18492eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 18592eb4f62SJeeja KP { 186bf242d19SVinod Koul struct firmware stripped_fw; 187bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 1887d3f91dcSJeeja KP int ret, i; 18992eb4f62SJeeja KP 19031d648f0SJeeja KP if (ctx->fw == NULL) { 191fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 19292eb4f62SJeeja KP if (ret < 0) { 19392eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 19431d648f0SJeeja KP return ret; 19592eb4f62SJeeja KP } 19631d648f0SJeeja KP } 197bf242d19SVinod Koul 1980bdd6d8bSVinod Koul /* prase uuids on first boot */ 1990bdd6d8bSVinod Koul if (skl->is_first_boot) { 200a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2013467a64dSVinod Koul if (ret < 0) 2023467a64dSVinod Koul goto sst_load_base_firmware_failed; 2030bdd6d8bSVinod Koul } 204bf242d19SVinod Koul 205bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 206bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 207bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 208bf242d19SVinod Koul 2097d3f91dcSJeeja KP 2107d3f91dcSJeeja KP for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) { 211bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 2127d3f91dcSJeeja KP if (ret == 0) 2137d3f91dcSJeeja KP break; 2147d3f91dcSJeeja KP } 2157d3f91dcSJeeja KP 21692eb4f62SJeeja KP if (ret < 0) { 2172023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2182023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2192023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2202023576dSSenthilnathan Veppur 22192eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 22292eb4f62SJeeja KP goto sst_load_base_firmware_failed; 22392eb4f62SJeeja KP } 22492eb4f62SJeeja KP 22592eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 22692eb4f62SJeeja KP if (ret < 0) { 22792eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 22892eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 22992eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 23092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 23192eb4f62SJeeja KP 232052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 23392eb4f62SJeeja KP } else { 23492eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 23592eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 23692eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 23792eb4f62SJeeja KP if (ret == 0) { 23892eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 239052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 24092eb4f62SJeeja KP ret = -EIO; 24192eb4f62SJeeja KP } else { 24292eb4f62SJeeja KP ret = 0; 2431665c177SJayachandran B skl->fw_loaded = true; 24492eb4f62SJeeja KP } 24592eb4f62SJeeja KP } 24692eb4f62SJeeja KP 24731d648f0SJeeja KP return ret; 24831d648f0SJeeja KP 24992eb4f62SJeeja KP sst_load_base_firmware_failed: 250fdfa82eeSVinod Koul release_firmware(ctx->fw); 25131d648f0SJeeja KP ctx->fw = NULL; 25292eb4f62SJeeja KP return ret; 25392eb4f62SJeeja KP } 25492eb4f62SJeeja KP 2555bb4cd46SJayachandran B /* 2565bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase 2575bb4cd46SJayachandran B * ref counts and DSP state 2585bb4cd46SJayachandran B * 2595bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state) 2605bb4cd46SJayachandran B * 2615bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3 2625bb4cd46SJayachandran B * 2635bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies 2645bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 2655bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 2665bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 2675bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 2685bb4cd46SJayachandran B */ 2695bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx) 2705bb4cd46SJayachandran B { 271bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 2725bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 2735bb4cd46SJayachandran B 2745bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 2755bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2765bb4cd46SJayachandran B 2775bb4cd46SJayachandran B if (d0i3->non_d0i3) 2785bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2795bb4cd46SJayachandran B else if (d0i3->streaming) 2805bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING; 2815bb4cd46SJayachandran B else if (d0i3->non_streaming) 2825bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING; 2835bb4cd46SJayachandran B else 2845bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2855bb4cd46SJayachandran B } 2865bb4cd46SJayachandran B 2875bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work) 2885bb4cd46SJayachandran B { 2895bb4cd46SJayachandran B int ret; 2905bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 291bcc2a2dcSCezary Rojewski struct skl_dev *skl = container_of(work, 292bcc2a2dcSCezary Rojewski struct skl_dev, d0i3.work.work); 2935bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp; 2945bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 2955bb4cd46SJayachandran B int target_state; 2965bb4cd46SJayachandran B 2975bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 2985bb4cd46SJayachandran B 2995bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */ 3005bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 3015bb4cd46SJayachandran B dev_warn(ctx->dev, 3025bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n"); 3035bb4cd46SJayachandran B return; 3045bb4cd46SJayachandran B } 3055bb4cd46SJayachandran B 3065bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx); 3075bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE) 3085bb4cd46SJayachandran B return; 3095bb4cd46SJayachandran B 3105bb4cd46SJayachandran B msg.instance_id = 0; 3115bb4cd46SJayachandran B msg.module_id = 0; 3125bb4cd46SJayachandran B msg.wake = 1; 3135bb4cd46SJayachandran B msg.streaming = 0; 3145bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING) 3155bb4cd46SJayachandran B msg.streaming = 1; 3165bb4cd46SJayachandran B 3175bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3185bb4cd46SJayachandran B 3195bb4cd46SJayachandran B if (ret < 0) { 3205bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 3215bb4cd46SJayachandran B return; 3225bb4cd46SJayachandran B } 3235bb4cd46SJayachandran B 3245bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 3255bb4cd46SJayachandran B if (skl->update_d0i3c) 3265bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true); 3275bb4cd46SJayachandran B 3285bb4cd46SJayachandran B d0i3->state = target_state; 3295bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 3305bb4cd46SJayachandran B } 3315bb4cd46SJayachandran B 3325bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 3335bb4cd46SJayachandran B { 334bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 3355bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3365bb4cd46SJayachandran B 3375bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */ 3385bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 3395bb4cd46SJayachandran B 3405bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 3415bb4cd46SJayachandran B 3425bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work, 3435bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY)); 3445bb4cd46SJayachandran B } 3455bb4cd46SJayachandran B 3465bb4cd46SJayachandran B return 0; 3475bb4cd46SJayachandran B } 3485bb4cd46SJayachandran B 3495bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 3505bb4cd46SJayachandran B { 3515bb4cd46SJayachandran B int ret; 3525bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 353bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 3545bb4cd46SJayachandran B 3555bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3565bb4cd46SJayachandran B 3575bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */ 3585bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work); 3595bb4cd46SJayachandran B 3605bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */ 3615bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 3625bb4cd46SJayachandran B return 0; 3635bb4cd46SJayachandran B 3645bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 3655bb4cd46SJayachandran B 3665bb4cd46SJayachandran B msg.instance_id = 0; 3675bb4cd46SJayachandran B msg.module_id = 0; 3685bb4cd46SJayachandran B msg.streaming = 0; 3695bb4cd46SJayachandran B msg.wake = 0; 3705bb4cd46SJayachandran B 3715bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 3725bb4cd46SJayachandran B msg.streaming = 1; 3735bb4cd46SJayachandran B 3745bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 3755bb4cd46SJayachandran B if (skl->update_d0i3c) 3765bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false); 3775bb4cd46SJayachandran B 3785bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3795bb4cd46SJayachandran B if (ret < 0) { 3805bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 3815bb4cd46SJayachandran B return ret; 3825bb4cd46SJayachandran B } 3835bb4cd46SJayachandran B 3845bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 3855bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE; 3865bb4cd46SJayachandran B 3875bb4cd46SJayachandran B return 0; 3885bb4cd46SJayachandran B } 3895bb4cd46SJayachandran B 390052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 39192eb4f62SJeeja KP { 392bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 39392eb4f62SJeeja KP int ret; 394e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 395e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 39692eb4f62SJeeja KP 3971665c177SJayachandran B if (skl->fw_loaded == false) { 39892eb4f62SJeeja KP skl->boot_complete = false; 3991665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 4001ef015e6SRamesh Babu if (ret < 0) { 4011665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 40292eb4f62SJeeja KP return ret; 40392eb4f62SJeeja KP } 40492eb4f62SJeeja KP 405eee0e16fSJeeja KP if (skl->lib_count > 1) { 406eee0e16fSJeeja KP ret = bxt_load_library(ctx, skl->lib_info, 407eee0e16fSJeeja KP skl->lib_count); 4081ef015e6SRamesh Babu if (ret < 0) { 4091ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 4101ef015e6SRamesh Babu return ret; 4111ef015e6SRamesh Babu } 4121ef015e6SRamesh Babu } 4131fb344a3SJeeja KP skl->cores.state[core_id] = SKL_DSP_RUNNING; 4141ef015e6SRamesh Babu return ret; 4151ef015e6SRamesh Babu } 4161ef015e6SRamesh Babu 417e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 418e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 419e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 420e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 421e68aca08SJayachandran B else 422e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 42392eb4f62SJeeja KP 424e68aca08SJayachandran B if (ret < 0) 425e68aca08SJayachandran B goto err; 426e68aca08SJayachandran B 427e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 428e68aca08SJayachandran B 429e68aca08SJayachandran B /* 430e68aca08SJayachandran B * Enable interrupt after SPA is set and before 431e68aca08SJayachandran B * DSP is unstalled 432e68aca08SJayachandran B */ 43392eb4f62SJeeja KP skl_ipc_int_enable(ctx); 43492eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 435e68aca08SJayachandran B skl->boot_complete = false; 436e68aca08SJayachandran B } 43792eb4f62SJeeja KP 438e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 439e68aca08SJayachandran B if (ret < 0) 440e68aca08SJayachandran B goto err; 441e68aca08SJayachandran B 442e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 443e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 444e68aca08SJayachandran B skl->boot_complete, 44592eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 446e68aca08SJayachandran B 447e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 448e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 44992eb4f62SJeeja KP if (ret == 0) { 450e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 45192eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 45292eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 45392eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 454e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 455e68aca08SJayachandran B ret = -EIO; 456e68aca08SJayachandran B goto err; 457e68aca08SJayachandran B } 45892eb4f62SJeeja KP } 45992eb4f62SJeeja KP 460e68aca08SJayachandran B /* Tell FW if additional core in now On */ 461e68aca08SJayachandran B 462e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 463e68aca08SJayachandran B dx.core_mask = core_mask; 464e68aca08SJayachandran B dx.dx_mask = core_mask; 465e68aca08SJayachandran B 466e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 467e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 468e68aca08SJayachandran B if (ret < 0) { 469e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 470e68aca08SJayachandran B core_id, ret); 471e68aca08SJayachandran B goto err; 472e68aca08SJayachandran B } 473e68aca08SJayachandran B } 474e68aca08SJayachandran B 475e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 47692eb4f62SJeeja KP return 0; 477e68aca08SJayachandran B err: 478e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 479e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 480e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 481e68aca08SJayachandran B 482e68aca08SJayachandran B return ret; 48392eb4f62SJeeja KP } 48492eb4f62SJeeja KP 485052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 48692eb4f62SJeeja KP { 487e68aca08SJayachandran B int ret; 48892eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 489bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context; 490e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 49192eb4f62SJeeja KP 492e68aca08SJayachandran B dx.core_mask = core_mask; 49392eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 49492eb4f62SJeeja KP 495e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 496e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 497e68aca08SJayachandran B 498e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 499e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 50003de8c2eSJeeja KP if (ret < 0) { 501e68aca08SJayachandran B dev_err(ctx->dev, 502e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 503e68aca08SJayachandran B core_id); 50403de8c2eSJeeja KP /* 50503de8c2eSJeeja KP * In case of D3 failure, re-download the firmware, so set 50603de8c2eSJeeja KP * fw_loaded to false. 50703de8c2eSJeeja KP */ 50803de8c2eSJeeja KP skl->fw_loaded = false; 50903de8c2eSJeeja KP } 510e68aca08SJayachandran B 5115518af9fSJeeja KP if (core_id == SKL_DSP_CORE0_ID) { 5125518af9fSJeeja KP /* disable Interrupt */ 5135518af9fSJeeja KP skl_ipc_op_int_disable(ctx); 5145518af9fSJeeja KP skl_ipc_int_disable(ctx); 5155518af9fSJeeja KP } 516e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 51792eb4f62SJeeja KP if (ret < 0) { 518ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 51992eb4f62SJeeja KP return ret; 52092eb4f62SJeeja KP } 521e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 52292eb4f62SJeeja KP return 0; 52392eb4f62SJeeja KP } 52492eb4f62SJeeja KP 5252788808aSBhumika Goyal static const struct skl_dsp_fw_ops bxt_fw_ops = { 52692eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 52792eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 5285bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3, 5295bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0, 53092eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 53192eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 5321ef015e6SRamesh Babu .load_library = bxt_load_library, 53392eb4f62SJeeja KP }; 53492eb4f62SJeeja KP 53592eb4f62SJeeja KP static struct sst_ops skl_ops = { 53692eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 53792eb4f62SJeeja KP .write = sst_shim32_write, 53892eb4f62SJeeja KP .read = sst_shim32_read, 53992eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 54092eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 54192eb4f62SJeeja KP .free = skl_dsp_free, 54292eb4f62SJeeja KP }; 54392eb4f62SJeeja KP 54492eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 54592eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 54692eb4f62SJeeja KP .ops = &skl_ops, 54792eb4f62SJeeja KP }; 54892eb4f62SJeeja KP 54992eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 55092eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 551bcc2a2dcSCezary Rojewski struct skl_dev **dsp) 55292eb4f62SJeeja KP { 553bcc2a2dcSCezary Rojewski struct skl_dev *skl; 55492eb4f62SJeeja KP struct sst_dsp *sst; 55592eb4f62SJeeja KP int ret; 55692eb4f62SJeeja KP 5579fe9c711SG Kranthi ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev); 5589fe9c711SG Kranthi if (ret < 0) { 559351d74e4SArnd Bergmann dev_err(dev, "%s: no device\n", __func__); 5609fe9c711SG Kranthi return ret; 56192eb4f62SJeeja KP } 56292eb4f62SJeeja KP 5639fe9c711SG Kranthi skl = *dsp; 56492eb4f62SJeeja KP sst = skl->dsp; 56592eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 56692eb4f62SJeeja KP sst->addr.lpe = mmio_base; 56792eb4f62SJeeja KP sst->addr.shim = mmio_base; 56809e914d6SGuneshwor Singh sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE; 56909e914d6SGuneshwor Singh sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE; 57009e914d6SGuneshwor Singh sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ; 57109e914d6SGuneshwor Singh sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ; 57292eb4f62SJeeja KP 57392eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 57492eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 57592eb4f62SJeeja KP 5762eed1b02SGuneshwor Singh ret = skl_ipc_init(dev, skl); 5773b3011adSSubhransu S. Prusty if (ret) { 5783b3011adSSubhransu S. Prusty skl_dsp_free(sst); 5792eed1b02SGuneshwor Singh return ret; 5803b3011adSSubhransu S. Prusty } 5812eed1b02SGuneshwor Singh 582a83e3b4cSVinod Koul /* set the D0i3 check */ 583a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 584a83e3b4cSVinod Koul 58592eb4f62SJeeja KP skl->boot_complete = false; 58692eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 587a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 588a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE; 58978cdbbdaSVinod Koul 5908e9d8e19SSubhransu S. Prusty return skl_dsp_acquire_irq(sst); 59178cdbbdaSVinod Koul } 59278cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 59378cdbbdaSVinod Koul 594bcc2a2dcSCezary Rojewski int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl) 59578cdbbdaSVinod Koul { 59678cdbbdaSVinod Koul int ret; 597bcc2a2dcSCezary Rojewski struct sst_dsp *sst = skl->dsp; 59892eb4f62SJeeja KP 59992eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 60092eb4f62SJeeja KP if (ret < 0) { 601ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 60292eb4f62SJeeja KP return ret; 60392eb4f62SJeeja KP } 60492eb4f62SJeeja KP 605052f103cSJayachandran B skl_dsp_init_core_state(sst); 606052f103cSJayachandran B 607bcc2a2dcSCezary Rojewski if (skl->lib_count > 1) { 608bcc2a2dcSCezary Rojewski ret = sst->fw_ops.load_library(sst, skl->lib_info, 609bcc2a2dcSCezary Rojewski skl->lib_count); 6101ef015e6SRamesh Babu if (ret < 0) { 611ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 6121ef015e6SRamesh Babu return ret; 6131ef015e6SRamesh Babu } 6141ef015e6SRamesh Babu } 615bcc2a2dcSCezary Rojewski skl->is_first_boot = false; 61692eb4f62SJeeja KP 61792eb4f62SJeeja KP return 0; 61892eb4f62SJeeja KP } 61978cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 62092eb4f62SJeeja KP 621bcc2a2dcSCezary Rojewski void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl) 62292eb4f62SJeeja KP { 62331d648f0SJeeja KP 624bcc2a2dcSCezary Rojewski skl_release_library(skl->lib_info, skl->lib_count); 625bcc2a2dcSCezary Rojewski if (skl->dsp->fw) 626bcc2a2dcSCezary Rojewski release_firmware(skl->dsp->fw); 627bcc2a2dcSCezary Rojewski skl_freeup_uuid_list(skl); 628bcc2a2dcSCezary Rojewski skl_ipc_free(&skl->ipc); 629bcc2a2dcSCezary Rojewski skl->dsp->ops->free(skl->dsp); 63092eb4f62SJeeja KP } 63192eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 63292eb4f62SJeeja KP 63392eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 63492eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 635