192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 261ef015e6SRamesh Babu #include "skl-tplg-interface.h" 2792eb4f62SJeeja KP 2892eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 2992eb4f62SJeeja KP #define BXT_INIT_TIMEOUT 500 3092eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3192eb4f62SJeeja KP 3292eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3392eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3492eb4f62SJeeja KP 3592eb4f62SJeeja KP /* Firmware status window */ 3692eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3792eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3892eb4f62SJeeja KP 3992eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 4092eb4f62SJeeja KP 41e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 42e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 43e68aca08SJayachandran B 441ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 451ef015e6SRamesh Babu 465bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */ 475bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000 485bb4cd46SJayachandran B 4992eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 5092eb4f62SJeeja KP { 5192eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 5292eb4f62SJeeja KP } 5392eb4f62SJeeja KP 541ef015e6SRamesh Babu static int 551ef015e6SRamesh Babu bxt_load_library(struct sst_dsp *ctx, struct skl_dfw_manifest *minfo) 561ef015e6SRamesh Babu { 571ef015e6SRamesh Babu struct snd_dma_buffer dmab; 581ef015e6SRamesh Babu struct skl_sst *skl = ctx->thread_context; 591ef015e6SRamesh Babu const struct firmware *fw = NULL; 601ef015e6SRamesh Babu struct firmware stripped_fw; 611ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 621ef015e6SRamesh Babu 631ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 641ef015e6SRamesh Babu for (i = 1; i < minfo->lib_count; i++) { 651ef015e6SRamesh Babu ret = request_firmware(&fw, minfo->lib[i].name, ctx->dev); 661ef015e6SRamesh Babu if (ret < 0) { 671ef015e6SRamesh Babu dev_err(ctx->dev, "Request lib %s failed:%d\n", 681ef015e6SRamesh Babu minfo->lib[i].name, ret); 691ef015e6SRamesh Babu return ret; 701ef015e6SRamesh Babu } 711ef015e6SRamesh Babu 721ef015e6SRamesh Babu if (skl->is_first_boot) { 731ef015e6SRamesh Babu ret = snd_skl_parse_uuids(ctx, fw, 741ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 751ef015e6SRamesh Babu if (ret < 0) 761ef015e6SRamesh Babu goto load_library_failed; 771ef015e6SRamesh Babu } 781ef015e6SRamesh Babu 791ef015e6SRamesh Babu stripped_fw.data = fw->data; 801ef015e6SRamesh Babu stripped_fw.size = fw->size; 811ef015e6SRamesh Babu skl_dsp_strip_extended_manifest(&stripped_fw); 821ef015e6SRamesh Babu 831ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 841ef015e6SRamesh Babu stripped_fw.size, &dmab); 851ef015e6SRamesh Babu if (stream_tag <= 0) { 861ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 871ef015e6SRamesh Babu stream_tag); 881ef015e6SRamesh Babu ret = stream_tag; 891ef015e6SRamesh Babu goto load_library_failed; 901ef015e6SRamesh Babu } 911ef015e6SRamesh Babu 921ef015e6SRamesh Babu dma_id = stream_tag - 1; 931ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 941ef015e6SRamesh Babu 951ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 961ef015e6SRamesh Babu ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 971ef015e6SRamesh Babu if (ret < 0) 981ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 991ef015e6SRamesh Babu minfo->lib[i].name, ret); 1001ef015e6SRamesh Babu 1011ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 1021ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 1031ef015e6SRamesh Babu release_firmware(fw); 1041ef015e6SRamesh Babu fw = NULL; 1051ef015e6SRamesh Babu } 1061ef015e6SRamesh Babu 1071ef015e6SRamesh Babu return ret; 1081ef015e6SRamesh Babu 1091ef015e6SRamesh Babu load_library_failed: 1101ef015e6SRamesh Babu release_firmware(fw); 1111ef015e6SRamesh Babu return ret; 1121ef015e6SRamesh Babu } 1131ef015e6SRamesh Babu 114e68aca08SJayachandran B /* 115e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 116e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 117e68aca08SJayachandran B * reset/stall and then turn it off 118e68aca08SJayachandran B */ 11992eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 12092eb4f62SJeeja KP const void *fwdata, u32 fwsize) 12192eb4f62SJeeja KP { 12292eb4f62SJeeja KP int stream_tag, ret, i; 12392eb4f62SJeeja KP u32 reg; 12492eb4f62SJeeja KP 12592eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 126e68aca08SJayachandran B if (stream_tag <= 0) { 12792eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 12892eb4f62SJeeja KP stream_tag); 12992eb4f62SJeeja KP return stream_tag; 13092eb4f62SJeeja KP } 13192eb4f62SJeeja KP 13292eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 13392eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 13492eb4f62SJeeja KP 135e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 136e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 137e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 13892eb4f62SJeeja KP if (ret < 0) { 139e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1402023576dSSenthilnathan Veppur goto base_fw_load_failed; 1412023576dSSenthilnathan Veppur } 1422023576dSSenthilnathan Veppur 143e68aca08SJayachandran B /* Step 2: Purge FW request */ 1442023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1452023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1462023576dSSenthilnathan Veppur 147e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 148052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1492023576dSSenthilnathan Veppur if (ret < 0) { 1502023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 15192eb4f62SJeeja KP ret = -EIO; 15292eb4f62SJeeja KP goto base_fw_load_failed; 15392eb4f62SJeeja KP } 15492eb4f62SJeeja KP 155e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 15692eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 15792eb4f62SJeeja KP reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE); 15892eb4f62SJeeja KP 15992eb4f62SJeeja KP if (reg & SKL_ADSP_REG_HIPCIE_DONE) { 16092eb4f62SJeeja KP sst_dsp_shim_update_bits_forced(ctx, 16192eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE, 16292eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 16392eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 16492eb4f62SJeeja KP break; 16592eb4f62SJeeja KP } 16692eb4f62SJeeja KP mdelay(1); 16792eb4f62SJeeja KP } 16892eb4f62SJeeja KP if (!i) { 16992eb4f62SJeeja KP dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg); 17092eb4f62SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE, 17192eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 17292eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 17392eb4f62SJeeja KP } 17492eb4f62SJeeja KP 175e68aca08SJayachandran B /* Step 5: power down core1 */ 176e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 177e68aca08SJayachandran B if (ret < 0) { 178e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 179e68aca08SJayachandran B goto base_fw_load_failed; 180e68aca08SJayachandran B } 181e68aca08SJayachandran B 182e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 18392eb4f62SJeeja KP skl_ipc_int_enable(ctx); 18492eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 18592eb4f62SJeeja KP 186e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 18792eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 18892eb4f62SJeeja KP if (SKL_FW_INIT == 18992eb4f62SJeeja KP (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) & 19092eb4f62SJeeja KP SKL_FW_STS_MASK)) { 19192eb4f62SJeeja KP 19292eb4f62SJeeja KP dev_info(ctx->dev, "ROM loaded, continue FW loading\n"); 19392eb4f62SJeeja KP break; 19492eb4f62SJeeja KP } 19592eb4f62SJeeja KP mdelay(1); 19692eb4f62SJeeja KP } 19792eb4f62SJeeja KP if (!i) { 19892eb4f62SJeeja KP dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg); 19992eb4f62SJeeja KP ret = -EIO; 20092eb4f62SJeeja KP goto base_fw_load_failed; 20192eb4f62SJeeja KP } 20292eb4f62SJeeja KP 20392eb4f62SJeeja KP return ret; 20492eb4f62SJeeja KP 20592eb4f62SJeeja KP base_fw_load_failed: 20692eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 207052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 208c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 20992eb4f62SJeeja KP return ret; 21092eb4f62SJeeja KP } 21192eb4f62SJeeja KP 21292eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 21392eb4f62SJeeja KP { 21492eb4f62SJeeja KP int ret; 21592eb4f62SJeeja KP 21692eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 21792eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 21892eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 21992eb4f62SJeeja KP 22092eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 22192eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 22292eb4f62SJeeja KP 22392eb4f62SJeeja KP return ret; 22492eb4f62SJeeja KP } 22592eb4f62SJeeja KP 22692eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 22792eb4f62SJeeja KP { 228bf242d19SVinod Koul struct firmware stripped_fw; 22992eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 23092eb4f62SJeeja KP int ret; 23192eb4f62SJeeja KP 232fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 23392eb4f62SJeeja KP if (ret < 0) { 23492eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 23592eb4f62SJeeja KP goto sst_load_base_firmware_failed; 23692eb4f62SJeeja KP } 23792eb4f62SJeeja KP 238bf242d19SVinod Koul /* check for extended manifest */ 239bf242d19SVinod Koul if (ctx->fw == NULL) 240bf242d19SVinod Koul goto sst_load_base_firmware_failed; 241bf242d19SVinod Koul 2420bdd6d8bSVinod Koul /* prase uuids on first boot */ 2430bdd6d8bSVinod Koul if (skl->is_first_boot) { 244a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2453467a64dSVinod Koul if (ret < 0) 2463467a64dSVinod Koul goto sst_load_base_firmware_failed; 2470bdd6d8bSVinod Koul } 248bf242d19SVinod Koul 249bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 250bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 251bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 252bf242d19SVinod Koul 253bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 25492eb4f62SJeeja KP /* Retry Enabling core and ROM load. Retry seemed to help */ 25592eb4f62SJeeja KP if (ret < 0) { 256bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 25792eb4f62SJeeja KP if (ret < 0) { 2582023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2592023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2602023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2612023576dSSenthilnathan Veppur 26292eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 26392eb4f62SJeeja KP goto sst_load_base_firmware_failed; 26492eb4f62SJeeja KP } 26592eb4f62SJeeja KP } 26692eb4f62SJeeja KP 26792eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 26892eb4f62SJeeja KP if (ret < 0) { 26992eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 27092eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 27192eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 27292eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 27392eb4f62SJeeja KP 274052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 27592eb4f62SJeeja KP } else { 27692eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 27792eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 27892eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 27992eb4f62SJeeja KP if (ret == 0) { 28092eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 281052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 28292eb4f62SJeeja KP ret = -EIO; 28392eb4f62SJeeja KP } else { 28492eb4f62SJeeja KP ret = 0; 2851665c177SJayachandran B skl->fw_loaded = true; 28692eb4f62SJeeja KP } 28792eb4f62SJeeja KP } 28892eb4f62SJeeja KP 28992eb4f62SJeeja KP sst_load_base_firmware_failed: 290fdfa82eeSVinod Koul release_firmware(ctx->fw); 29192eb4f62SJeeja KP return ret; 29292eb4f62SJeeja KP } 29392eb4f62SJeeja KP 2945bb4cd46SJayachandran B /* 2955bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase 2965bb4cd46SJayachandran B * ref counts and DSP state 2975bb4cd46SJayachandran B * 2985bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state) 2995bb4cd46SJayachandran B * 3005bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3 3015bb4cd46SJayachandran B * 3025bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies 3035bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 3045bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 3055bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 3065bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 3075bb4cd46SJayachandran B */ 3085bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx) 3095bb4cd46SJayachandran B { 3105bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3115bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3125bb4cd46SJayachandran B 3135bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 3145bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3155bb4cd46SJayachandran B 3165bb4cd46SJayachandran B if (d0i3->non_d0i3) 3175bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3185bb4cd46SJayachandran B else if (d0i3->streaming) 3195bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING; 3205bb4cd46SJayachandran B else if (d0i3->non_streaming) 3215bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING; 3225bb4cd46SJayachandran B else 3235bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3245bb4cd46SJayachandran B } 3255bb4cd46SJayachandran B 3265bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work) 3275bb4cd46SJayachandran B { 3285bb4cd46SJayachandran B int ret; 3295bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3305bb4cd46SJayachandran B struct skl_sst *skl = container_of(work, 3315bb4cd46SJayachandran B struct skl_sst, d0i3.work.work); 3325bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp; 3335bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3345bb4cd46SJayachandran B int target_state; 3355bb4cd46SJayachandran B 3365bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3375bb4cd46SJayachandran B 3385bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */ 3395bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 3405bb4cd46SJayachandran B dev_warn(ctx->dev, 3415bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n"); 3425bb4cd46SJayachandran B return; 3435bb4cd46SJayachandran B } 3445bb4cd46SJayachandran B 3455bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx); 3465bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE) 3475bb4cd46SJayachandran B return; 3485bb4cd46SJayachandran B 3495bb4cd46SJayachandran B msg.instance_id = 0; 3505bb4cd46SJayachandran B msg.module_id = 0; 3515bb4cd46SJayachandran B msg.wake = 1; 3525bb4cd46SJayachandran B msg.streaming = 0; 3535bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING) 3545bb4cd46SJayachandran B msg.streaming = 1; 3555bb4cd46SJayachandran B 3565bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3575bb4cd46SJayachandran B 3585bb4cd46SJayachandran B if (ret < 0) { 3595bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 3605bb4cd46SJayachandran B return; 3615bb4cd46SJayachandran B } 3625bb4cd46SJayachandran B 3635bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 3645bb4cd46SJayachandran B if (skl->update_d0i3c) 3655bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true); 3665bb4cd46SJayachandran B 3675bb4cd46SJayachandran B d0i3->state = target_state; 3685bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 3695bb4cd46SJayachandran B } 3705bb4cd46SJayachandran B 3715bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 3725bb4cd46SJayachandran B { 3735bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3745bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3755bb4cd46SJayachandran B 3765bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */ 3775bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 3785bb4cd46SJayachandran B 3795bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 3805bb4cd46SJayachandran B 3815bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work, 3825bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY)); 3835bb4cd46SJayachandran B } 3845bb4cd46SJayachandran B 3855bb4cd46SJayachandran B return 0; 3865bb4cd46SJayachandran B } 3875bb4cd46SJayachandran B 3885bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 3895bb4cd46SJayachandran B { 3905bb4cd46SJayachandran B int ret; 3915bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3925bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3935bb4cd46SJayachandran B 3945bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3955bb4cd46SJayachandran B 3965bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */ 3975bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work); 3985bb4cd46SJayachandran B 3995bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */ 4005bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 4015bb4cd46SJayachandran B return 0; 4025bb4cd46SJayachandran B 4035bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 4045bb4cd46SJayachandran B 4055bb4cd46SJayachandran B msg.instance_id = 0; 4065bb4cd46SJayachandran B msg.module_id = 0; 4075bb4cd46SJayachandran B msg.streaming = 0; 4085bb4cd46SJayachandran B msg.wake = 0; 4095bb4cd46SJayachandran B 4105bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 4115bb4cd46SJayachandran B msg.streaming = 1; 4125bb4cd46SJayachandran B 4135bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 4145bb4cd46SJayachandran B if (skl->update_d0i3c) 4155bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false); 4165bb4cd46SJayachandran B 4175bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 4185bb4cd46SJayachandran B if (ret < 0) { 4195bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 4205bb4cd46SJayachandran B return ret; 4215bb4cd46SJayachandran B } 4225bb4cd46SJayachandran B 4235bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 4245bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE; 4255bb4cd46SJayachandran B 4265bb4cd46SJayachandran B return 0; 4275bb4cd46SJayachandran B } 4285bb4cd46SJayachandran B 429052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 43092eb4f62SJeeja KP { 43192eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 43292eb4f62SJeeja KP int ret; 433e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 434e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 4351ef015e6SRamesh Babu struct skl_dfw_manifest *minfo = &skl->manifest; 43692eb4f62SJeeja KP 4371665c177SJayachandran B if (skl->fw_loaded == false) { 43892eb4f62SJeeja KP skl->boot_complete = false; 4391665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 4401ef015e6SRamesh Babu if (ret < 0) { 4411665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 44292eb4f62SJeeja KP return ret; 44392eb4f62SJeeja KP } 44492eb4f62SJeeja KP 4451ef015e6SRamesh Babu if (minfo->lib_count > 1) { 4461ef015e6SRamesh Babu ret = bxt_load_library(ctx, minfo); 4471ef015e6SRamesh Babu if (ret < 0) { 4481ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 4491ef015e6SRamesh Babu return ret; 4501ef015e6SRamesh Babu } 4511ef015e6SRamesh Babu } 4521ef015e6SRamesh Babu return ret; 4531ef015e6SRamesh Babu } 4541ef015e6SRamesh Babu 455e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 456e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 457e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 458e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 459e68aca08SJayachandran B else 460e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 46192eb4f62SJeeja KP 462e68aca08SJayachandran B if (ret < 0) 463e68aca08SJayachandran B goto err; 464e68aca08SJayachandran B 465e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 466e68aca08SJayachandran B 467e68aca08SJayachandran B /* 468e68aca08SJayachandran B * Enable interrupt after SPA is set and before 469e68aca08SJayachandran B * DSP is unstalled 470e68aca08SJayachandran B */ 47192eb4f62SJeeja KP skl_ipc_int_enable(ctx); 47292eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 473e68aca08SJayachandran B skl->boot_complete = false; 474e68aca08SJayachandran B } 47592eb4f62SJeeja KP 476e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 477e68aca08SJayachandran B if (ret < 0) 478e68aca08SJayachandran B goto err; 479e68aca08SJayachandran B 480e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 481e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 482e68aca08SJayachandran B skl->boot_complete, 48392eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 484e68aca08SJayachandran B 485e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 486e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 48792eb4f62SJeeja KP if (ret == 0) { 488e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 48992eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 49092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 49192eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 492e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 493e68aca08SJayachandran B ret = -EIO; 494e68aca08SJayachandran B goto err; 495e68aca08SJayachandran B } 49692eb4f62SJeeja KP } 49792eb4f62SJeeja KP 498e68aca08SJayachandran B /* Tell FW if additional core in now On */ 499e68aca08SJayachandran B 500e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 501e68aca08SJayachandran B dx.core_mask = core_mask; 502e68aca08SJayachandran B dx.dx_mask = core_mask; 503e68aca08SJayachandran B 504e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 505e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 506e68aca08SJayachandran B if (ret < 0) { 507e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 508e68aca08SJayachandran B core_id, ret); 509e68aca08SJayachandran B goto err; 510e68aca08SJayachandran B } 511e68aca08SJayachandran B } 512e68aca08SJayachandran B 513e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 51492eb4f62SJeeja KP return 0; 515e68aca08SJayachandran B err: 516e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 517e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 518e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 519e68aca08SJayachandran B 520e68aca08SJayachandran B return ret; 52192eb4f62SJeeja KP } 52292eb4f62SJeeja KP 523052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 52492eb4f62SJeeja KP { 525e68aca08SJayachandran B int ret; 52692eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 52792eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 528e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 52992eb4f62SJeeja KP 530e68aca08SJayachandran B dx.core_mask = core_mask; 53192eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 53292eb4f62SJeeja KP 533e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 534e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 535e68aca08SJayachandran B 536e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 537e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 538e68aca08SJayachandran B if (ret < 0) 539e68aca08SJayachandran B dev_err(ctx->dev, 540e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 541e68aca08SJayachandran B core_id); 542e68aca08SJayachandran B 543e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 54492eb4f62SJeeja KP if (ret < 0) { 545ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 54692eb4f62SJeeja KP return ret; 54792eb4f62SJeeja KP } 548e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 54992eb4f62SJeeja KP return 0; 55092eb4f62SJeeja KP } 55192eb4f62SJeeja KP 55292eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 55392eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 55492eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 5555bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3, 5565bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0, 55792eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 55892eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 5591ef015e6SRamesh Babu .load_library = bxt_load_library, 56092eb4f62SJeeja KP }; 56192eb4f62SJeeja KP 56292eb4f62SJeeja KP static struct sst_ops skl_ops = { 56392eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 56492eb4f62SJeeja KP .write = sst_shim32_write, 56592eb4f62SJeeja KP .read = sst_shim32_read, 56692eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 56792eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 56892eb4f62SJeeja KP .free = skl_dsp_free, 56992eb4f62SJeeja KP }; 57092eb4f62SJeeja KP 57192eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 57292eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 57392eb4f62SJeeja KP .ops = &skl_ops, 57492eb4f62SJeeja KP }; 57592eb4f62SJeeja KP 57692eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 57792eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 57892eb4f62SJeeja KP struct skl_sst **dsp) 57992eb4f62SJeeja KP { 58092eb4f62SJeeja KP struct skl_sst *skl; 58192eb4f62SJeeja KP struct sst_dsp *sst; 58292eb4f62SJeeja KP int ret; 58392eb4f62SJeeja KP 58492eb4f62SJeeja KP skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 58592eb4f62SJeeja KP if (skl == NULL) 58692eb4f62SJeeja KP return -ENOMEM; 58792eb4f62SJeeja KP 58892eb4f62SJeeja KP skl->dev = dev; 58992eb4f62SJeeja KP skl_dev.thread_context = skl; 5903467a64dSVinod Koul INIT_LIST_HEAD(&skl->uuid_list); 59192eb4f62SJeeja KP 59292eb4f62SJeeja KP skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 59392eb4f62SJeeja KP if (!skl->dsp) { 59492eb4f62SJeeja KP dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 59592eb4f62SJeeja KP return -ENODEV; 59692eb4f62SJeeja KP } 59792eb4f62SJeeja KP 59892eb4f62SJeeja KP sst = skl->dsp; 59992eb4f62SJeeja KP sst->fw_name = fw_name; 60092eb4f62SJeeja KP sst->dsp_ops = dsp_ops; 60192eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 60292eb4f62SJeeja KP sst->addr.lpe = mmio_base; 60392eb4f62SJeeja KP sst->addr.shim = mmio_base; 60492eb4f62SJeeja KP 60592eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 60692eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 60792eb4f62SJeeja KP 608b914bb55SVinod Koul INIT_LIST_HEAD(&sst->module_list); 60992eb4f62SJeeja KP ret = skl_ipc_init(dev, skl); 61092eb4f62SJeeja KP if (ret) 61192eb4f62SJeeja KP return ret; 61292eb4f62SJeeja KP 613a83e3b4cSVinod Koul /* set the D0i3 check */ 614a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 615a83e3b4cSVinod Koul 616052f103cSJayachandran B skl->cores.count = 2; 61792eb4f62SJeeja KP skl->boot_complete = false; 61892eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 61978cdbbdaSVinod Koul skl->is_first_boot = true; 620a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 621a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE; 62278cdbbdaSVinod Koul 62378cdbbdaSVinod Koul if (dsp) 62478cdbbdaSVinod Koul *dsp = skl; 62578cdbbdaSVinod Koul 62678cdbbdaSVinod Koul return 0; 62778cdbbdaSVinod Koul } 62878cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 62978cdbbdaSVinod Koul 63078cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 63178cdbbdaSVinod Koul { 63278cdbbdaSVinod Koul int ret; 63378cdbbdaSVinod Koul struct sst_dsp *sst = ctx->dsp; 63492eb4f62SJeeja KP 63592eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 63692eb4f62SJeeja KP if (ret < 0) { 637ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 63892eb4f62SJeeja KP return ret; 63992eb4f62SJeeja KP } 64092eb4f62SJeeja KP 641052f103cSJayachandran B skl_dsp_init_core_state(sst); 642052f103cSJayachandran B 6431ef015e6SRamesh Babu if (ctx->manifest.lib_count > 1) { 6441ef015e6SRamesh Babu ret = sst->fw_ops.load_library(sst, &ctx->manifest); 6451ef015e6SRamesh Babu if (ret < 0) { 646ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 6471ef015e6SRamesh Babu return ret; 6481ef015e6SRamesh Babu } 6491ef015e6SRamesh Babu } 65078cdbbdaSVinod Koul ctx->is_first_boot = false; 65192eb4f62SJeeja KP 65292eb4f62SJeeja KP return 0; 65392eb4f62SJeeja KP } 65478cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 65592eb4f62SJeeja KP 65692eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 65792eb4f62SJeeja KP { 6583467a64dSVinod Koul skl_freeup_uuid_list(ctx); 65992eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 66092eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 66192eb4f62SJeeja KP 66292eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 66392eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 66492eb4f62SJeeja KP 66592eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 66692eb4f62SJeeja KP } 66792eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 66892eb4f62SJeeja KP 66992eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 67092eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 671