18e8e69d6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
292eb4f62SJeeja KP /*
392eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform
492eb4f62SJeeja KP *
592eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp
692eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
792eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com>
892eb4f62SJeeja KP */
992eb4f62SJeeja KP
1092eb4f62SJeeja KP #include <linux/module.h>
1192eb4f62SJeeja KP #include <linux/delay.h>
1292eb4f62SJeeja KP #include <linux/firmware.h>
1392eb4f62SJeeja KP #include <linux/device.h>
1492eb4f62SJeeja KP
1592eb4f62SJeeja KP #include "../common/sst-dsp.h"
1692eb4f62SJeeja KP #include "../common/sst-dsp-priv.h"
17bcc2a2dcSCezary Rojewski #include "skl.h"
1892eb4f62SJeeja KP
1992eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000
207d3f91dcSJeeja KP #define BXT_ROM_INIT_TIMEOUT 70
2192eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000
2292eb4f62SJeeja KP
2392eb4f62SJeeja KP #define BXT_ROM_INIT 0x5
2492eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000
2592eb4f62SJeeja KP
2692eb4f62SJeeja KP /* Firmware status window */
2792eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
2892eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
2992eb4f62SJeeja KP
3092eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000
3192eb4f62SJeeja KP
32e68aca08SJayachandran B #define BXT_INSTANCE_ID 0
33e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0
34e68aca08SJayachandran B
351ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
361ef015e6SRamesh Babu
375bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */
385bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000
395bb4cd46SJayachandran B
bxt_get_errorcode(struct sst_dsp * ctx)4092eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
4192eb4f62SJeeja KP {
4292eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
4392eb4f62SJeeja KP }
4492eb4f62SJeeja KP
451ef015e6SRamesh Babu static int
bxt_load_library(struct sst_dsp * ctx,struct skl_lib_info * linfo,int lib_count)46eee0e16fSJeeja KP bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
471ef015e6SRamesh Babu {
481ef015e6SRamesh Babu struct snd_dma_buffer dmab;
49bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
501ef015e6SRamesh Babu struct firmware stripped_fw;
511ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag;
521ef015e6SRamesh Babu
531ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */
54eee0e16fSJeeja KP for (i = 1; i < lib_count; i++) {
55ebe89076SSubhransu S. Prusty ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
561ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i);
571ef015e6SRamesh Babu if (ret < 0)
581ef015e6SRamesh Babu goto load_library_failed;
591ef015e6SRamesh Babu
601ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
611ef015e6SRamesh Babu stripped_fw.size, &dmab);
621ef015e6SRamesh Babu if (stream_tag <= 0) {
631ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
641ef015e6SRamesh Babu stream_tag);
651ef015e6SRamesh Babu ret = stream_tag;
661ef015e6SRamesh Babu goto load_library_failed;
671ef015e6SRamesh Babu }
681ef015e6SRamesh Babu
691ef015e6SRamesh Babu dma_id = stream_tag - 1;
701ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
711ef015e6SRamesh Babu
721ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
73100e7f39SSubhransu S. Prusty ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
741ef015e6SRamesh Babu if (ret < 0)
751ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
76eee0e16fSJeeja KP linfo[i].name, ret);
771ef015e6SRamesh Babu
781ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
791ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
801ef015e6SRamesh Babu }
811ef015e6SRamesh Babu
821ef015e6SRamesh Babu return ret;
831ef015e6SRamesh Babu
841ef015e6SRamesh Babu load_library_failed:
85ebe89076SSubhransu S. Prusty skl_release_library(linfo, lib_count);
861ef015e6SRamesh Babu return ret;
871ef015e6SRamesh Babu }
881ef015e6SRamesh Babu
89e68aca08SJayachandran B /*
90e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power
91e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in
92e68aca08SJayachandran B * reset/stall and then turn it off
93e68aca08SJayachandran B */
sst_bxt_prepare_fw(struct sst_dsp * ctx,const void * fwdata,u32 fwsize)9492eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
9592eb4f62SJeeja KP const void *fwdata, u32 fwsize)
9692eb4f62SJeeja KP {
97eee0e16fSJeeja KP int stream_tag, ret;
9892eb4f62SJeeja KP
9992eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
100e68aca08SJayachandran B if (stream_tag <= 0) {
10192eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
10292eb4f62SJeeja KP stream_tag);
10392eb4f62SJeeja KP return stream_tag;
10492eb4f62SJeeja KP }
10592eb4f62SJeeja KP
10692eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag;
10792eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize);
10892eb4f62SJeeja KP
109e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */
110e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
111e68aca08SJayachandran B SKL_DSP_CORE_MASK(1));
11292eb4f62SJeeja KP if (ret < 0) {
113e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n");
1142023576dSSenthilnathan Veppur goto base_fw_load_failed;
1152023576dSSenthilnathan Veppur }
1162023576dSSenthilnathan Veppur
117e68aca08SJayachandran B /* Step 2: Purge FW request */
1182023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
1192023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
1202023576dSSenthilnathan Veppur
121e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */
122052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
1232023576dSSenthilnathan Veppur if (ret < 0) {
1242023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
12592eb4f62SJeeja KP ret = -EIO;
12692eb4f62SJeeja KP goto base_fw_load_failed;
12792eb4f62SJeeja KP }
12892eb4f62SJeeja KP
129e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */
1301448099dSJeeja KP ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
13192eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE,
13292eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE,
1331448099dSJeeja KP BXT_INIT_TIMEOUT, "HIPCIE Done");
1341448099dSJeeja KP if (ret < 0) {
1355f75b19eSColin Ian King dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
1361448099dSJeeja KP goto base_fw_load_failed;
13792eb4f62SJeeja KP }
13892eb4f62SJeeja KP
139e68aca08SJayachandran B /* Step 5: power down core1 */
140e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
141e68aca08SJayachandran B if (ret < 0) {
142e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n");
143e68aca08SJayachandran B goto base_fw_load_failed;
144e68aca08SJayachandran B }
145e68aca08SJayachandran B
146e68aca08SJayachandran B /* Step 6: Enable Interrupt */
14792eb4f62SJeeja KP skl_ipc_int_enable(ctx);
14892eb4f62SJeeja KP skl_ipc_op_int_enable(ctx);
14992eb4f62SJeeja KP
150e68aca08SJayachandran B /* Step 7: Wait for ROM init */
1511448099dSJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
1527d3f91dcSJeeja KP SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
1531448099dSJeeja KP if (ret < 0) {
1541448099dSJeeja KP dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
15592eb4f62SJeeja KP goto base_fw_load_failed;
15692eb4f62SJeeja KP }
15792eb4f62SJeeja KP
15892eb4f62SJeeja KP return ret;
15992eb4f62SJeeja KP
16092eb4f62SJeeja KP base_fw_load_failed:
16192eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
162052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
163c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
16492eb4f62SJeeja KP return ret;
16592eb4f62SJeeja KP }
16692eb4f62SJeeja KP
sst_transfer_fw_host_dma(struct sst_dsp * ctx)16792eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
16892eb4f62SJeeja KP {
16992eb4f62SJeeja KP int ret;
17092eb4f62SJeeja KP
17192eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
17292eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
17392eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
17492eb4f62SJeeja KP
17592eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
17692eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
17792eb4f62SJeeja KP
17892eb4f62SJeeja KP return ret;
17992eb4f62SJeeja KP }
18092eb4f62SJeeja KP
bxt_load_base_firmware(struct sst_dsp * ctx)18192eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx)
18292eb4f62SJeeja KP {
183bf242d19SVinod Koul struct firmware stripped_fw;
184bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
1857d3f91dcSJeeja KP int ret, i;
18692eb4f62SJeeja KP
18731d648f0SJeeja KP if (ctx->fw == NULL) {
188fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
18992eb4f62SJeeja KP if (ret < 0) {
19092eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret);
19131d648f0SJeeja KP return ret;
19292eb4f62SJeeja KP }
19331d648f0SJeeja KP }
194bf242d19SVinod Koul
1950bdd6d8bSVinod Koul /* prase uuids on first boot */
1960bdd6d8bSVinod Koul if (skl->is_first_boot) {
197a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
1983467a64dSVinod Koul if (ret < 0)
1993467a64dSVinod Koul goto sst_load_base_firmware_failed;
2000bdd6d8bSVinod Koul }
201bf242d19SVinod Koul
202bf242d19SVinod Koul stripped_fw.data = ctx->fw->data;
203bf242d19SVinod Koul stripped_fw.size = ctx->fw->size;
204bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw);
205bf242d19SVinod Koul
2067d3f91dcSJeeja KP
2077d3f91dcSJeeja KP for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
208bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
2097d3f91dcSJeeja KP if (ret == 0)
2107d3f91dcSJeeja KP break;
2117d3f91dcSJeeja KP }
2127d3f91dcSJeeja KP
21392eb4f62SJeeja KP if (ret < 0) {
2142023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
2152023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
2162023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
2172023576dSSenthilnathan Veppur
21892eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
21992eb4f62SJeeja KP goto sst_load_base_firmware_failed;
22092eb4f62SJeeja KP }
22192eb4f62SJeeja KP
22292eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx);
22392eb4f62SJeeja KP if (ret < 0) {
22492eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
22592eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
22692eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
22792eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
22892eb4f62SJeeja KP
229052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
23092eb4f62SJeeja KP } else {
23192eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n");
23292eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
23392eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
23492eb4f62SJeeja KP if (ret == 0) {
23592eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
236052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
23792eb4f62SJeeja KP ret = -EIO;
23892eb4f62SJeeja KP } else {
23992eb4f62SJeeja KP ret = 0;
2401665c177SJayachandran B skl->fw_loaded = true;
24192eb4f62SJeeja KP }
24292eb4f62SJeeja KP }
24392eb4f62SJeeja KP
24431d648f0SJeeja KP return ret;
24531d648f0SJeeja KP
24692eb4f62SJeeja KP sst_load_base_firmware_failed:
247fdfa82eeSVinod Koul release_firmware(ctx->fw);
24831d648f0SJeeja KP ctx->fw = NULL;
24992eb4f62SJeeja KP return ret;
25092eb4f62SJeeja KP }
25192eb4f62SJeeja KP
2525bb4cd46SJayachandran B /*
2535bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase
2545bb4cd46SJayachandran B * ref counts and DSP state
2555bb4cd46SJayachandran B *
2565bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state)
2575bb4cd46SJayachandran B *
2585bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3
2595bb4cd46SJayachandran B *
2605bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies
2615bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
2625bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
2635bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
2645bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
2655bb4cd46SJayachandran B */
bxt_d0i3_target_state(struct sst_dsp * ctx)2665bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx)
2675bb4cd46SJayachandran B {
268bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
2695bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3;
2705bb4cd46SJayachandran B
2715bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
2725bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE;
2735bb4cd46SJayachandran B
2745bb4cd46SJayachandran B if (d0i3->non_d0i3)
2755bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE;
2765bb4cd46SJayachandran B else if (d0i3->streaming)
2775bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING;
2785bb4cd46SJayachandran B else if (d0i3->non_streaming)
2795bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING;
2805bb4cd46SJayachandran B else
2815bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE;
2825bb4cd46SJayachandran B }
2835bb4cd46SJayachandran B
bxt_set_dsp_D0i3(struct work_struct * work)2845bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work)
2855bb4cd46SJayachandran B {
2865bb4cd46SJayachandran B int ret;
2875bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg;
288bcc2a2dcSCezary Rojewski struct skl_dev *skl = container_of(work,
289bcc2a2dcSCezary Rojewski struct skl_dev, d0i3.work.work);
2905bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp;
2915bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3;
2925bb4cd46SJayachandran B int target_state;
2935bb4cd46SJayachandran B
2945bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__);
2955bb4cd46SJayachandran B
2965bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */
2975bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) {
2985bb4cd46SJayachandran B dev_warn(ctx->dev,
2995bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n");
3005bb4cd46SJayachandran B return;
3015bb4cd46SJayachandran B }
3025bb4cd46SJayachandran B
3035bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx);
3045bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE)
3055bb4cd46SJayachandran B return;
3065bb4cd46SJayachandran B
3075bb4cd46SJayachandran B msg.instance_id = 0;
3085bb4cd46SJayachandran B msg.module_id = 0;
3095bb4cd46SJayachandran B msg.wake = 1;
3105bb4cd46SJayachandran B msg.streaming = 0;
3115bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING)
3125bb4cd46SJayachandran B msg.streaming = 1;
3135bb4cd46SJayachandran B
3145bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
3155bb4cd46SJayachandran B
3165bb4cd46SJayachandran B if (ret < 0) {
3175bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
3185bb4cd46SJayachandran B return;
3195bb4cd46SJayachandran B }
3205bb4cd46SJayachandran B
3215bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/
3225bb4cd46SJayachandran B if (skl->update_d0i3c)
3235bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true);
3245bb4cd46SJayachandran B
3255bb4cd46SJayachandran B d0i3->state = target_state;
3265bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
3275bb4cd46SJayachandran B }
3285bb4cd46SJayachandran B
bxt_schedule_dsp_D0i3(struct sst_dsp * ctx)3295bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
3305bb4cd46SJayachandran B {
331bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
3325bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3;
3335bb4cd46SJayachandran B
3345bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */
3355bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
3365bb4cd46SJayachandran B
3375bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
3385bb4cd46SJayachandran B
3395bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work,
3405bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY));
3415bb4cd46SJayachandran B }
3425bb4cd46SJayachandran B
3435bb4cd46SJayachandran B return 0;
3445bb4cd46SJayachandran B }
3455bb4cd46SJayachandran B
bxt_set_dsp_D0i0(struct sst_dsp * ctx)3465bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
3475bb4cd46SJayachandran B {
3485bb4cd46SJayachandran B int ret;
3495bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg;
350bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
3515bb4cd46SJayachandran B
3525bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__);
3535bb4cd46SJayachandran B
3545bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */
3555bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work);
3565bb4cd46SJayachandran B
3575bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */
3585bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
3595bb4cd46SJayachandran B return 0;
3605bb4cd46SJayachandran B
3615bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n");
3625bb4cd46SJayachandran B
3635bb4cd46SJayachandran B msg.instance_id = 0;
3645bb4cd46SJayachandran B msg.module_id = 0;
3655bb4cd46SJayachandran B msg.streaming = 0;
3665bb4cd46SJayachandran B msg.wake = 0;
3675bb4cd46SJayachandran B
3685bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
3695bb4cd46SJayachandran B msg.streaming = 1;
3705bb4cd46SJayachandran B
3715bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
3725bb4cd46SJayachandran B if (skl->update_d0i3c)
3735bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false);
3745bb4cd46SJayachandran B
3755bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg);
3765bb4cd46SJayachandran B if (ret < 0) {
3775bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
3785bb4cd46SJayachandran B return ret;
3795bb4cd46SJayachandran B }
3805bb4cd46SJayachandran B
3815bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
3825bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE;
3835bb4cd46SJayachandran B
3845bb4cd46SJayachandran B return 0;
3855bb4cd46SJayachandran B }
3865bb4cd46SJayachandran B
bxt_set_dsp_D0(struct sst_dsp * ctx,unsigned int core_id)387052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
38892eb4f62SJeeja KP {
389bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
39092eb4f62SJeeja KP int ret;
391e68aca08SJayachandran B struct skl_ipc_dxstate_info dx;
392e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
39392eb4f62SJeeja KP
3941665c177SJayachandran B if (skl->fw_loaded == false) {
39592eb4f62SJeeja KP skl->boot_complete = false;
3961665c177SJayachandran B ret = bxt_load_base_firmware(ctx);
3971ef015e6SRamesh Babu if (ret < 0) {
3981665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret);
39992eb4f62SJeeja KP return ret;
40092eb4f62SJeeja KP }
40192eb4f62SJeeja KP
402eee0e16fSJeeja KP if (skl->lib_count > 1) {
403eee0e16fSJeeja KP ret = bxt_load_library(ctx, skl->lib_info,
404eee0e16fSJeeja KP skl->lib_count);
4051ef015e6SRamesh Babu if (ret < 0) {
4061ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret);
4071ef015e6SRamesh Babu return ret;
4081ef015e6SRamesh Babu }
4091ef015e6SRamesh Babu }
4101fb344a3SJeeja KP skl->cores.state[core_id] = SKL_DSP_RUNNING;
4111ef015e6SRamesh Babu return ret;
4121ef015e6SRamesh Babu }
4131ef015e6SRamesh Babu
414e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */
415e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID)
416e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask |
417e68aca08SJayachandran B SKL_DSP_CORE_MASK(1));
418e68aca08SJayachandran B else
419e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask);
42092eb4f62SJeeja KP
421e68aca08SJayachandran B if (ret < 0)
422e68aca08SJayachandran B goto err;
423e68aca08SJayachandran B
424e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) {
425e68aca08SJayachandran B
426e68aca08SJayachandran B /*
427e68aca08SJayachandran B * Enable interrupt after SPA is set and before
428e68aca08SJayachandran B * DSP is unstalled
429e68aca08SJayachandran B */
43092eb4f62SJeeja KP skl_ipc_int_enable(ctx);
43192eb4f62SJeeja KP skl_ipc_op_int_enable(ctx);
432e68aca08SJayachandran B skl->boot_complete = false;
433e68aca08SJayachandran B }
43492eb4f62SJeeja KP
435e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask);
436e68aca08SJayachandran B if (ret < 0)
437e68aca08SJayachandran B goto err;
438e68aca08SJayachandran B
439e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) {
440e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait,
441e68aca08SJayachandran B skl->boot_complete,
44292eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
443e68aca08SJayachandran B
444e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */
445e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
44692eb4f62SJeeja KP if (ret == 0) {
447e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
44892eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
44992eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
45092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
451e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
452e68aca08SJayachandran B ret = -EIO;
453e68aca08SJayachandran B goto err;
454e68aca08SJayachandran B }
45592eb4f62SJeeja KP }
45692eb4f62SJeeja KP
457e68aca08SJayachandran B /* Tell FW if additional core in now On */
458e68aca08SJayachandran B
459e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) {
460e68aca08SJayachandran B dx.core_mask = core_mask;
461e68aca08SJayachandran B dx.dx_mask = core_mask;
462e68aca08SJayachandran B
463e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
464e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx);
465e68aca08SJayachandran B if (ret < 0) {
466e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
467e68aca08SJayachandran B core_id, ret);
468e68aca08SJayachandran B goto err;
469e68aca08SJayachandran B }
470e68aca08SJayachandran B }
471e68aca08SJayachandran B
472e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING;
47392eb4f62SJeeja KP return 0;
474e68aca08SJayachandran B err:
475e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID)
476e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1);
477e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask);
478e68aca08SJayachandran B
479e68aca08SJayachandran B return ret;
48092eb4f62SJeeja KP }
48192eb4f62SJeeja KP
bxt_set_dsp_D3(struct sst_dsp * ctx,unsigned int core_id)482052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
48392eb4f62SJeeja KP {
484e68aca08SJayachandran B int ret;
48592eb4f62SJeeja KP struct skl_ipc_dxstate_info dx;
486bcc2a2dcSCezary Rojewski struct skl_dev *skl = ctx->thread_context;
487e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
48892eb4f62SJeeja KP
489e68aca08SJayachandran B dx.core_mask = core_mask;
49092eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK;
49192eb4f62SJeeja KP
492e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
493e68aca08SJayachandran B dx.core_mask, dx.dx_mask);
494e68aca08SJayachandran B
495e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
496e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx);
49703de8c2eSJeeja KP if (ret < 0) {
498e68aca08SJayachandran B dev_err(ctx->dev,
499e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n",
500e68aca08SJayachandran B core_id);
50103de8c2eSJeeja KP /*
50203de8c2eSJeeja KP * In case of D3 failure, re-download the firmware, so set
50303de8c2eSJeeja KP * fw_loaded to false.
50403de8c2eSJeeja KP */
50503de8c2eSJeeja KP skl->fw_loaded = false;
50603de8c2eSJeeja KP }
507e68aca08SJayachandran B
5085518af9fSJeeja KP if (core_id == SKL_DSP_CORE0_ID) {
5095518af9fSJeeja KP /* disable Interrupt */
5105518af9fSJeeja KP skl_ipc_op_int_disable(ctx);
5115518af9fSJeeja KP skl_ipc_int_disable(ctx);
5125518af9fSJeeja KP }
513e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask);
51492eb4f62SJeeja KP if (ret < 0) {
515ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret);
51692eb4f62SJeeja KP return ret;
51792eb4f62SJeeja KP }
518e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET;
51992eb4f62SJeeja KP return 0;
52092eb4f62SJeeja KP }
52192eb4f62SJeeja KP
5222788808aSBhumika Goyal static const struct skl_dsp_fw_ops bxt_fw_ops = {
52392eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0,
52492eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3,
5255bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3,
5265bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0,
52792eb4f62SJeeja KP .load_fw = bxt_load_base_firmware,
52892eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode,
5291ef015e6SRamesh Babu .load_library = bxt_load_library,
53092eb4f62SJeeja KP };
53192eb4f62SJeeja KP
53292eb4f62SJeeja KP static struct sst_ops skl_ops = {
53392eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt,
53492eb4f62SJeeja KP .write = sst_shim32_write,
53592eb4f62SJeeja KP .read = sst_shim32_read,
53692eb4f62SJeeja KP .free = skl_dsp_free,
53792eb4f62SJeeja KP };
53892eb4f62SJeeja KP
53992eb4f62SJeeja KP static struct sst_dsp_device skl_dev = {
54092eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler,
54192eb4f62SJeeja KP .ops = &skl_ops,
54292eb4f62SJeeja KP };
54392eb4f62SJeeja KP
bxt_sst_dsp_init(struct device * dev,void __iomem * mmio_base,int irq,const char * fw_name,struct skl_dsp_loader_ops dsp_ops,struct skl_dev ** dsp)54492eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
54592eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
546bcc2a2dcSCezary Rojewski struct skl_dev **dsp)
54792eb4f62SJeeja KP {
548bcc2a2dcSCezary Rojewski struct skl_dev *skl;
54992eb4f62SJeeja KP struct sst_dsp *sst;
55092eb4f62SJeeja KP int ret;
55192eb4f62SJeeja KP
5529fe9c711SG Kranthi ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
5539fe9c711SG Kranthi if (ret < 0) {
554351d74e4SArnd Bergmann dev_err(dev, "%s: no device\n", __func__);
5559fe9c711SG Kranthi return ret;
55692eb4f62SJeeja KP }
55792eb4f62SJeeja KP
5589fe9c711SG Kranthi skl = *dsp;
55992eb4f62SJeeja KP sst = skl->dsp;
56092eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops;
56192eb4f62SJeeja KP sst->addr.lpe = mmio_base;
56292eb4f62SJeeja KP sst->addr.shim = mmio_base;
56309e914d6SGuneshwor Singh sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
56409e914d6SGuneshwor Singh sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
56509e914d6SGuneshwor Singh sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
56609e914d6SGuneshwor Singh sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
56792eb4f62SJeeja KP
56892eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
56992eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
57092eb4f62SJeeja KP
5712eed1b02SGuneshwor Singh ret = skl_ipc_init(dev, skl);
5723b3011adSSubhransu S. Prusty if (ret) {
5733b3011adSSubhransu S. Prusty skl_dsp_free(sst);
5742eed1b02SGuneshwor Singh return ret;
5753b3011adSSubhransu S. Prusty }
5762eed1b02SGuneshwor Singh
577a83e3b4cSVinod Koul /* set the D0i3 check */
578a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
579a83e3b4cSVinod Koul
58092eb4f62SJeeja KP skl->boot_complete = false;
58192eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait);
582a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
583a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE;
58478cdbbdaSVinod Koul
5858e9d8e19SSubhransu S. Prusty return skl_dsp_acquire_irq(sst);
58678cdbbdaSVinod Koul }
58778cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
58878cdbbdaSVinod Koul
bxt_sst_init_fw(struct device * dev,struct skl_dev * skl)589bcc2a2dcSCezary Rojewski int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl)
59078cdbbdaSVinod Koul {
59178cdbbdaSVinod Koul int ret;
592bcc2a2dcSCezary Rojewski struct sst_dsp *sst = skl->dsp;
59392eb4f62SJeeja KP
59492eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst);
59592eb4f62SJeeja KP if (ret < 0) {
596ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret);
59792eb4f62SJeeja KP return ret;
59892eb4f62SJeeja KP }
59992eb4f62SJeeja KP
600052f103cSJayachandran B skl_dsp_init_core_state(sst);
601052f103cSJayachandran B
602bcc2a2dcSCezary Rojewski if (skl->lib_count > 1) {
603bcc2a2dcSCezary Rojewski ret = sst->fw_ops.load_library(sst, skl->lib_info,
604bcc2a2dcSCezary Rojewski skl->lib_count);
6051ef015e6SRamesh Babu if (ret < 0) {
606ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret);
6071ef015e6SRamesh Babu return ret;
6081ef015e6SRamesh Babu }
6091ef015e6SRamesh Babu }
610bcc2a2dcSCezary Rojewski skl->is_first_boot = false;
61192eb4f62SJeeja KP
61292eb4f62SJeeja KP return 0;
61392eb4f62SJeeja KP }
61478cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
61592eb4f62SJeeja KP
bxt_sst_dsp_cleanup(struct device * dev,struct skl_dev * skl)616bcc2a2dcSCezary Rojewski void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
61792eb4f62SJeeja KP {
61831d648f0SJeeja KP
619bcc2a2dcSCezary Rojewski skl_release_library(skl->lib_info, skl->lib_count);
620bcc2a2dcSCezary Rojewski if (skl->dsp->fw)
621bcc2a2dcSCezary Rojewski release_firmware(skl->dsp->fw);
622bcc2a2dcSCezary Rojewski skl_freeup_uuid_list(skl);
623bcc2a2dcSCezary Rojewski skl_ipc_free(&skl->ipc);
624bcc2a2dcSCezary Rojewski skl->dsp->ops->free(skl->dsp);
62592eb4f62SJeeja KP }
62692eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
62792eb4f62SJeeja KP
62892eb4f62SJeeja KP MODULE_LICENSE("GPL v2");
62992eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver");
630