192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 287d3f91dcSJeeja KP #define BXT_INIT_TIMEOUT 300 297d3f91dcSJeeja KP #define BXT_ROM_INIT_TIMEOUT 70 3092eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3192eb4f62SJeeja KP 3292eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3392eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3492eb4f62SJeeja KP 3592eb4f62SJeeja KP /* Firmware status window */ 3692eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3792eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3892eb4f62SJeeja KP 3992eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 4092eb4f62SJeeja KP 41e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 42e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 43e68aca08SJayachandran B 441ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 451ef015e6SRamesh Babu 465bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */ 475bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000 485bb4cd46SJayachandran B 497d3f91dcSJeeja KP #define BXT_FW_ROM_INIT_RETRY 3 507d3f91dcSJeeja KP 5192eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 5292eb4f62SJeeja KP { 5392eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 5492eb4f62SJeeja KP } 5592eb4f62SJeeja KP 5631d648f0SJeeja KP static void sst_bxt_release_library(struct skl_lib_info *linfo, int lib_count) 5731d648f0SJeeja KP { 5831d648f0SJeeja KP int i; 5931d648f0SJeeja KP 6031d648f0SJeeja KP for (i = 1; i < lib_count; i++) { 6131d648f0SJeeja KP if (linfo[i].fw) { 6231d648f0SJeeja KP release_firmware(linfo[i].fw); 6331d648f0SJeeja KP linfo[i].fw = NULL; 6431d648f0SJeeja KP } 6531d648f0SJeeja KP } 6631d648f0SJeeja KP } 6731d648f0SJeeja KP 681ef015e6SRamesh Babu static int 69eee0e16fSJeeja KP bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count) 701ef015e6SRamesh Babu { 711ef015e6SRamesh Babu struct snd_dma_buffer dmab; 721ef015e6SRamesh Babu struct skl_sst *skl = ctx->thread_context; 731ef015e6SRamesh Babu struct firmware stripped_fw; 741ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 751ef015e6SRamesh Babu 761ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 77eee0e16fSJeeja KP for (i = 1; i < lib_count; i++) { 7831d648f0SJeeja KP if (linfo[i].fw == NULL) { 7931d648f0SJeeja KP ret = request_firmware(&linfo[i].fw, linfo[i].name, 8031d648f0SJeeja KP ctx->dev); 811ef015e6SRamesh Babu if (ret < 0) { 821ef015e6SRamesh Babu dev_err(ctx->dev, "Request lib %s failed:%d\n", 83eee0e16fSJeeja KP linfo[i].name, ret); 8431d648f0SJeeja KP goto load_library_failed; 8531d648f0SJeeja KP } 861ef015e6SRamesh Babu } 871ef015e6SRamesh Babu 881ef015e6SRamesh Babu if (skl->is_first_boot) { 8931d648f0SJeeja KP ret = snd_skl_parse_uuids(ctx, linfo[i].fw, 901ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 911ef015e6SRamesh Babu if (ret < 0) 921ef015e6SRamesh Babu goto load_library_failed; 931ef015e6SRamesh Babu } 941ef015e6SRamesh Babu 9531d648f0SJeeja KP stripped_fw.data = linfo[i].fw->data; 9631d648f0SJeeja KP stripped_fw.size = linfo[i].fw->size; 971ef015e6SRamesh Babu skl_dsp_strip_extended_manifest(&stripped_fw); 981ef015e6SRamesh Babu 991ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 1001ef015e6SRamesh Babu stripped_fw.size, &dmab); 1011ef015e6SRamesh Babu if (stream_tag <= 0) { 1021ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 1031ef015e6SRamesh Babu stream_tag); 1041ef015e6SRamesh Babu ret = stream_tag; 1051ef015e6SRamesh Babu goto load_library_failed; 1061ef015e6SRamesh Babu } 1071ef015e6SRamesh Babu 1081ef015e6SRamesh Babu dma_id = stream_tag - 1; 1091ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 1101ef015e6SRamesh Babu 1111ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 1121ef015e6SRamesh Babu ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 1131ef015e6SRamesh Babu if (ret < 0) 1141ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 115eee0e16fSJeeja KP linfo[i].name, ret); 1161ef015e6SRamesh Babu 1171ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 1181ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 1191ef015e6SRamesh Babu } 1201ef015e6SRamesh Babu 1211ef015e6SRamesh Babu return ret; 1221ef015e6SRamesh Babu 1231ef015e6SRamesh Babu load_library_failed: 12431d648f0SJeeja KP sst_bxt_release_library(linfo, lib_count); 1251ef015e6SRamesh Babu return ret; 1261ef015e6SRamesh Babu } 1271ef015e6SRamesh Babu 128e68aca08SJayachandran B /* 129e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 130e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 131e68aca08SJayachandran B * reset/stall and then turn it off 132e68aca08SJayachandran B */ 13392eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 13492eb4f62SJeeja KP const void *fwdata, u32 fwsize) 13592eb4f62SJeeja KP { 136eee0e16fSJeeja KP int stream_tag, ret; 13792eb4f62SJeeja KP 13892eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 139e68aca08SJayachandran B if (stream_tag <= 0) { 14092eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 14192eb4f62SJeeja KP stream_tag); 14292eb4f62SJeeja KP return stream_tag; 14392eb4f62SJeeja KP } 14492eb4f62SJeeja KP 14592eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 14692eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 14792eb4f62SJeeja KP 148e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 149e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 150e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 15192eb4f62SJeeja KP if (ret < 0) { 152e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1532023576dSSenthilnathan Veppur goto base_fw_load_failed; 1542023576dSSenthilnathan Veppur } 1552023576dSSenthilnathan Veppur 156e68aca08SJayachandran B /* Step 2: Purge FW request */ 1572023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1582023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1592023576dSSenthilnathan Veppur 160e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 161052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1622023576dSSenthilnathan Veppur if (ret < 0) { 1632023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 16492eb4f62SJeeja KP ret = -EIO; 16592eb4f62SJeeja KP goto base_fw_load_failed; 16692eb4f62SJeeja KP } 16792eb4f62SJeeja KP 168e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 1691448099dSJeeja KP ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE, 17092eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 17192eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 1721448099dSJeeja KP BXT_INIT_TIMEOUT, "HIPCIE Done"); 1731448099dSJeeja KP if (ret < 0) { 1745f75b19eSColin Ian King dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret); 1751448099dSJeeja KP goto base_fw_load_failed; 17692eb4f62SJeeja KP } 17792eb4f62SJeeja KP 178e68aca08SJayachandran B /* Step 5: power down core1 */ 179e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 180e68aca08SJayachandran B if (ret < 0) { 181e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 182e68aca08SJayachandran B goto base_fw_load_failed; 183e68aca08SJayachandran B } 184e68aca08SJayachandran B 185e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 18692eb4f62SJeeja KP skl_ipc_int_enable(ctx); 18792eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 18892eb4f62SJeeja KP 189e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 1901448099dSJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 1917d3f91dcSJeeja KP SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load"); 1921448099dSJeeja KP if (ret < 0) { 1931448099dSJeeja KP dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret); 19492eb4f62SJeeja KP goto base_fw_load_failed; 19592eb4f62SJeeja KP } 19692eb4f62SJeeja KP 19792eb4f62SJeeja KP return ret; 19892eb4f62SJeeja KP 19992eb4f62SJeeja KP base_fw_load_failed: 20092eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 201052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 202c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 20392eb4f62SJeeja KP return ret; 20492eb4f62SJeeja KP } 20592eb4f62SJeeja KP 20692eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 20792eb4f62SJeeja KP { 20892eb4f62SJeeja KP int ret; 20992eb4f62SJeeja KP 21092eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 21192eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 21292eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 21392eb4f62SJeeja KP 21492eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 21592eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 21692eb4f62SJeeja KP 21792eb4f62SJeeja KP return ret; 21892eb4f62SJeeja KP } 21992eb4f62SJeeja KP 22092eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 22192eb4f62SJeeja KP { 222bf242d19SVinod Koul struct firmware stripped_fw; 22392eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 2247d3f91dcSJeeja KP int ret, i; 22592eb4f62SJeeja KP 22631d648f0SJeeja KP if (ctx->fw == NULL) { 227fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 22892eb4f62SJeeja KP if (ret < 0) { 22992eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 23031d648f0SJeeja KP return ret; 23192eb4f62SJeeja KP } 23231d648f0SJeeja KP } 233bf242d19SVinod Koul 2340bdd6d8bSVinod Koul /* prase uuids on first boot */ 2350bdd6d8bSVinod Koul if (skl->is_first_boot) { 236a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2373467a64dSVinod Koul if (ret < 0) 2383467a64dSVinod Koul goto sst_load_base_firmware_failed; 2390bdd6d8bSVinod Koul } 240bf242d19SVinod Koul 241bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 242bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 243bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 244bf242d19SVinod Koul 2457d3f91dcSJeeja KP 2467d3f91dcSJeeja KP for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) { 247bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 2487d3f91dcSJeeja KP if (ret == 0) 2497d3f91dcSJeeja KP break; 2507d3f91dcSJeeja KP } 2517d3f91dcSJeeja KP 25292eb4f62SJeeja KP if (ret < 0) { 2532023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2542023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2552023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2562023576dSSenthilnathan Veppur 25792eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 25892eb4f62SJeeja KP goto sst_load_base_firmware_failed; 25992eb4f62SJeeja KP } 26092eb4f62SJeeja KP 26192eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 26292eb4f62SJeeja KP if (ret < 0) { 26392eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 26492eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 26592eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 26692eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 26792eb4f62SJeeja KP 268052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 26992eb4f62SJeeja KP } else { 27092eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 27192eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 27292eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 27392eb4f62SJeeja KP if (ret == 0) { 27492eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 275052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 27692eb4f62SJeeja KP ret = -EIO; 27792eb4f62SJeeja KP } else { 27892eb4f62SJeeja KP ret = 0; 2791665c177SJayachandran B skl->fw_loaded = true; 28092eb4f62SJeeja KP } 28192eb4f62SJeeja KP } 28292eb4f62SJeeja KP 28331d648f0SJeeja KP return ret; 28431d648f0SJeeja KP 28592eb4f62SJeeja KP sst_load_base_firmware_failed: 286fdfa82eeSVinod Koul release_firmware(ctx->fw); 28731d648f0SJeeja KP ctx->fw = NULL; 28892eb4f62SJeeja KP return ret; 28992eb4f62SJeeja KP } 29092eb4f62SJeeja KP 2915bb4cd46SJayachandran B /* 2925bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase 2935bb4cd46SJayachandran B * ref counts and DSP state 2945bb4cd46SJayachandran B * 2955bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state) 2965bb4cd46SJayachandran B * 2975bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3 2985bb4cd46SJayachandran B * 2995bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies 3005bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 3015bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 3025bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 3035bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 3045bb4cd46SJayachandran B */ 3055bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx) 3065bb4cd46SJayachandran B { 3075bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3085bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3095bb4cd46SJayachandran B 3105bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 3115bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3125bb4cd46SJayachandran B 3135bb4cd46SJayachandran B if (d0i3->non_d0i3) 3145bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3155bb4cd46SJayachandran B else if (d0i3->streaming) 3165bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING; 3175bb4cd46SJayachandran B else if (d0i3->non_streaming) 3185bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING; 3195bb4cd46SJayachandran B else 3205bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3215bb4cd46SJayachandran B } 3225bb4cd46SJayachandran B 3235bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work) 3245bb4cd46SJayachandran B { 3255bb4cd46SJayachandran B int ret; 3265bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3275bb4cd46SJayachandran B struct skl_sst *skl = container_of(work, 3285bb4cd46SJayachandran B struct skl_sst, d0i3.work.work); 3295bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp; 3305bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3315bb4cd46SJayachandran B int target_state; 3325bb4cd46SJayachandran B 3335bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3345bb4cd46SJayachandran B 3355bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */ 3365bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 3375bb4cd46SJayachandran B dev_warn(ctx->dev, 3385bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n"); 3395bb4cd46SJayachandran B return; 3405bb4cd46SJayachandran B } 3415bb4cd46SJayachandran B 3425bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx); 3435bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE) 3445bb4cd46SJayachandran B return; 3455bb4cd46SJayachandran B 3465bb4cd46SJayachandran B msg.instance_id = 0; 3475bb4cd46SJayachandran B msg.module_id = 0; 3485bb4cd46SJayachandran B msg.wake = 1; 3495bb4cd46SJayachandran B msg.streaming = 0; 3505bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING) 3515bb4cd46SJayachandran B msg.streaming = 1; 3525bb4cd46SJayachandran B 3535bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3545bb4cd46SJayachandran B 3555bb4cd46SJayachandran B if (ret < 0) { 3565bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 3575bb4cd46SJayachandran B return; 3585bb4cd46SJayachandran B } 3595bb4cd46SJayachandran B 3605bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 3615bb4cd46SJayachandran B if (skl->update_d0i3c) 3625bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true); 3635bb4cd46SJayachandran B 3645bb4cd46SJayachandran B d0i3->state = target_state; 3655bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 3665bb4cd46SJayachandran B } 3675bb4cd46SJayachandran B 3685bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 3695bb4cd46SJayachandran B { 3705bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3715bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3725bb4cd46SJayachandran B 3735bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */ 3745bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 3755bb4cd46SJayachandran B 3765bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 3775bb4cd46SJayachandran B 3785bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work, 3795bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY)); 3805bb4cd46SJayachandran B } 3815bb4cd46SJayachandran B 3825bb4cd46SJayachandran B return 0; 3835bb4cd46SJayachandran B } 3845bb4cd46SJayachandran B 3855bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 3865bb4cd46SJayachandran B { 3875bb4cd46SJayachandran B int ret; 3885bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3895bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3905bb4cd46SJayachandran B 3915bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3925bb4cd46SJayachandran B 3935bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */ 3945bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work); 3955bb4cd46SJayachandran B 3965bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */ 3975bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 3985bb4cd46SJayachandran B return 0; 3995bb4cd46SJayachandran B 4005bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 4015bb4cd46SJayachandran B 4025bb4cd46SJayachandran B msg.instance_id = 0; 4035bb4cd46SJayachandran B msg.module_id = 0; 4045bb4cd46SJayachandran B msg.streaming = 0; 4055bb4cd46SJayachandran B msg.wake = 0; 4065bb4cd46SJayachandran B 4075bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 4085bb4cd46SJayachandran B msg.streaming = 1; 4095bb4cd46SJayachandran B 4105bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 4115bb4cd46SJayachandran B if (skl->update_d0i3c) 4125bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false); 4135bb4cd46SJayachandran B 4145bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 4155bb4cd46SJayachandran B if (ret < 0) { 4165bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 4175bb4cd46SJayachandran B return ret; 4185bb4cd46SJayachandran B } 4195bb4cd46SJayachandran B 4205bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 4215bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE; 4225bb4cd46SJayachandran B 4235bb4cd46SJayachandran B return 0; 4245bb4cd46SJayachandran B } 4255bb4cd46SJayachandran B 426052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 42792eb4f62SJeeja KP { 42892eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 42992eb4f62SJeeja KP int ret; 430e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 431e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 43292eb4f62SJeeja KP 4331665c177SJayachandran B if (skl->fw_loaded == false) { 43492eb4f62SJeeja KP skl->boot_complete = false; 4351665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 4361ef015e6SRamesh Babu if (ret < 0) { 4371665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 43892eb4f62SJeeja KP return ret; 43992eb4f62SJeeja KP } 44092eb4f62SJeeja KP 441eee0e16fSJeeja KP if (skl->lib_count > 1) { 442eee0e16fSJeeja KP ret = bxt_load_library(ctx, skl->lib_info, 443eee0e16fSJeeja KP skl->lib_count); 4441ef015e6SRamesh Babu if (ret < 0) { 4451ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 4461ef015e6SRamesh Babu return ret; 4471ef015e6SRamesh Babu } 4481ef015e6SRamesh Babu } 4491fb344a3SJeeja KP skl->cores.state[core_id] = SKL_DSP_RUNNING; 4501ef015e6SRamesh Babu return ret; 4511ef015e6SRamesh Babu } 4521ef015e6SRamesh Babu 453e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 454e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 455e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 456e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 457e68aca08SJayachandran B else 458e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 45992eb4f62SJeeja KP 460e68aca08SJayachandran B if (ret < 0) 461e68aca08SJayachandran B goto err; 462e68aca08SJayachandran B 463e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 464e68aca08SJayachandran B 465e68aca08SJayachandran B /* 466e68aca08SJayachandran B * Enable interrupt after SPA is set and before 467e68aca08SJayachandran B * DSP is unstalled 468e68aca08SJayachandran B */ 46992eb4f62SJeeja KP skl_ipc_int_enable(ctx); 47092eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 471e68aca08SJayachandran B skl->boot_complete = false; 472e68aca08SJayachandran B } 47392eb4f62SJeeja KP 474e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 475e68aca08SJayachandran B if (ret < 0) 476e68aca08SJayachandran B goto err; 477e68aca08SJayachandran B 478e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 479e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 480e68aca08SJayachandran B skl->boot_complete, 48192eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 482e68aca08SJayachandran B 483e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 484e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 48592eb4f62SJeeja KP if (ret == 0) { 486e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 48792eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 48892eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 48992eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 490e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 491e68aca08SJayachandran B ret = -EIO; 492e68aca08SJayachandran B goto err; 493e68aca08SJayachandran B } 49492eb4f62SJeeja KP } 49592eb4f62SJeeja KP 496e68aca08SJayachandran B /* Tell FW if additional core in now On */ 497e68aca08SJayachandran B 498e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 499e68aca08SJayachandran B dx.core_mask = core_mask; 500e68aca08SJayachandran B dx.dx_mask = core_mask; 501e68aca08SJayachandran B 502e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 503e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 504e68aca08SJayachandran B if (ret < 0) { 505e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 506e68aca08SJayachandran B core_id, ret); 507e68aca08SJayachandran B goto err; 508e68aca08SJayachandran B } 509e68aca08SJayachandran B } 510e68aca08SJayachandran B 511e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 51292eb4f62SJeeja KP return 0; 513e68aca08SJayachandran B err: 514e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 515e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 516e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 517e68aca08SJayachandran B 518e68aca08SJayachandran B return ret; 51992eb4f62SJeeja KP } 52092eb4f62SJeeja KP 521052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 52292eb4f62SJeeja KP { 523e68aca08SJayachandran B int ret; 52492eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 52592eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 526e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 52792eb4f62SJeeja KP 528e68aca08SJayachandran B dx.core_mask = core_mask; 52992eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 53092eb4f62SJeeja KP 531e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 532e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 533e68aca08SJayachandran B 534e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 535e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 53603de8c2eSJeeja KP if (ret < 0) { 537e68aca08SJayachandran B dev_err(ctx->dev, 538e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 539e68aca08SJayachandran B core_id); 54003de8c2eSJeeja KP /* 54103de8c2eSJeeja KP * In case of D3 failure, re-download the firmware, so set 54203de8c2eSJeeja KP * fw_loaded to false. 54303de8c2eSJeeja KP */ 54403de8c2eSJeeja KP skl->fw_loaded = false; 54503de8c2eSJeeja KP } 546e68aca08SJayachandran B 5475518af9fSJeeja KP if (core_id == SKL_DSP_CORE0_ID) { 5485518af9fSJeeja KP /* disable Interrupt */ 5495518af9fSJeeja KP skl_ipc_op_int_disable(ctx); 5505518af9fSJeeja KP skl_ipc_int_disable(ctx); 5515518af9fSJeeja KP } 552e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 55392eb4f62SJeeja KP if (ret < 0) { 554ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 55592eb4f62SJeeja KP return ret; 55692eb4f62SJeeja KP } 557e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 55892eb4f62SJeeja KP return 0; 55992eb4f62SJeeja KP } 56092eb4f62SJeeja KP 56192eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 56292eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 56392eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 5645bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3, 5655bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0, 56692eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 56792eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 5681ef015e6SRamesh Babu .load_library = bxt_load_library, 56992eb4f62SJeeja KP }; 57092eb4f62SJeeja KP 57192eb4f62SJeeja KP static struct sst_ops skl_ops = { 57292eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 57392eb4f62SJeeja KP .write = sst_shim32_write, 57492eb4f62SJeeja KP .read = sst_shim32_read, 57592eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 57692eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 57792eb4f62SJeeja KP .free = skl_dsp_free, 57892eb4f62SJeeja KP }; 57992eb4f62SJeeja KP 58092eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 58192eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 58292eb4f62SJeeja KP .ops = &skl_ops, 58392eb4f62SJeeja KP }; 58492eb4f62SJeeja KP 58592eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 58692eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 58792eb4f62SJeeja KP struct skl_sst **dsp) 58892eb4f62SJeeja KP { 58992eb4f62SJeeja KP struct skl_sst *skl; 59092eb4f62SJeeja KP struct sst_dsp *sst; 59192eb4f62SJeeja KP int ret; 59292eb4f62SJeeja KP 5939fe9c711SG Kranthi ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev); 5949fe9c711SG Kranthi if (ret < 0) { 5959fe9c711SG Kranthi dev_err(skl->dev, "%s: no device\n", __func__); 5969fe9c711SG Kranthi return ret; 59792eb4f62SJeeja KP } 59892eb4f62SJeeja KP 5999fe9c711SG Kranthi skl = *dsp; 60092eb4f62SJeeja KP sst = skl->dsp; 60192eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 60292eb4f62SJeeja KP sst->addr.lpe = mmio_base; 60392eb4f62SJeeja KP sst->addr.shim = mmio_base; 60492eb4f62SJeeja KP 60592eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 60692eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 60792eb4f62SJeeja KP 608a83e3b4cSVinod Koul /* set the D0i3 check */ 609a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 610a83e3b4cSVinod Koul 611052f103cSJayachandran B skl->cores.count = 2; 61292eb4f62SJeeja KP skl->boot_complete = false; 61392eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 614a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 615a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE; 61678cdbbdaSVinod Koul 61778cdbbdaSVinod Koul return 0; 61878cdbbdaSVinod Koul } 61978cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 62078cdbbdaSVinod Koul 62178cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 62278cdbbdaSVinod Koul { 62378cdbbdaSVinod Koul int ret; 62478cdbbdaSVinod Koul struct sst_dsp *sst = ctx->dsp; 62592eb4f62SJeeja KP 62692eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 62792eb4f62SJeeja KP if (ret < 0) { 628ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 62992eb4f62SJeeja KP return ret; 63092eb4f62SJeeja KP } 63192eb4f62SJeeja KP 632052f103cSJayachandran B skl_dsp_init_core_state(sst); 633052f103cSJayachandran B 634eee0e16fSJeeja KP if (ctx->lib_count > 1) { 635eee0e16fSJeeja KP ret = sst->fw_ops.load_library(sst, ctx->lib_info, 636eee0e16fSJeeja KP ctx->lib_count); 6371ef015e6SRamesh Babu if (ret < 0) { 638ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 6391ef015e6SRamesh Babu return ret; 6401ef015e6SRamesh Babu } 6411ef015e6SRamesh Babu } 64278cdbbdaSVinod Koul ctx->is_first_boot = false; 64392eb4f62SJeeja KP 64492eb4f62SJeeja KP return 0; 64592eb4f62SJeeja KP } 64678cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 64792eb4f62SJeeja KP 64892eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 64992eb4f62SJeeja KP { 65031d648f0SJeeja KP 65131d648f0SJeeja KP sst_bxt_release_library(ctx->lib_info, ctx->lib_count); 65231d648f0SJeeja KP if (ctx->dsp->fw) 65331d648f0SJeeja KP release_firmware(ctx->dsp->fw); 6543467a64dSVinod Koul skl_freeup_uuid_list(ctx); 65592eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 65692eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 65792eb4f62SJeeja KP 65892eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 65992eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 66092eb4f62SJeeja KP 66192eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 66292eb4f62SJeeja KP } 66392eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 66492eb4f62SJeeja KP 66592eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 66692eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 667