192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 2892eb4f62SJeeja KP #define BXT_INIT_TIMEOUT 500 2992eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3092eb4f62SJeeja KP 3192eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3292eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3392eb4f62SJeeja KP 3492eb4f62SJeeja KP /* Firmware status window */ 3592eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3692eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3792eb4f62SJeeja KP 3892eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 3992eb4f62SJeeja KP 40e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 41e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 42e68aca08SJayachandran B 431ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 441ef015e6SRamesh Babu 455bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */ 465bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000 475bb4cd46SJayachandran B 4892eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 4992eb4f62SJeeja KP { 5092eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 5192eb4f62SJeeja KP } 5292eb4f62SJeeja KP 5331d648f0SJeeja KP static void sst_bxt_release_library(struct skl_lib_info *linfo, int lib_count) 5431d648f0SJeeja KP { 5531d648f0SJeeja KP int i; 5631d648f0SJeeja KP 5731d648f0SJeeja KP for (i = 1; i < lib_count; i++) { 5831d648f0SJeeja KP if (linfo[i].fw) { 5931d648f0SJeeja KP release_firmware(linfo[i].fw); 6031d648f0SJeeja KP linfo[i].fw = NULL; 6131d648f0SJeeja KP } 6231d648f0SJeeja KP } 6331d648f0SJeeja KP } 6431d648f0SJeeja KP 651ef015e6SRamesh Babu static int 66eee0e16fSJeeja KP bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count) 671ef015e6SRamesh Babu { 681ef015e6SRamesh Babu struct snd_dma_buffer dmab; 691ef015e6SRamesh Babu struct skl_sst *skl = ctx->thread_context; 701ef015e6SRamesh Babu struct firmware stripped_fw; 711ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 721ef015e6SRamesh Babu 731ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 74eee0e16fSJeeja KP for (i = 1; i < lib_count; i++) { 7531d648f0SJeeja KP if (linfo[i].fw == NULL) { 7631d648f0SJeeja KP ret = request_firmware(&linfo[i].fw, linfo[i].name, 7731d648f0SJeeja KP ctx->dev); 781ef015e6SRamesh Babu if (ret < 0) { 791ef015e6SRamesh Babu dev_err(ctx->dev, "Request lib %s failed:%d\n", 80eee0e16fSJeeja KP linfo[i].name, ret); 8131d648f0SJeeja KP goto load_library_failed; 8231d648f0SJeeja KP } 831ef015e6SRamesh Babu } 841ef015e6SRamesh Babu 851ef015e6SRamesh Babu if (skl->is_first_boot) { 8631d648f0SJeeja KP ret = snd_skl_parse_uuids(ctx, linfo[i].fw, 871ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 881ef015e6SRamesh Babu if (ret < 0) 891ef015e6SRamesh Babu goto load_library_failed; 901ef015e6SRamesh Babu } 911ef015e6SRamesh Babu 9231d648f0SJeeja KP stripped_fw.data = linfo[i].fw->data; 9331d648f0SJeeja KP stripped_fw.size = linfo[i].fw->size; 941ef015e6SRamesh Babu skl_dsp_strip_extended_manifest(&stripped_fw); 951ef015e6SRamesh Babu 961ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 971ef015e6SRamesh Babu stripped_fw.size, &dmab); 981ef015e6SRamesh Babu if (stream_tag <= 0) { 991ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 1001ef015e6SRamesh Babu stream_tag); 1011ef015e6SRamesh Babu ret = stream_tag; 1021ef015e6SRamesh Babu goto load_library_failed; 1031ef015e6SRamesh Babu } 1041ef015e6SRamesh Babu 1051ef015e6SRamesh Babu dma_id = stream_tag - 1; 1061ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 1071ef015e6SRamesh Babu 1081ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 1091ef015e6SRamesh Babu ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 1101ef015e6SRamesh Babu if (ret < 0) 1111ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 112eee0e16fSJeeja KP linfo[i].name, ret); 1131ef015e6SRamesh Babu 1141ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 1151ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 1161ef015e6SRamesh Babu } 1171ef015e6SRamesh Babu 1181ef015e6SRamesh Babu return ret; 1191ef015e6SRamesh Babu 1201ef015e6SRamesh Babu load_library_failed: 12131d648f0SJeeja KP sst_bxt_release_library(linfo, lib_count); 1221ef015e6SRamesh Babu return ret; 1231ef015e6SRamesh Babu } 1241ef015e6SRamesh Babu 125e68aca08SJayachandran B /* 126e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 127e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 128e68aca08SJayachandran B * reset/stall and then turn it off 129e68aca08SJayachandran B */ 13092eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 13192eb4f62SJeeja KP const void *fwdata, u32 fwsize) 13292eb4f62SJeeja KP { 133eee0e16fSJeeja KP int stream_tag, ret; 13492eb4f62SJeeja KP 13592eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 136e68aca08SJayachandran B if (stream_tag <= 0) { 13792eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 13892eb4f62SJeeja KP stream_tag); 13992eb4f62SJeeja KP return stream_tag; 14092eb4f62SJeeja KP } 14192eb4f62SJeeja KP 14292eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 14392eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 14492eb4f62SJeeja KP 145e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 146e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 147e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 14892eb4f62SJeeja KP if (ret < 0) { 149e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1502023576dSSenthilnathan Veppur goto base_fw_load_failed; 1512023576dSSenthilnathan Veppur } 1522023576dSSenthilnathan Veppur 153e68aca08SJayachandran B /* Step 2: Purge FW request */ 1542023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1552023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1562023576dSSenthilnathan Veppur 157e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 158052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1592023576dSSenthilnathan Veppur if (ret < 0) { 1602023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 16192eb4f62SJeeja KP ret = -EIO; 16292eb4f62SJeeja KP goto base_fw_load_failed; 16392eb4f62SJeeja KP } 16492eb4f62SJeeja KP 165e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 1661448099dSJeeja KP ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE, 16792eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 16892eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 1691448099dSJeeja KP BXT_INIT_TIMEOUT, "HIPCIE Done"); 1701448099dSJeeja KP if (ret < 0) { 1711448099dSJeeja KP dev_err(ctx->dev, "Timout for Purge Request%d\n", ret); 1721448099dSJeeja KP goto base_fw_load_failed; 17392eb4f62SJeeja KP } 17492eb4f62SJeeja KP 175e68aca08SJayachandran B /* Step 5: power down core1 */ 176e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 177e68aca08SJayachandran B if (ret < 0) { 178e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 179e68aca08SJayachandran B goto base_fw_load_failed; 180e68aca08SJayachandran B } 181e68aca08SJayachandran B 182e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 18392eb4f62SJeeja KP skl_ipc_int_enable(ctx); 18492eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 18592eb4f62SJeeja KP 186e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 1871448099dSJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 1881448099dSJeeja KP SKL_FW_INIT, BXT_INIT_TIMEOUT, "ROM Load"); 1891448099dSJeeja KP if (ret < 0) { 1901448099dSJeeja KP dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret); 19192eb4f62SJeeja KP goto base_fw_load_failed; 19292eb4f62SJeeja KP } 19392eb4f62SJeeja KP 19492eb4f62SJeeja KP return ret; 19592eb4f62SJeeja KP 19692eb4f62SJeeja KP base_fw_load_failed: 19792eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 198052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 199c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 20092eb4f62SJeeja KP return ret; 20192eb4f62SJeeja KP } 20292eb4f62SJeeja KP 20392eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 20492eb4f62SJeeja KP { 20592eb4f62SJeeja KP int ret; 20692eb4f62SJeeja KP 20792eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 20892eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 20992eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 21092eb4f62SJeeja KP 21192eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 21292eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 21392eb4f62SJeeja KP 21492eb4f62SJeeja KP return ret; 21592eb4f62SJeeja KP } 21692eb4f62SJeeja KP 21792eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 21892eb4f62SJeeja KP { 219bf242d19SVinod Koul struct firmware stripped_fw; 22092eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 22192eb4f62SJeeja KP int ret; 22292eb4f62SJeeja KP 22331d648f0SJeeja KP if (ctx->fw == NULL) { 224fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 22592eb4f62SJeeja KP if (ret < 0) { 22692eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 22731d648f0SJeeja KP return ret; 22892eb4f62SJeeja KP } 22931d648f0SJeeja KP } 230bf242d19SVinod Koul 2310bdd6d8bSVinod Koul /* prase uuids on first boot */ 2320bdd6d8bSVinod Koul if (skl->is_first_boot) { 233a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2343467a64dSVinod Koul if (ret < 0) 2353467a64dSVinod Koul goto sst_load_base_firmware_failed; 2360bdd6d8bSVinod Koul } 237bf242d19SVinod Koul 238bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 239bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 240bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 241bf242d19SVinod Koul 242bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 24392eb4f62SJeeja KP /* Retry Enabling core and ROM load. Retry seemed to help */ 24492eb4f62SJeeja KP if (ret < 0) { 245bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 24692eb4f62SJeeja KP if (ret < 0) { 2472023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2482023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2492023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2502023576dSSenthilnathan Veppur 25192eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 25292eb4f62SJeeja KP goto sst_load_base_firmware_failed; 25392eb4f62SJeeja KP } 25492eb4f62SJeeja KP } 25592eb4f62SJeeja KP 25692eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 25792eb4f62SJeeja KP if (ret < 0) { 25892eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 25992eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 26092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 26192eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 26292eb4f62SJeeja KP 263052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 26492eb4f62SJeeja KP } else { 26592eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 26692eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 26792eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 26892eb4f62SJeeja KP if (ret == 0) { 26992eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 270052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 27192eb4f62SJeeja KP ret = -EIO; 27292eb4f62SJeeja KP } else { 27392eb4f62SJeeja KP ret = 0; 2741665c177SJayachandran B skl->fw_loaded = true; 27592eb4f62SJeeja KP } 27692eb4f62SJeeja KP } 27792eb4f62SJeeja KP 27831d648f0SJeeja KP return ret; 27931d648f0SJeeja KP 28092eb4f62SJeeja KP sst_load_base_firmware_failed: 281fdfa82eeSVinod Koul release_firmware(ctx->fw); 28231d648f0SJeeja KP ctx->fw = NULL; 28392eb4f62SJeeja KP return ret; 28492eb4f62SJeeja KP } 28592eb4f62SJeeja KP 2865bb4cd46SJayachandran B /* 2875bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase 2885bb4cd46SJayachandran B * ref counts and DSP state 2895bb4cd46SJayachandran B * 2905bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state) 2915bb4cd46SJayachandran B * 2925bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3 2935bb4cd46SJayachandran B * 2945bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies 2955bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 2965bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 2975bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 2985bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 2995bb4cd46SJayachandran B */ 3005bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx) 3015bb4cd46SJayachandran B { 3025bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3035bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3045bb4cd46SJayachandran B 3055bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 3065bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3075bb4cd46SJayachandran B 3085bb4cd46SJayachandran B if (d0i3->non_d0i3) 3095bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3105bb4cd46SJayachandran B else if (d0i3->streaming) 3115bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING; 3125bb4cd46SJayachandran B else if (d0i3->non_streaming) 3135bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING; 3145bb4cd46SJayachandran B else 3155bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3165bb4cd46SJayachandran B } 3175bb4cd46SJayachandran B 3185bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work) 3195bb4cd46SJayachandran B { 3205bb4cd46SJayachandran B int ret; 3215bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3225bb4cd46SJayachandran B struct skl_sst *skl = container_of(work, 3235bb4cd46SJayachandran B struct skl_sst, d0i3.work.work); 3245bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp; 3255bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3265bb4cd46SJayachandran B int target_state; 3275bb4cd46SJayachandran B 3285bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3295bb4cd46SJayachandran B 3305bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */ 3315bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 3325bb4cd46SJayachandran B dev_warn(ctx->dev, 3335bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n"); 3345bb4cd46SJayachandran B return; 3355bb4cd46SJayachandran B } 3365bb4cd46SJayachandran B 3375bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx); 3385bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE) 3395bb4cd46SJayachandran B return; 3405bb4cd46SJayachandran B 3415bb4cd46SJayachandran B msg.instance_id = 0; 3425bb4cd46SJayachandran B msg.module_id = 0; 3435bb4cd46SJayachandran B msg.wake = 1; 3445bb4cd46SJayachandran B msg.streaming = 0; 3455bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING) 3465bb4cd46SJayachandran B msg.streaming = 1; 3475bb4cd46SJayachandran B 3485bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3495bb4cd46SJayachandran B 3505bb4cd46SJayachandran B if (ret < 0) { 3515bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 3525bb4cd46SJayachandran B return; 3535bb4cd46SJayachandran B } 3545bb4cd46SJayachandran B 3555bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 3565bb4cd46SJayachandran B if (skl->update_d0i3c) 3575bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true); 3585bb4cd46SJayachandran B 3595bb4cd46SJayachandran B d0i3->state = target_state; 3605bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 3615bb4cd46SJayachandran B } 3625bb4cd46SJayachandran B 3635bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 3645bb4cd46SJayachandran B { 3655bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3665bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3675bb4cd46SJayachandran B 3685bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */ 3695bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 3705bb4cd46SJayachandran B 3715bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 3725bb4cd46SJayachandran B 3735bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work, 3745bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY)); 3755bb4cd46SJayachandran B } 3765bb4cd46SJayachandran B 3775bb4cd46SJayachandran B return 0; 3785bb4cd46SJayachandran B } 3795bb4cd46SJayachandran B 3805bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 3815bb4cd46SJayachandran B { 3825bb4cd46SJayachandran B int ret; 3835bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3845bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3855bb4cd46SJayachandran B 3865bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3875bb4cd46SJayachandran B 3885bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */ 3895bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work); 3905bb4cd46SJayachandran B 3915bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */ 3925bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 3935bb4cd46SJayachandran B return 0; 3945bb4cd46SJayachandran B 3955bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 3965bb4cd46SJayachandran B 3975bb4cd46SJayachandran B msg.instance_id = 0; 3985bb4cd46SJayachandran B msg.module_id = 0; 3995bb4cd46SJayachandran B msg.streaming = 0; 4005bb4cd46SJayachandran B msg.wake = 0; 4015bb4cd46SJayachandran B 4025bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 4035bb4cd46SJayachandran B msg.streaming = 1; 4045bb4cd46SJayachandran B 4055bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 4065bb4cd46SJayachandran B if (skl->update_d0i3c) 4075bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false); 4085bb4cd46SJayachandran B 4095bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 4105bb4cd46SJayachandran B if (ret < 0) { 4115bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 4125bb4cd46SJayachandran B return ret; 4135bb4cd46SJayachandran B } 4145bb4cd46SJayachandran B 4155bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 4165bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE; 4175bb4cd46SJayachandran B 4185bb4cd46SJayachandran B return 0; 4195bb4cd46SJayachandran B } 4205bb4cd46SJayachandran B 421052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 42292eb4f62SJeeja KP { 42392eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 42492eb4f62SJeeja KP int ret; 425e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 426e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 42792eb4f62SJeeja KP 4281665c177SJayachandran B if (skl->fw_loaded == false) { 42992eb4f62SJeeja KP skl->boot_complete = false; 4301665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 4311ef015e6SRamesh Babu if (ret < 0) { 4321665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 43392eb4f62SJeeja KP return ret; 43492eb4f62SJeeja KP } 43592eb4f62SJeeja KP 436eee0e16fSJeeja KP if (skl->lib_count > 1) { 437eee0e16fSJeeja KP ret = bxt_load_library(ctx, skl->lib_info, 438eee0e16fSJeeja KP skl->lib_count); 4391ef015e6SRamesh Babu if (ret < 0) { 4401ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 4411ef015e6SRamesh Babu return ret; 4421ef015e6SRamesh Babu } 4431ef015e6SRamesh Babu } 4441ef015e6SRamesh Babu return ret; 4451ef015e6SRamesh Babu } 4461ef015e6SRamesh Babu 447e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 448e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 449e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 450e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 451e68aca08SJayachandran B else 452e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 45392eb4f62SJeeja KP 454e68aca08SJayachandran B if (ret < 0) 455e68aca08SJayachandran B goto err; 456e68aca08SJayachandran B 457e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 458e68aca08SJayachandran B 459e68aca08SJayachandran B /* 460e68aca08SJayachandran B * Enable interrupt after SPA is set and before 461e68aca08SJayachandran B * DSP is unstalled 462e68aca08SJayachandran B */ 46392eb4f62SJeeja KP skl_ipc_int_enable(ctx); 46492eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 465e68aca08SJayachandran B skl->boot_complete = false; 466e68aca08SJayachandran B } 46792eb4f62SJeeja KP 468e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 469e68aca08SJayachandran B if (ret < 0) 470e68aca08SJayachandran B goto err; 471e68aca08SJayachandran B 472e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 473e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 474e68aca08SJayachandran B skl->boot_complete, 47592eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 476e68aca08SJayachandran B 477e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 478e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 47992eb4f62SJeeja KP if (ret == 0) { 480e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 48192eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 48292eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 48392eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 484e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 485e68aca08SJayachandran B ret = -EIO; 486e68aca08SJayachandran B goto err; 487e68aca08SJayachandran B } 48892eb4f62SJeeja KP } 48992eb4f62SJeeja KP 490e68aca08SJayachandran B /* Tell FW if additional core in now On */ 491e68aca08SJayachandran B 492e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 493e68aca08SJayachandran B dx.core_mask = core_mask; 494e68aca08SJayachandran B dx.dx_mask = core_mask; 495e68aca08SJayachandran B 496e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 497e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 498e68aca08SJayachandran B if (ret < 0) { 499e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 500e68aca08SJayachandran B core_id, ret); 501e68aca08SJayachandran B goto err; 502e68aca08SJayachandran B } 503e68aca08SJayachandran B } 504e68aca08SJayachandran B 505e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 50692eb4f62SJeeja KP return 0; 507e68aca08SJayachandran B err: 508e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 509e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 510e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 511e68aca08SJayachandran B 512e68aca08SJayachandran B return ret; 51392eb4f62SJeeja KP } 51492eb4f62SJeeja KP 515052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 51692eb4f62SJeeja KP { 517e68aca08SJayachandran B int ret; 51892eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 51992eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 520e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 52192eb4f62SJeeja KP 522e68aca08SJayachandran B dx.core_mask = core_mask; 52392eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 52492eb4f62SJeeja KP 525e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 526e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 527e68aca08SJayachandran B 528e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 529e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 530e68aca08SJayachandran B if (ret < 0) 531e68aca08SJayachandran B dev_err(ctx->dev, 532e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 533e68aca08SJayachandran B core_id); 534e68aca08SJayachandran B 535e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 53692eb4f62SJeeja KP if (ret < 0) { 537ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 53892eb4f62SJeeja KP return ret; 53992eb4f62SJeeja KP } 540e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 54192eb4f62SJeeja KP return 0; 54292eb4f62SJeeja KP } 54392eb4f62SJeeja KP 54492eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 54592eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 54692eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 5475bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3, 5485bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0, 54992eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 55092eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 5511ef015e6SRamesh Babu .load_library = bxt_load_library, 55292eb4f62SJeeja KP }; 55392eb4f62SJeeja KP 55492eb4f62SJeeja KP static struct sst_ops skl_ops = { 55592eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 55692eb4f62SJeeja KP .write = sst_shim32_write, 55792eb4f62SJeeja KP .read = sst_shim32_read, 55892eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 55992eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 56092eb4f62SJeeja KP .free = skl_dsp_free, 56192eb4f62SJeeja KP }; 56292eb4f62SJeeja KP 56392eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 56492eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 56592eb4f62SJeeja KP .ops = &skl_ops, 56692eb4f62SJeeja KP }; 56792eb4f62SJeeja KP 56892eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 56992eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 57092eb4f62SJeeja KP struct skl_sst **dsp) 57192eb4f62SJeeja KP { 57292eb4f62SJeeja KP struct skl_sst *skl; 57392eb4f62SJeeja KP struct sst_dsp *sst; 57492eb4f62SJeeja KP int ret; 57592eb4f62SJeeja KP 57692eb4f62SJeeja KP skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 57792eb4f62SJeeja KP if (skl == NULL) 57892eb4f62SJeeja KP return -ENOMEM; 57992eb4f62SJeeja KP 58092eb4f62SJeeja KP skl->dev = dev; 58192eb4f62SJeeja KP skl_dev.thread_context = skl; 5823467a64dSVinod Koul INIT_LIST_HEAD(&skl->uuid_list); 58392eb4f62SJeeja KP 58492eb4f62SJeeja KP skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 58592eb4f62SJeeja KP if (!skl->dsp) { 58692eb4f62SJeeja KP dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 58792eb4f62SJeeja KP return -ENODEV; 58892eb4f62SJeeja KP } 58992eb4f62SJeeja KP 59092eb4f62SJeeja KP sst = skl->dsp; 59192eb4f62SJeeja KP sst->fw_name = fw_name; 59292eb4f62SJeeja KP sst->dsp_ops = dsp_ops; 59392eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 59492eb4f62SJeeja KP sst->addr.lpe = mmio_base; 59592eb4f62SJeeja KP sst->addr.shim = mmio_base; 59692eb4f62SJeeja KP 59792eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 59892eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 59992eb4f62SJeeja KP 600b914bb55SVinod Koul INIT_LIST_HEAD(&sst->module_list); 60192eb4f62SJeeja KP ret = skl_ipc_init(dev, skl); 60292eb4f62SJeeja KP if (ret) 60392eb4f62SJeeja KP return ret; 60492eb4f62SJeeja KP 605a83e3b4cSVinod Koul /* set the D0i3 check */ 606a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 607a83e3b4cSVinod Koul 608052f103cSJayachandran B skl->cores.count = 2; 60992eb4f62SJeeja KP skl->boot_complete = false; 61092eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 61178cdbbdaSVinod Koul skl->is_first_boot = true; 612a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 613a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE; 61478cdbbdaSVinod Koul 61578cdbbdaSVinod Koul if (dsp) 61678cdbbdaSVinod Koul *dsp = skl; 61778cdbbdaSVinod Koul 61878cdbbdaSVinod Koul return 0; 61978cdbbdaSVinod Koul } 62078cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 62178cdbbdaSVinod Koul 62278cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 62378cdbbdaSVinod Koul { 62478cdbbdaSVinod Koul int ret; 62578cdbbdaSVinod Koul struct sst_dsp *sst = ctx->dsp; 62692eb4f62SJeeja KP 62792eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 62892eb4f62SJeeja KP if (ret < 0) { 629ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 63092eb4f62SJeeja KP return ret; 63192eb4f62SJeeja KP } 63292eb4f62SJeeja KP 633052f103cSJayachandran B skl_dsp_init_core_state(sst); 634052f103cSJayachandran B 635eee0e16fSJeeja KP if (ctx->lib_count > 1) { 636eee0e16fSJeeja KP ret = sst->fw_ops.load_library(sst, ctx->lib_info, 637eee0e16fSJeeja KP ctx->lib_count); 6381ef015e6SRamesh Babu if (ret < 0) { 639ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 6401ef015e6SRamesh Babu return ret; 6411ef015e6SRamesh Babu } 6421ef015e6SRamesh Babu } 64378cdbbdaSVinod Koul ctx->is_first_boot = false; 64492eb4f62SJeeja KP 64592eb4f62SJeeja KP return 0; 64692eb4f62SJeeja KP } 64778cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 64892eb4f62SJeeja KP 64992eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 65092eb4f62SJeeja KP { 65131d648f0SJeeja KP 65231d648f0SJeeja KP sst_bxt_release_library(ctx->lib_info, ctx->lib_count); 65331d648f0SJeeja KP if (ctx->dsp->fw) 65431d648f0SJeeja KP release_firmware(ctx->dsp->fw); 6553467a64dSVinod Koul skl_freeup_uuid_list(ctx); 65692eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 65792eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 65892eb4f62SJeeja KP 65992eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 66092eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 66192eb4f62SJeeja KP 66292eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 66392eb4f62SJeeja KP } 66492eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 66592eb4f62SJeeja KP 66692eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 66792eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 668