192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 2892eb4f62SJeeja KP #define BXT_INIT_TIMEOUT 500 2992eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3092eb4f62SJeeja KP 3192eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3292eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3392eb4f62SJeeja KP 3492eb4f62SJeeja KP /* Firmware status window */ 3592eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3692eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3792eb4f62SJeeja KP 3892eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 3992eb4f62SJeeja KP 4092eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 4192eb4f62SJeeja KP { 4292eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 4392eb4f62SJeeja KP } 4492eb4f62SJeeja KP 4592eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 4692eb4f62SJeeja KP const void *fwdata, u32 fwsize) 4792eb4f62SJeeja KP { 4892eb4f62SJeeja KP int stream_tag, ret, i; 4992eb4f62SJeeja KP u32 reg; 5092eb4f62SJeeja KP 5192eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 5292eb4f62SJeeja KP if (stream_tag < 0) { 5392eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 5492eb4f62SJeeja KP stream_tag); 5592eb4f62SJeeja KP return stream_tag; 5692eb4f62SJeeja KP } 5792eb4f62SJeeja KP 5892eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 5992eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 6092eb4f62SJeeja KP 612023576dSSenthilnathan Veppur ret = skl_dsp_core_power_up(ctx); 6292eb4f62SJeeja KP if (ret < 0) { 6392eb4f62SJeeja KP dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret); 642023576dSSenthilnathan Veppur goto base_fw_load_failed; 652023576dSSenthilnathan Veppur } 662023576dSSenthilnathan Veppur 672023576dSSenthilnathan Veppur /* Purge FW request */ 682023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 692023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 702023576dSSenthilnathan Veppur 712023576dSSenthilnathan Veppur ret = skl_dsp_start_core(ctx); 722023576dSSenthilnathan Veppur if (ret < 0) { 732023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 7492eb4f62SJeeja KP ret = -EIO; 7592eb4f62SJeeja KP goto base_fw_load_failed; 7692eb4f62SJeeja KP } 7792eb4f62SJeeja KP 7892eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 7992eb4f62SJeeja KP reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE); 8092eb4f62SJeeja KP 8192eb4f62SJeeja KP if (reg & SKL_ADSP_REG_HIPCIE_DONE) { 8292eb4f62SJeeja KP sst_dsp_shim_update_bits_forced(ctx, 8392eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE, 8492eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 8592eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 8692eb4f62SJeeja KP break; 8792eb4f62SJeeja KP } 8892eb4f62SJeeja KP mdelay(1); 8992eb4f62SJeeja KP } 9092eb4f62SJeeja KP if (!i) { 9192eb4f62SJeeja KP dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg); 9292eb4f62SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE, 9392eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 9492eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE); 9592eb4f62SJeeja KP } 9692eb4f62SJeeja KP 9792eb4f62SJeeja KP /* enable Interrupt */ 9892eb4f62SJeeja KP skl_ipc_int_enable(ctx); 9992eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 10092eb4f62SJeeja KP 10192eb4f62SJeeja KP for (i = BXT_INIT_TIMEOUT; i > 0; --i) { 10292eb4f62SJeeja KP if (SKL_FW_INIT == 10392eb4f62SJeeja KP (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) & 10492eb4f62SJeeja KP SKL_FW_STS_MASK)) { 10592eb4f62SJeeja KP 10692eb4f62SJeeja KP dev_info(ctx->dev, "ROM loaded, continue FW loading\n"); 10792eb4f62SJeeja KP break; 10892eb4f62SJeeja KP } 10992eb4f62SJeeja KP mdelay(1); 11092eb4f62SJeeja KP } 11192eb4f62SJeeja KP if (!i) { 11292eb4f62SJeeja KP dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg); 11392eb4f62SJeeja KP ret = -EIO; 11492eb4f62SJeeja KP goto base_fw_load_failed; 11592eb4f62SJeeja KP } 11692eb4f62SJeeja KP 11792eb4f62SJeeja KP return ret; 11892eb4f62SJeeja KP 11992eb4f62SJeeja KP base_fw_load_failed: 12092eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 12192eb4f62SJeeja KP skl_dsp_disable_core(ctx); 12292eb4f62SJeeja KP return ret; 12392eb4f62SJeeja KP } 12492eb4f62SJeeja KP 12592eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 12692eb4f62SJeeja KP { 12792eb4f62SJeeja KP int ret; 12892eb4f62SJeeja KP 12992eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 13092eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 13192eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 13292eb4f62SJeeja KP 13392eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 13492eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 13592eb4f62SJeeja KP 13692eb4f62SJeeja KP return ret; 13792eb4f62SJeeja KP } 13892eb4f62SJeeja KP 1393467a64dSVinod Koul #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 1403467a64dSVinod Koul 14192eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 14292eb4f62SJeeja KP { 143bf242d19SVinod Koul struct firmware stripped_fw; 14492eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 14592eb4f62SJeeja KP int ret; 14692eb4f62SJeeja KP 147fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 14892eb4f62SJeeja KP if (ret < 0) { 14992eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 15092eb4f62SJeeja KP goto sst_load_base_firmware_failed; 15192eb4f62SJeeja KP } 15292eb4f62SJeeja KP 153bf242d19SVinod Koul /* check for extended manifest */ 154bf242d19SVinod Koul if (ctx->fw == NULL) 155bf242d19SVinod Koul goto sst_load_base_firmware_failed; 156bf242d19SVinod Koul 1573467a64dSVinod Koul ret = snd_skl_parse_uuids(ctx, BXT_ADSP_FW_BIN_HDR_OFFSET); 1583467a64dSVinod Koul if (ret < 0) 1593467a64dSVinod Koul goto sst_load_base_firmware_failed; 160bf242d19SVinod Koul 161bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 162bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 163bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 164bf242d19SVinod Koul 165bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 16692eb4f62SJeeja KP /* Retry Enabling core and ROM load. Retry seemed to help */ 16792eb4f62SJeeja KP if (ret < 0) { 168bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 16992eb4f62SJeeja KP if (ret < 0) { 1702023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 1712023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 1722023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 1732023576dSSenthilnathan Veppur 17492eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 17592eb4f62SJeeja KP goto sst_load_base_firmware_failed; 17692eb4f62SJeeja KP } 17792eb4f62SJeeja KP } 17892eb4f62SJeeja KP 17992eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 18092eb4f62SJeeja KP if (ret < 0) { 18192eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 18292eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 18392eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 18492eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 18592eb4f62SJeeja KP 18692eb4f62SJeeja KP skl_dsp_disable_core(ctx); 18792eb4f62SJeeja KP } else { 18892eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 18992eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 19092eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 19192eb4f62SJeeja KP if (ret == 0) { 19292eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 19392eb4f62SJeeja KP skl_dsp_disable_core(ctx); 19492eb4f62SJeeja KP ret = -EIO; 19592eb4f62SJeeja KP } else { 19692eb4f62SJeeja KP skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 19792eb4f62SJeeja KP ret = 0; 1981665c177SJayachandran B skl->fw_loaded = true; 19992eb4f62SJeeja KP } 20092eb4f62SJeeja KP } 20192eb4f62SJeeja KP 20292eb4f62SJeeja KP sst_load_base_firmware_failed: 203fdfa82eeSVinod Koul release_firmware(ctx->fw); 20492eb4f62SJeeja KP return ret; 20592eb4f62SJeeja KP } 20692eb4f62SJeeja KP 20792eb4f62SJeeja KP static int bxt_set_dsp_D0(struct sst_dsp *ctx) 20892eb4f62SJeeja KP { 20992eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 21092eb4f62SJeeja KP int ret; 21192eb4f62SJeeja KP 21292eb4f62SJeeja KP skl->boot_complete = false; 21392eb4f62SJeeja KP 2141665c177SJayachandran B if (skl->fw_loaded == false) { 2151665c177SJayachandran B dev_dbg(ctx->dev, "Re-loading fw\n"); 2161665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 2171665c177SJayachandran B if (ret < 0) 2181665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 2191665c177SJayachandran B return ret; 2201665c177SJayachandran B } 2211665c177SJayachandran B 22292eb4f62SJeeja KP ret = skl_dsp_enable_core(ctx); 22392eb4f62SJeeja KP if (ret < 0) { 22492eb4f62SJeeja KP dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret); 22592eb4f62SJeeja KP return ret; 22692eb4f62SJeeja KP } 22792eb4f62SJeeja KP 22892eb4f62SJeeja KP /* enable interrupt */ 22992eb4f62SJeeja KP skl_ipc_int_enable(ctx); 23092eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 23192eb4f62SJeeja KP 23292eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 23392eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 23492eb4f62SJeeja KP if (ret == 0) { 23592eb4f62SJeeja KP dev_err(ctx->dev, "ipc: error DSP boot timeout\n"); 23692eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 23792eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 23892eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 23992eb4f62SJeeja KP return -EIO; 24092eb4f62SJeeja KP } 24192eb4f62SJeeja KP 24292eb4f62SJeeja KP skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING); 24392eb4f62SJeeja KP return 0; 24492eb4f62SJeeja KP } 24592eb4f62SJeeja KP 24692eb4f62SJeeja KP static int bxt_set_dsp_D3(struct sst_dsp *ctx) 24792eb4f62SJeeja KP { 24892eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 24992eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 25092eb4f62SJeeja KP int ret = 0; 25192eb4f62SJeeja KP 25292eb4f62SJeeja KP if (!is_skl_dsp_running(ctx)) 25392eb4f62SJeeja KP return ret; 25492eb4f62SJeeja KP 25592eb4f62SJeeja KP dx.core_mask = SKL_DSP_CORE0_MASK; 25692eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 25792eb4f62SJeeja KP 25892eb4f62SJeeja KP ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, 25992eb4f62SJeeja KP SKL_BASE_FW_MODULE_ID, &dx); 26092eb4f62SJeeja KP if (ret < 0) { 26192eb4f62SJeeja KP dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret); 26292eb4f62SJeeja KP return ret; 26392eb4f62SJeeja KP } 26492eb4f62SJeeja KP 26592eb4f62SJeeja KP ret = skl_dsp_disable_core(ctx); 26692eb4f62SJeeja KP if (ret < 0) { 26792eb4f62SJeeja KP dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret); 26892eb4f62SJeeja KP ret = -EIO; 26992eb4f62SJeeja KP } 27092eb4f62SJeeja KP 27192eb4f62SJeeja KP skl_dsp_set_state_locked(ctx, SKL_DSP_RESET); 27292eb4f62SJeeja KP return 0; 27392eb4f62SJeeja KP } 27492eb4f62SJeeja KP 27592eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 27692eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 27792eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 27892eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 27992eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 28092eb4f62SJeeja KP }; 28192eb4f62SJeeja KP 28292eb4f62SJeeja KP static struct sst_ops skl_ops = { 28392eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 28492eb4f62SJeeja KP .write = sst_shim32_write, 28592eb4f62SJeeja KP .read = sst_shim32_read, 28692eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 28792eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 28892eb4f62SJeeja KP .free = skl_dsp_free, 28992eb4f62SJeeja KP }; 29092eb4f62SJeeja KP 29192eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 29292eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 29392eb4f62SJeeja KP .ops = &skl_ops, 29492eb4f62SJeeja KP }; 29592eb4f62SJeeja KP 29692eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 29792eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 29892eb4f62SJeeja KP struct skl_sst **dsp) 29992eb4f62SJeeja KP { 30092eb4f62SJeeja KP struct skl_sst *skl; 30192eb4f62SJeeja KP struct sst_dsp *sst; 30292eb4f62SJeeja KP int ret; 30392eb4f62SJeeja KP 30492eb4f62SJeeja KP skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 30592eb4f62SJeeja KP if (skl == NULL) 30692eb4f62SJeeja KP return -ENOMEM; 30792eb4f62SJeeja KP 30892eb4f62SJeeja KP skl->dev = dev; 30992eb4f62SJeeja KP skl_dev.thread_context = skl; 3103467a64dSVinod Koul INIT_LIST_HEAD(&skl->uuid_list); 31192eb4f62SJeeja KP 31292eb4f62SJeeja KP skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 31392eb4f62SJeeja KP if (!skl->dsp) { 31492eb4f62SJeeja KP dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 31592eb4f62SJeeja KP return -ENODEV; 31692eb4f62SJeeja KP } 31792eb4f62SJeeja KP 31892eb4f62SJeeja KP sst = skl->dsp; 31992eb4f62SJeeja KP sst->fw_name = fw_name; 32092eb4f62SJeeja KP sst->dsp_ops = dsp_ops; 32192eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 32292eb4f62SJeeja KP sst->addr.lpe = mmio_base; 32392eb4f62SJeeja KP sst->addr.shim = mmio_base; 32492eb4f62SJeeja KP 32592eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 32692eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 32792eb4f62SJeeja KP 32892eb4f62SJeeja KP ret = skl_ipc_init(dev, skl); 32992eb4f62SJeeja KP if (ret) 33092eb4f62SJeeja KP return ret; 33192eb4f62SJeeja KP 33292eb4f62SJeeja KP skl->boot_complete = false; 33392eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 33492eb4f62SJeeja KP 33592eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 33692eb4f62SJeeja KP if (ret < 0) { 33792eb4f62SJeeja KP dev_err(dev, "Load base fw failed: %x", ret); 33892eb4f62SJeeja KP return ret; 33992eb4f62SJeeja KP } 34092eb4f62SJeeja KP 34192eb4f62SJeeja KP if (dsp) 34292eb4f62SJeeja KP *dsp = skl; 34392eb4f62SJeeja KP 34492eb4f62SJeeja KP return 0; 34592eb4f62SJeeja KP } 34692eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 34792eb4f62SJeeja KP 34892eb4f62SJeeja KP 34992eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 35092eb4f62SJeeja KP { 3513467a64dSVinod Koul skl_freeup_uuid_list(ctx); 35292eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 35392eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 35492eb4f62SJeeja KP 35592eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 35692eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 35792eb4f62SJeeja KP 35892eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 35992eb4f62SJeeja KP } 36092eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 36192eb4f62SJeeja KP 36292eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 36392eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 364