192eb4f62SJeeja KP /* 292eb4f62SJeeja KP * bxt-sst.c - DSP library functions for BXT platform 392eb4f62SJeeja KP * 492eb4f62SJeeja KP * Copyright (C) 2015-16 Intel Corp 592eb4f62SJeeja KP * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> 692eb4f62SJeeja KP * Jeeja KP <jeeja.kp@intel.com> 792eb4f62SJeeja KP * 892eb4f62SJeeja KP * This program is free software; you can redistribute it and/or modify 992eb4f62SJeeja KP * it under the terms of the GNU General Public License as published by 1092eb4f62SJeeja KP * the Free Software Foundation; version 2 of the License. 1192eb4f62SJeeja KP * 1292eb4f62SJeeja KP * This program is distributed in the hope that it will be useful, but 1392eb4f62SJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 1492eb4f62SJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1592eb4f62SJeeja KP * General Public License for more details. 1692eb4f62SJeeja KP */ 1792eb4f62SJeeja KP 1892eb4f62SJeeja KP #include <linux/module.h> 1992eb4f62SJeeja KP #include <linux/delay.h> 2092eb4f62SJeeja KP #include <linux/firmware.h> 2192eb4f62SJeeja KP #include <linux/device.h> 2292eb4f62SJeeja KP 2392eb4f62SJeeja KP #include "../common/sst-dsp.h" 2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h" 2592eb4f62SJeeja KP #include "skl-sst-ipc.h" 2692eb4f62SJeeja KP 2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT 3000 2892eb4f62SJeeja KP #define BXT_INIT_TIMEOUT 500 2992eb4f62SJeeja KP #define BXT_IPC_PURGE_FW 0x01004000 3092eb4f62SJeeja KP 3192eb4f62SJeeja KP #define BXT_ROM_INIT 0x5 3292eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE 0x80000 3392eb4f62SJeeja KP 3492eb4f62SJeeja KP /* Firmware status window */ 3592eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE 3692eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4) 3792eb4f62SJeeja KP 3892eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE 0xA0000 3992eb4f62SJeeja KP 40e68aca08SJayachandran B #define BXT_INSTANCE_ID 0 41e68aca08SJayachandran B #define BXT_BASE_FW_MODULE_ID 0 42e68aca08SJayachandran B 431ef015e6SRamesh Babu #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000 441ef015e6SRamesh Babu 455bb4cd46SJayachandran B /* Delay before scheduling D0i3 entry */ 465bb4cd46SJayachandran B #define BXT_D0I3_DELAY 5000 475bb4cd46SJayachandran B 4892eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx) 4992eb4f62SJeeja KP { 5092eb4f62SJeeja KP return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE); 5192eb4f62SJeeja KP } 5292eb4f62SJeeja KP 531ef015e6SRamesh Babu static int 54eee0e16fSJeeja KP bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count) 551ef015e6SRamesh Babu { 561ef015e6SRamesh Babu struct snd_dma_buffer dmab; 571ef015e6SRamesh Babu struct skl_sst *skl = ctx->thread_context; 581ef015e6SRamesh Babu const struct firmware *fw = NULL; 591ef015e6SRamesh Babu struct firmware stripped_fw; 601ef015e6SRamesh Babu int ret = 0, i, dma_id, stream_tag; 611ef015e6SRamesh Babu 621ef015e6SRamesh Babu /* library indices start from 1 to N. 0 represents base FW */ 63eee0e16fSJeeja KP for (i = 1; i < lib_count; i++) { 64eee0e16fSJeeja KP ret = request_firmware(&fw, linfo[i].name, ctx->dev); 651ef015e6SRamesh Babu if (ret < 0) { 661ef015e6SRamesh Babu dev_err(ctx->dev, "Request lib %s failed:%d\n", 67eee0e16fSJeeja KP linfo[i].name, ret); 681ef015e6SRamesh Babu return ret; 691ef015e6SRamesh Babu } 701ef015e6SRamesh Babu 711ef015e6SRamesh Babu if (skl->is_first_boot) { 721ef015e6SRamesh Babu ret = snd_skl_parse_uuids(ctx, fw, 731ef015e6SRamesh Babu BXT_ADSP_FW_BIN_HDR_OFFSET, i); 741ef015e6SRamesh Babu if (ret < 0) 751ef015e6SRamesh Babu goto load_library_failed; 761ef015e6SRamesh Babu } 771ef015e6SRamesh Babu 781ef015e6SRamesh Babu stripped_fw.data = fw->data; 791ef015e6SRamesh Babu stripped_fw.size = fw->size; 801ef015e6SRamesh Babu skl_dsp_strip_extended_manifest(&stripped_fw); 811ef015e6SRamesh Babu 821ef015e6SRamesh Babu stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, 831ef015e6SRamesh Babu stripped_fw.size, &dmab); 841ef015e6SRamesh Babu if (stream_tag <= 0) { 851ef015e6SRamesh Babu dev_err(ctx->dev, "Lib prepare DMA err: %x\n", 861ef015e6SRamesh Babu stream_tag); 871ef015e6SRamesh Babu ret = stream_tag; 881ef015e6SRamesh Babu goto load_library_failed; 891ef015e6SRamesh Babu } 901ef015e6SRamesh Babu 911ef015e6SRamesh Babu dma_id = stream_tag - 1; 921ef015e6SRamesh Babu memcpy(dmab.area, stripped_fw.data, stripped_fw.size); 931ef015e6SRamesh Babu 941ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, true, stream_tag); 951ef015e6SRamesh Babu ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i); 961ef015e6SRamesh Babu if (ret < 0) 971ef015e6SRamesh Babu dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n", 98eee0e16fSJeeja KP linfo[i].name, ret); 991ef015e6SRamesh Babu 1001ef015e6SRamesh Babu ctx->dsp_ops.trigger(ctx->dev, false, stream_tag); 1011ef015e6SRamesh Babu ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag); 1021ef015e6SRamesh Babu release_firmware(fw); 1031ef015e6SRamesh Babu fw = NULL; 1041ef015e6SRamesh Babu } 1051ef015e6SRamesh Babu 1061ef015e6SRamesh Babu return ret; 1071ef015e6SRamesh Babu 1081ef015e6SRamesh Babu load_library_failed: 1091ef015e6SRamesh Babu release_firmware(fw); 1101ef015e6SRamesh Babu return ret; 1111ef015e6SRamesh Babu } 1121ef015e6SRamesh Babu 113e68aca08SJayachandran B /* 114e68aca08SJayachandran B * First boot sequence has some extra steps. Core 0 waits for power 115e68aca08SJayachandran B * status on core 1, so power up core 1 also momentarily, keep it in 116e68aca08SJayachandran B * reset/stall and then turn it off 117e68aca08SJayachandran B */ 11892eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx, 11992eb4f62SJeeja KP const void *fwdata, u32 fwsize) 12092eb4f62SJeeja KP { 121eee0e16fSJeeja KP int stream_tag, ret; 12292eb4f62SJeeja KP 12392eb4f62SJeeja KP stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab); 124e68aca08SJayachandran B if (stream_tag <= 0) { 12592eb4f62SJeeja KP dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n", 12692eb4f62SJeeja KP stream_tag); 12792eb4f62SJeeja KP return stream_tag; 12892eb4f62SJeeja KP } 12992eb4f62SJeeja KP 13092eb4f62SJeeja KP ctx->dsp_ops.stream_tag = stream_tag; 13192eb4f62SJeeja KP memcpy(ctx->dmab.area, fwdata, fwsize); 13292eb4f62SJeeja KP 133e68aca08SJayachandran B /* Step 1: Power up core 0 and core1 */ 134e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK | 135e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 13692eb4f62SJeeja KP if (ret < 0) { 137e68aca08SJayachandran B dev_err(ctx->dev, "dsp core0/1 power up failed\n"); 1382023576dSSenthilnathan Veppur goto base_fw_load_failed; 1392023576dSSenthilnathan Veppur } 1402023576dSSenthilnathan Veppur 141e68aca08SJayachandran B /* Step 2: Purge FW request */ 1422023576dSSenthilnathan Veppur sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY | 1432023576dSSenthilnathan Veppur (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9))); 1442023576dSSenthilnathan Veppur 145e68aca08SJayachandran B /* Step 3: Unset core0 reset state & unstall/run core0 */ 146052f103cSJayachandran B ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK); 1472023576dSSenthilnathan Veppur if (ret < 0) { 1482023576dSSenthilnathan Veppur dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret); 14992eb4f62SJeeja KP ret = -EIO; 15092eb4f62SJeeja KP goto base_fw_load_failed; 15192eb4f62SJeeja KP } 15292eb4f62SJeeja KP 153e68aca08SJayachandran B /* Step 4: Wait for DONE Bit */ 1541448099dSJeeja KP ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE, 15592eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 15692eb4f62SJeeja KP SKL_ADSP_REG_HIPCIE_DONE, 1571448099dSJeeja KP BXT_INIT_TIMEOUT, "HIPCIE Done"); 1581448099dSJeeja KP if (ret < 0) { 1591448099dSJeeja KP dev_err(ctx->dev, "Timout for Purge Request%d\n", ret); 1601448099dSJeeja KP goto base_fw_load_failed; 16192eb4f62SJeeja KP } 16292eb4f62SJeeja KP 163e68aca08SJayachandran B /* Step 5: power down core1 */ 164e68aca08SJayachandran B ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 165e68aca08SJayachandran B if (ret < 0) { 166e68aca08SJayachandran B dev_err(ctx->dev, "dsp core1 power down failed\n"); 167e68aca08SJayachandran B goto base_fw_load_failed; 168e68aca08SJayachandran B } 169e68aca08SJayachandran B 170e68aca08SJayachandran B /* Step 6: Enable Interrupt */ 17192eb4f62SJeeja KP skl_ipc_int_enable(ctx); 17292eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 17392eb4f62SJeeja KP 174e68aca08SJayachandran B /* Step 7: Wait for ROM init */ 1751448099dSJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 1761448099dSJeeja KP SKL_FW_INIT, BXT_INIT_TIMEOUT, "ROM Load"); 1771448099dSJeeja KP if (ret < 0) { 1781448099dSJeeja KP dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret); 17992eb4f62SJeeja KP goto base_fw_load_failed; 18092eb4f62SJeeja KP } 18192eb4f62SJeeja KP 18292eb4f62SJeeja KP return ret; 18392eb4f62SJeeja KP 18492eb4f62SJeeja KP base_fw_load_failed: 18592eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag); 186052f103cSJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 187c7872267SSenthilnathan Veppur skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 18892eb4f62SJeeja KP return ret; 18992eb4f62SJeeja KP } 19092eb4f62SJeeja KP 19192eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx) 19292eb4f62SJeeja KP { 19392eb4f62SJeeja KP int ret; 19492eb4f62SJeeja KP 19592eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag); 19692eb4f62SJeeja KP ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK, 19792eb4f62SJeeja KP BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot"); 19892eb4f62SJeeja KP 19992eb4f62SJeeja KP ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag); 20092eb4f62SJeeja KP ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag); 20192eb4f62SJeeja KP 20292eb4f62SJeeja KP return ret; 20392eb4f62SJeeja KP } 20492eb4f62SJeeja KP 20592eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx) 20692eb4f62SJeeja KP { 207bf242d19SVinod Koul struct firmware stripped_fw; 20892eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 20992eb4f62SJeeja KP int ret; 21092eb4f62SJeeja KP 211fdfa82eeSVinod Koul ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev); 21292eb4f62SJeeja KP if (ret < 0) { 21392eb4f62SJeeja KP dev_err(ctx->dev, "Request firmware failed %d\n", ret); 21492eb4f62SJeeja KP goto sst_load_base_firmware_failed; 21592eb4f62SJeeja KP } 21692eb4f62SJeeja KP 217bf242d19SVinod Koul /* check for extended manifest */ 218bf242d19SVinod Koul if (ctx->fw == NULL) 219bf242d19SVinod Koul goto sst_load_base_firmware_failed; 220bf242d19SVinod Koul 2210bdd6d8bSVinod Koul /* prase uuids on first boot */ 2220bdd6d8bSVinod Koul if (skl->is_first_boot) { 223a8e2c19eSSenthilnathan Veppur ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0); 2243467a64dSVinod Koul if (ret < 0) 2253467a64dSVinod Koul goto sst_load_base_firmware_failed; 2260bdd6d8bSVinod Koul } 227bf242d19SVinod Koul 228bf242d19SVinod Koul stripped_fw.data = ctx->fw->data; 229bf242d19SVinod Koul stripped_fw.size = ctx->fw->size; 230bf242d19SVinod Koul skl_dsp_strip_extended_manifest(&stripped_fw); 231bf242d19SVinod Koul 232bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 23392eb4f62SJeeja KP /* Retry Enabling core and ROM load. Retry seemed to help */ 23492eb4f62SJeeja KP if (ret < 0) { 235bf242d19SVinod Koul ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size); 23692eb4f62SJeeja KP if (ret < 0) { 2372023576dSSenthilnathan Veppur dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 2382023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 2392023576dSSenthilnathan Veppur sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 2402023576dSSenthilnathan Veppur 24192eb4f62SJeeja KP dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret); 24292eb4f62SJeeja KP goto sst_load_base_firmware_failed; 24392eb4f62SJeeja KP } 24492eb4f62SJeeja KP } 24592eb4f62SJeeja KP 24692eb4f62SJeeja KP ret = sst_transfer_fw_host_dma(ctx); 24792eb4f62SJeeja KP if (ret < 0) { 24892eb4f62SJeeja KP dev_err(ctx->dev, "Transfer firmware failed %d\n", ret); 24992eb4f62SJeeja KP dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 25092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 25192eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 25292eb4f62SJeeja KP 253052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 25492eb4f62SJeeja KP } else { 25592eb4f62SJeeja KP dev_dbg(ctx->dev, "Firmware download successful\n"); 25692eb4f62SJeeja KP ret = wait_event_timeout(skl->boot_wait, skl->boot_complete, 25792eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 25892eb4f62SJeeja KP if (ret == 0) { 25992eb4f62SJeeja KP dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n"); 260052f103cSJayachandran B skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK); 26192eb4f62SJeeja KP ret = -EIO; 26292eb4f62SJeeja KP } else { 26392eb4f62SJeeja KP ret = 0; 2641665c177SJayachandran B skl->fw_loaded = true; 26592eb4f62SJeeja KP } 26692eb4f62SJeeja KP } 26792eb4f62SJeeja KP 26892eb4f62SJeeja KP sst_load_base_firmware_failed: 269fdfa82eeSVinod Koul release_firmware(ctx->fw); 27092eb4f62SJeeja KP return ret; 27192eb4f62SJeeja KP } 27292eb4f62SJeeja KP 2735bb4cd46SJayachandran B /* 2745bb4cd46SJayachandran B * Decide the D0i3 state that can be targeted based on the usecase 2755bb4cd46SJayachandran B * ref counts and DSP state 2765bb4cd46SJayachandran B * 2775bb4cd46SJayachandran B * Decision Matrix: (X= dont care; state = target state) 2785bb4cd46SJayachandran B * 2795bb4cd46SJayachandran B * DSP state != SKL_DSP_RUNNING ; state = no d0i3 2805bb4cd46SJayachandran B * 2815bb4cd46SJayachandran B * DSP state == SKL_DSP_RUNNING , the following matrix applies 2825bb4cd46SJayachandran B * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3 2835bb4cd46SJayachandran B * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3 2845bb4cd46SJayachandran B * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3 2855bb4cd46SJayachandran B * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3 2865bb4cd46SJayachandran B */ 2875bb4cd46SJayachandran B static int bxt_d0i3_target_state(struct sst_dsp *ctx) 2885bb4cd46SJayachandran B { 2895bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 2905bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 2915bb4cd46SJayachandran B 2925bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) 2935bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2945bb4cd46SJayachandran B 2955bb4cd46SJayachandran B if (d0i3->non_d0i3) 2965bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 2975bb4cd46SJayachandran B else if (d0i3->streaming) 2985bb4cd46SJayachandran B return SKL_DSP_D0I3_STREAMING; 2995bb4cd46SJayachandran B else if (d0i3->non_streaming) 3005bb4cd46SJayachandran B return SKL_DSP_D0I3_NON_STREAMING; 3015bb4cd46SJayachandran B else 3025bb4cd46SJayachandran B return SKL_DSP_D0I3_NONE; 3035bb4cd46SJayachandran B } 3045bb4cd46SJayachandran B 3055bb4cd46SJayachandran B static void bxt_set_dsp_D0i3(struct work_struct *work) 3065bb4cd46SJayachandran B { 3075bb4cd46SJayachandran B int ret; 3085bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3095bb4cd46SJayachandran B struct skl_sst *skl = container_of(work, 3105bb4cd46SJayachandran B struct skl_sst, d0i3.work.work); 3115bb4cd46SJayachandran B struct sst_dsp *ctx = skl->dsp; 3125bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3135bb4cd46SJayachandran B int target_state; 3145bb4cd46SJayachandran B 3155bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3165bb4cd46SJayachandran B 3175bb4cd46SJayachandran B /* D0i3 entry allowed only if core 0 alone is running */ 3185bb4cd46SJayachandran B if (skl_dsp_get_enabled_cores(ctx) != SKL_DSP_CORE0_MASK) { 3195bb4cd46SJayachandran B dev_warn(ctx->dev, 3205bb4cd46SJayachandran B "D0i3 allowed when only core0 running:Exit\n"); 3215bb4cd46SJayachandran B return; 3225bb4cd46SJayachandran B } 3235bb4cd46SJayachandran B 3245bb4cd46SJayachandran B target_state = bxt_d0i3_target_state(ctx); 3255bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_NONE) 3265bb4cd46SJayachandran B return; 3275bb4cd46SJayachandran B 3285bb4cd46SJayachandran B msg.instance_id = 0; 3295bb4cd46SJayachandran B msg.module_id = 0; 3305bb4cd46SJayachandran B msg.wake = 1; 3315bb4cd46SJayachandran B msg.streaming = 0; 3325bb4cd46SJayachandran B if (target_state == SKL_DSP_D0I3_STREAMING) 3335bb4cd46SJayachandran B msg.streaming = 1; 3345bb4cd46SJayachandran B 3355bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3365bb4cd46SJayachandran B 3375bb4cd46SJayachandran B if (ret < 0) { 3385bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n"); 3395bb4cd46SJayachandran B return; 3405bb4cd46SJayachandran B } 3415bb4cd46SJayachandran B 3425bb4cd46SJayachandran B /* Set Vendor specific register D0I3C.I3 to enable D0i3*/ 3435bb4cd46SJayachandran B if (skl->update_d0i3c) 3445bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, true); 3455bb4cd46SJayachandran B 3465bb4cd46SJayachandran B d0i3->state = target_state; 3475bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; 3485bb4cd46SJayachandran B } 3495bb4cd46SJayachandran B 3505bb4cd46SJayachandran B static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx) 3515bb4cd46SJayachandran B { 3525bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3535bb4cd46SJayachandran B struct skl_d0i3_data *d0i3 = &skl->d0i3; 3545bb4cd46SJayachandran B 3555bb4cd46SJayachandran B /* Schedule D0i3 only if the usecase ref counts are appropriate */ 3565bb4cd46SJayachandran B if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) { 3575bb4cd46SJayachandran B 3585bb4cd46SJayachandran B dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__); 3595bb4cd46SJayachandran B 3605bb4cd46SJayachandran B schedule_delayed_work(&d0i3->work, 3615bb4cd46SJayachandran B msecs_to_jiffies(BXT_D0I3_DELAY)); 3625bb4cd46SJayachandran B } 3635bb4cd46SJayachandran B 3645bb4cd46SJayachandran B return 0; 3655bb4cd46SJayachandran B } 3665bb4cd46SJayachandran B 3675bb4cd46SJayachandran B static int bxt_set_dsp_D0i0(struct sst_dsp *ctx) 3685bb4cd46SJayachandran B { 3695bb4cd46SJayachandran B int ret; 3705bb4cd46SJayachandran B struct skl_ipc_d0ix_msg msg; 3715bb4cd46SJayachandran B struct skl_sst *skl = ctx->thread_context; 3725bb4cd46SJayachandran B 3735bb4cd46SJayachandran B dev_dbg(ctx->dev, "In %s:\n", __func__); 3745bb4cd46SJayachandran B 3755bb4cd46SJayachandran B /* First Cancel any pending attempt to put DSP to D0i3 */ 3765bb4cd46SJayachandran B cancel_delayed_work_sync(&skl->d0i3.work); 3775bb4cd46SJayachandran B 3785bb4cd46SJayachandran B /* If DSP is currently in D0i3, bring it to D0i0 */ 3795bb4cd46SJayachandran B if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) 3805bb4cd46SJayachandran B return 0; 3815bb4cd46SJayachandran B 3825bb4cd46SJayachandran B dev_dbg(ctx->dev, "Set DSP to D0i0\n"); 3835bb4cd46SJayachandran B 3845bb4cd46SJayachandran B msg.instance_id = 0; 3855bb4cd46SJayachandran B msg.module_id = 0; 3865bb4cd46SJayachandran B msg.streaming = 0; 3875bb4cd46SJayachandran B msg.wake = 0; 3885bb4cd46SJayachandran B 3895bb4cd46SJayachandran B if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING) 3905bb4cd46SJayachandran B msg.streaming = 1; 3915bb4cd46SJayachandran B 3925bb4cd46SJayachandran B /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/ 3935bb4cd46SJayachandran B if (skl->update_d0i3c) 3945bb4cd46SJayachandran B skl->update_d0i3c(skl->dev, false); 3955bb4cd46SJayachandran B 3965bb4cd46SJayachandran B ret = skl_ipc_set_d0ix(&skl->ipc, &msg); 3975bb4cd46SJayachandran B if (ret < 0) { 3985bb4cd46SJayachandran B dev_err(ctx->dev, "Failed to set DSP to D0i0\n"); 3995bb4cd46SJayachandran B return ret; 4005bb4cd46SJayachandran B } 4015bb4cd46SJayachandran B 4025bb4cd46SJayachandran B skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; 4035bb4cd46SJayachandran B skl->d0i3.state = SKL_DSP_D0I3_NONE; 4045bb4cd46SJayachandran B 4055bb4cd46SJayachandran B return 0; 4065bb4cd46SJayachandran B } 4075bb4cd46SJayachandran B 408052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id) 40992eb4f62SJeeja KP { 41092eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 41192eb4f62SJeeja KP int ret; 412e68aca08SJayachandran B struct skl_ipc_dxstate_info dx; 413e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 41492eb4f62SJeeja KP 4151665c177SJayachandran B if (skl->fw_loaded == false) { 41692eb4f62SJeeja KP skl->boot_complete = false; 4171665c177SJayachandran B ret = bxt_load_base_firmware(ctx); 4181ef015e6SRamesh Babu if (ret < 0) { 4191665c177SJayachandran B dev_err(ctx->dev, "reload fw failed: %d\n", ret); 42092eb4f62SJeeja KP return ret; 42192eb4f62SJeeja KP } 42292eb4f62SJeeja KP 423eee0e16fSJeeja KP if (skl->lib_count > 1) { 424eee0e16fSJeeja KP ret = bxt_load_library(ctx, skl->lib_info, 425eee0e16fSJeeja KP skl->lib_count); 4261ef015e6SRamesh Babu if (ret < 0) { 4271ef015e6SRamesh Babu dev_err(ctx->dev, "reload libs failed: %d\n", ret); 4281ef015e6SRamesh Babu return ret; 4291ef015e6SRamesh Babu } 4301ef015e6SRamesh Babu } 4311ef015e6SRamesh Babu return ret; 4321ef015e6SRamesh Babu } 4331ef015e6SRamesh Babu 434e68aca08SJayachandran B /* If core 0 is being turned on, turn on core 1 as well */ 435e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 436e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask | 437e68aca08SJayachandran B SKL_DSP_CORE_MASK(1)); 438e68aca08SJayachandran B else 439e68aca08SJayachandran B ret = skl_dsp_core_power_up(ctx, core_mask); 44092eb4f62SJeeja KP 441e68aca08SJayachandran B if (ret < 0) 442e68aca08SJayachandran B goto err; 443e68aca08SJayachandran B 444e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 445e68aca08SJayachandran B 446e68aca08SJayachandran B /* 447e68aca08SJayachandran B * Enable interrupt after SPA is set and before 448e68aca08SJayachandran B * DSP is unstalled 449e68aca08SJayachandran B */ 45092eb4f62SJeeja KP skl_ipc_int_enable(ctx); 45192eb4f62SJeeja KP skl_ipc_op_int_enable(ctx); 452e68aca08SJayachandran B skl->boot_complete = false; 453e68aca08SJayachandran B } 45492eb4f62SJeeja KP 455e68aca08SJayachandran B ret = skl_dsp_start_core(ctx, core_mask); 456e68aca08SJayachandran B if (ret < 0) 457e68aca08SJayachandran B goto err; 458e68aca08SJayachandran B 459e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) { 460e68aca08SJayachandran B ret = wait_event_timeout(skl->boot_wait, 461e68aca08SJayachandran B skl->boot_complete, 46292eb4f62SJeeja KP msecs_to_jiffies(SKL_IPC_BOOT_MSECS)); 463e68aca08SJayachandran B 464e68aca08SJayachandran B /* If core 1 was turned on for booting core 0, turn it off */ 465e68aca08SJayachandran B skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1)); 46692eb4f62SJeeja KP if (ret == 0) { 467e68aca08SJayachandran B dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__); 46892eb4f62SJeeja KP dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n", 46992eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE), 47092eb4f62SJeeja KP sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS)); 471e68aca08SJayachandran B dev_err(ctx->dev, "Failed to set core0 to D0 state\n"); 472e68aca08SJayachandran B ret = -EIO; 473e68aca08SJayachandran B goto err; 474e68aca08SJayachandran B } 47592eb4f62SJeeja KP } 47692eb4f62SJeeja KP 477e68aca08SJayachandran B /* Tell FW if additional core in now On */ 478e68aca08SJayachandran B 479e68aca08SJayachandran B if (core_id != SKL_DSP_CORE0_ID) { 480e68aca08SJayachandran B dx.core_mask = core_mask; 481e68aca08SJayachandran B dx.dx_mask = core_mask; 482e68aca08SJayachandran B 483e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 484e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 485e68aca08SJayachandran B if (ret < 0) { 486e68aca08SJayachandran B dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n", 487e68aca08SJayachandran B core_id, ret); 488e68aca08SJayachandran B goto err; 489e68aca08SJayachandran B } 490e68aca08SJayachandran B } 491e68aca08SJayachandran B 492e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RUNNING; 49392eb4f62SJeeja KP return 0; 494e68aca08SJayachandran B err: 495e68aca08SJayachandran B if (core_id == SKL_DSP_CORE0_ID) 496e68aca08SJayachandran B core_mask |= SKL_DSP_CORE_MASK(1); 497e68aca08SJayachandran B skl_dsp_disable_core(ctx, core_mask); 498e68aca08SJayachandran B 499e68aca08SJayachandran B return ret; 50092eb4f62SJeeja KP } 50192eb4f62SJeeja KP 502052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id) 50392eb4f62SJeeja KP { 504e68aca08SJayachandran B int ret; 50592eb4f62SJeeja KP struct skl_ipc_dxstate_info dx; 50692eb4f62SJeeja KP struct skl_sst *skl = ctx->thread_context; 507e68aca08SJayachandran B unsigned int core_mask = SKL_DSP_CORE_MASK(core_id); 50892eb4f62SJeeja KP 509e68aca08SJayachandran B dx.core_mask = core_mask; 51092eb4f62SJeeja KP dx.dx_mask = SKL_IPC_D3_MASK; 51192eb4f62SJeeja KP 512e68aca08SJayachandran B dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n", 513e68aca08SJayachandran B dx.core_mask, dx.dx_mask); 514e68aca08SJayachandran B 515e68aca08SJayachandran B ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID, 516e68aca08SJayachandran B BXT_BASE_FW_MODULE_ID, &dx); 517e68aca08SJayachandran B if (ret < 0) 518e68aca08SJayachandran B dev_err(ctx->dev, 519e68aca08SJayachandran B "Failed to set DSP to D3:core id = %d;Continue reset\n", 520e68aca08SJayachandran B core_id); 521e68aca08SJayachandran B 522e68aca08SJayachandran B ret = skl_dsp_disable_core(ctx, core_mask); 52392eb4f62SJeeja KP if (ret < 0) { 524ecd286a9SColin Ian King dev_err(ctx->dev, "Failed to disable core %d\n", ret); 52592eb4f62SJeeja KP return ret; 52692eb4f62SJeeja KP } 527e68aca08SJayachandran B skl->cores.state[core_id] = SKL_DSP_RESET; 52892eb4f62SJeeja KP return 0; 52992eb4f62SJeeja KP } 53092eb4f62SJeeja KP 53192eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = { 53292eb4f62SJeeja KP .set_state_D0 = bxt_set_dsp_D0, 53392eb4f62SJeeja KP .set_state_D3 = bxt_set_dsp_D3, 5345bb4cd46SJayachandran B .set_state_D0i3 = bxt_schedule_dsp_D0i3, 5355bb4cd46SJayachandran B .set_state_D0i0 = bxt_set_dsp_D0i0, 53692eb4f62SJeeja KP .load_fw = bxt_load_base_firmware, 53792eb4f62SJeeja KP .get_fw_errcode = bxt_get_errorcode, 5381ef015e6SRamesh Babu .load_library = bxt_load_library, 53992eb4f62SJeeja KP }; 54092eb4f62SJeeja KP 54192eb4f62SJeeja KP static struct sst_ops skl_ops = { 54292eb4f62SJeeja KP .irq_handler = skl_dsp_sst_interrupt, 54392eb4f62SJeeja KP .write = sst_shim32_write, 54492eb4f62SJeeja KP .read = sst_shim32_read, 54592eb4f62SJeeja KP .ram_read = sst_memcpy_fromio_32, 54692eb4f62SJeeja KP .ram_write = sst_memcpy_toio_32, 54792eb4f62SJeeja KP .free = skl_dsp_free, 54892eb4f62SJeeja KP }; 54992eb4f62SJeeja KP 55092eb4f62SJeeja KP static struct sst_dsp_device skl_dev = { 55192eb4f62SJeeja KP .thread = skl_dsp_irq_thread_handler, 55292eb4f62SJeeja KP .ops = &skl_ops, 55392eb4f62SJeeja KP }; 55492eb4f62SJeeja KP 55592eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 55692eb4f62SJeeja KP const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 55792eb4f62SJeeja KP struct skl_sst **dsp) 55892eb4f62SJeeja KP { 55992eb4f62SJeeja KP struct skl_sst *skl; 56092eb4f62SJeeja KP struct sst_dsp *sst; 56192eb4f62SJeeja KP int ret; 56292eb4f62SJeeja KP 56392eb4f62SJeeja KP skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL); 56492eb4f62SJeeja KP if (skl == NULL) 56592eb4f62SJeeja KP return -ENOMEM; 56692eb4f62SJeeja KP 56792eb4f62SJeeja KP skl->dev = dev; 56892eb4f62SJeeja KP skl_dev.thread_context = skl; 5693467a64dSVinod Koul INIT_LIST_HEAD(&skl->uuid_list); 57092eb4f62SJeeja KP 57192eb4f62SJeeja KP skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq); 57292eb4f62SJeeja KP if (!skl->dsp) { 57392eb4f62SJeeja KP dev_err(skl->dev, "skl_dsp_ctx_init failed\n"); 57492eb4f62SJeeja KP return -ENODEV; 57592eb4f62SJeeja KP } 57692eb4f62SJeeja KP 57792eb4f62SJeeja KP sst = skl->dsp; 57892eb4f62SJeeja KP sst->fw_name = fw_name; 57992eb4f62SJeeja KP sst->dsp_ops = dsp_ops; 58092eb4f62SJeeja KP sst->fw_ops = bxt_fw_ops; 58192eb4f62SJeeja KP sst->addr.lpe = mmio_base; 58292eb4f62SJeeja KP sst->addr.shim = mmio_base; 58392eb4f62SJeeja KP 58492eb4f62SJeeja KP sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ), 58592eb4f62SJeeja KP SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ); 58692eb4f62SJeeja KP 587b914bb55SVinod Koul INIT_LIST_HEAD(&sst->module_list); 58892eb4f62SJeeja KP ret = skl_ipc_init(dev, skl); 58992eb4f62SJeeja KP if (ret) 59092eb4f62SJeeja KP return ret; 59192eb4f62SJeeja KP 592a83e3b4cSVinod Koul /* set the D0i3 check */ 593a83e3b4cSVinod Koul skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0; 594a83e3b4cSVinod Koul 595052f103cSJayachandran B skl->cores.count = 2; 59692eb4f62SJeeja KP skl->boot_complete = false; 59792eb4f62SJeeja KP init_waitqueue_head(&skl->boot_wait); 59878cdbbdaSVinod Koul skl->is_first_boot = true; 599a83e3b4cSVinod Koul INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3); 600a83e3b4cSVinod Koul skl->d0i3.state = SKL_DSP_D0I3_NONE; 60178cdbbdaSVinod Koul 60278cdbbdaSVinod Koul if (dsp) 60378cdbbdaSVinod Koul *dsp = skl; 60478cdbbdaSVinod Koul 60578cdbbdaSVinod Koul return 0; 60678cdbbdaSVinod Koul } 60778cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_dsp_init); 60878cdbbdaSVinod Koul 60978cdbbdaSVinod Koul int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx) 61078cdbbdaSVinod Koul { 61178cdbbdaSVinod Koul int ret; 61278cdbbdaSVinod Koul struct sst_dsp *sst = ctx->dsp; 61392eb4f62SJeeja KP 61492eb4f62SJeeja KP ret = sst->fw_ops.load_fw(sst); 61592eb4f62SJeeja KP if (ret < 0) { 616ecd286a9SColin Ian King dev_err(dev, "Load base fw failed: %x\n", ret); 61792eb4f62SJeeja KP return ret; 61892eb4f62SJeeja KP } 61992eb4f62SJeeja KP 620052f103cSJayachandran B skl_dsp_init_core_state(sst); 621052f103cSJayachandran B 622eee0e16fSJeeja KP if (ctx->lib_count > 1) { 623eee0e16fSJeeja KP ret = sst->fw_ops.load_library(sst, ctx->lib_info, 624eee0e16fSJeeja KP ctx->lib_count); 6251ef015e6SRamesh Babu if (ret < 0) { 626ecd286a9SColin Ian King dev_err(dev, "Load Library failed : %x\n", ret); 6271ef015e6SRamesh Babu return ret; 6281ef015e6SRamesh Babu } 6291ef015e6SRamesh Babu } 63078cdbbdaSVinod Koul ctx->is_first_boot = false; 63192eb4f62SJeeja KP 63292eb4f62SJeeja KP return 0; 63392eb4f62SJeeja KP } 63478cdbbdaSVinod Koul EXPORT_SYMBOL_GPL(bxt_sst_init_fw); 63592eb4f62SJeeja KP 63692eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx) 63792eb4f62SJeeja KP { 6383467a64dSVinod Koul skl_freeup_uuid_list(ctx); 63992eb4f62SJeeja KP skl_ipc_free(&ctx->ipc); 64092eb4f62SJeeja KP ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp); 64192eb4f62SJeeja KP 64292eb4f62SJeeja KP if (ctx->dsp->addr.lpe) 64392eb4f62SJeeja KP iounmap(ctx->dsp->addr.lpe); 64492eb4f62SJeeja KP 64592eb4f62SJeeja KP ctx->dsp->ops->free(ctx->dsp); 64692eb4f62SJeeja KP } 64792eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup); 64892eb4f62SJeeja KP 64992eb4f62SJeeja KP MODULE_LICENSE("GPL v2"); 65092eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver"); 651