xref: /openbmc/linux/sound/soc/intel/skylake/bxt-sst.c (revision 052f103c)
192eb4f62SJeeja KP /*
292eb4f62SJeeja KP  *  bxt-sst.c - DSP library functions for BXT platform
392eb4f62SJeeja KP  *
492eb4f62SJeeja KP  *  Copyright (C) 2015-16 Intel Corp
592eb4f62SJeeja KP  *  Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
692eb4f62SJeeja KP  *	   Jeeja KP <jeeja.kp@intel.com>
792eb4f62SJeeja KP  *
892eb4f62SJeeja KP  *  This program is free software; you can redistribute it and/or modify
992eb4f62SJeeja KP  *  it under the terms of the GNU General Public License as published by
1092eb4f62SJeeja KP  *  the Free Software Foundation; version 2 of the License.
1192eb4f62SJeeja KP  *
1292eb4f62SJeeja KP  *  This program is distributed in the hope that it will be useful, but
1392eb4f62SJeeja KP  *  WITHOUT ANY WARRANTY; without even the implied warranty of
1492eb4f62SJeeja KP  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
1592eb4f62SJeeja KP  *  General Public License for more details.
1692eb4f62SJeeja KP  */
1792eb4f62SJeeja KP 
1892eb4f62SJeeja KP #include <linux/module.h>
1992eb4f62SJeeja KP #include <linux/delay.h>
2092eb4f62SJeeja KP #include <linux/firmware.h>
2192eb4f62SJeeja KP #include <linux/device.h>
2292eb4f62SJeeja KP 
2392eb4f62SJeeja KP #include "../common/sst-dsp.h"
2492eb4f62SJeeja KP #include "../common/sst-dsp-priv.h"
2592eb4f62SJeeja KP #include "skl-sst-ipc.h"
2692eb4f62SJeeja KP 
2792eb4f62SJeeja KP #define BXT_BASEFW_TIMEOUT	3000
2892eb4f62SJeeja KP #define BXT_INIT_TIMEOUT	500
2992eb4f62SJeeja KP #define BXT_IPC_PURGE_FW	0x01004000
3092eb4f62SJeeja KP 
3192eb4f62SJeeja KP #define BXT_ROM_INIT		0x5
3292eb4f62SJeeja KP #define BXT_ADSP_SRAM0_BASE	0x80000
3392eb4f62SJeeja KP 
3492eb4f62SJeeja KP /* Firmware status window */
3592eb4f62SJeeja KP #define BXT_ADSP_FW_STATUS	BXT_ADSP_SRAM0_BASE
3692eb4f62SJeeja KP #define BXT_ADSP_ERROR_CODE     (BXT_ADSP_FW_STATUS + 0x4)
3792eb4f62SJeeja KP 
3892eb4f62SJeeja KP #define BXT_ADSP_SRAM1_BASE	0xA0000
3992eb4f62SJeeja KP 
4092eb4f62SJeeja KP static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
4192eb4f62SJeeja KP {
4292eb4f62SJeeja KP 	 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
4392eb4f62SJeeja KP }
4492eb4f62SJeeja KP 
4592eb4f62SJeeja KP static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
4692eb4f62SJeeja KP 			const void *fwdata, u32 fwsize)
4792eb4f62SJeeja KP {
4892eb4f62SJeeja KP 	int stream_tag, ret, i;
4992eb4f62SJeeja KP 	u32 reg;
5092eb4f62SJeeja KP 
5192eb4f62SJeeja KP 	stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
5292eb4f62SJeeja KP 	if (stream_tag < 0) {
5392eb4f62SJeeja KP 		dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
5492eb4f62SJeeja KP 				stream_tag);
5592eb4f62SJeeja KP 		return stream_tag;
5692eb4f62SJeeja KP 	}
5792eb4f62SJeeja KP 
5892eb4f62SJeeja KP 	ctx->dsp_ops.stream_tag = stream_tag;
5992eb4f62SJeeja KP 	memcpy(ctx->dmab.area, fwdata, fwsize);
6092eb4f62SJeeja KP 
61052f103cSJayachandran B 	ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK);
6292eb4f62SJeeja KP 	if (ret < 0) {
6392eb4f62SJeeja KP 		dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
642023576dSSenthilnathan Veppur 		goto base_fw_load_failed;
652023576dSSenthilnathan Veppur 	}
662023576dSSenthilnathan Veppur 
672023576dSSenthilnathan Veppur 	/* Purge FW request */
682023576dSSenthilnathan Veppur 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
692023576dSSenthilnathan Veppur 				(BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
702023576dSSenthilnathan Veppur 
71052f103cSJayachandran B 	ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
722023576dSSenthilnathan Veppur 	if (ret < 0) {
732023576dSSenthilnathan Veppur 		dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
7492eb4f62SJeeja KP 		ret = -EIO;
7592eb4f62SJeeja KP 		goto base_fw_load_failed;
7692eb4f62SJeeja KP 	}
7792eb4f62SJeeja KP 
7892eb4f62SJeeja KP 	for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
7992eb4f62SJeeja KP 		reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
8092eb4f62SJeeja KP 
8192eb4f62SJeeja KP 		if (reg & SKL_ADSP_REG_HIPCIE_DONE) {
8292eb4f62SJeeja KP 			sst_dsp_shim_update_bits_forced(ctx,
8392eb4f62SJeeja KP 					SKL_ADSP_REG_HIPCIE,
8492eb4f62SJeeja KP 					SKL_ADSP_REG_HIPCIE_DONE,
8592eb4f62SJeeja KP 					SKL_ADSP_REG_HIPCIE_DONE);
8692eb4f62SJeeja KP 			break;
8792eb4f62SJeeja KP 		}
8892eb4f62SJeeja KP 		mdelay(1);
8992eb4f62SJeeja KP 	}
9092eb4f62SJeeja KP 	if (!i) {
9192eb4f62SJeeja KP 		dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg);
9292eb4f62SJeeja KP 		sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE,
9392eb4f62SJeeja KP 				SKL_ADSP_REG_HIPCIE_DONE,
9492eb4f62SJeeja KP 				SKL_ADSP_REG_HIPCIE_DONE);
9592eb4f62SJeeja KP 	}
9692eb4f62SJeeja KP 
9792eb4f62SJeeja KP 	/* enable Interrupt */
9892eb4f62SJeeja KP 	skl_ipc_int_enable(ctx);
9992eb4f62SJeeja KP 	skl_ipc_op_int_enable(ctx);
10092eb4f62SJeeja KP 
10192eb4f62SJeeja KP 	for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
10292eb4f62SJeeja KP 		if (SKL_FW_INIT ==
10392eb4f62SJeeja KP 				(sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
10492eb4f62SJeeja KP 				SKL_FW_STS_MASK)) {
10592eb4f62SJeeja KP 
10692eb4f62SJeeja KP 			dev_info(ctx->dev, "ROM loaded, continue FW loading\n");
10792eb4f62SJeeja KP 			break;
10892eb4f62SJeeja KP 		}
10992eb4f62SJeeja KP 		mdelay(1);
11092eb4f62SJeeja KP 	}
11192eb4f62SJeeja KP 	if (!i) {
11292eb4f62SJeeja KP 		dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg);
11392eb4f62SJeeja KP 		ret = -EIO;
11492eb4f62SJeeja KP 		goto base_fw_load_failed;
11592eb4f62SJeeja KP 	}
11692eb4f62SJeeja KP 
11792eb4f62SJeeja KP 	return ret;
11892eb4f62SJeeja KP 
11992eb4f62SJeeja KP base_fw_load_failed:
12092eb4f62SJeeja KP 	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
121052f103cSJayachandran B 	skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
122052f103cSJayachandran B 	skl_dsp_disable_core(ctx, SKL_DSP_CORE_MASK(1));
12392eb4f62SJeeja KP 	return ret;
12492eb4f62SJeeja KP }
12592eb4f62SJeeja KP 
12692eb4f62SJeeja KP static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
12792eb4f62SJeeja KP {
12892eb4f62SJeeja KP 	int ret;
12992eb4f62SJeeja KP 
13092eb4f62SJeeja KP 	ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
13192eb4f62SJeeja KP 	ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
13292eb4f62SJeeja KP 			BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
13392eb4f62SJeeja KP 
13492eb4f62SJeeja KP 	ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
13592eb4f62SJeeja KP 	ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
13692eb4f62SJeeja KP 
13792eb4f62SJeeja KP 	return ret;
13892eb4f62SJeeja KP }
13992eb4f62SJeeja KP 
1403467a64dSVinod Koul #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
1413467a64dSVinod Koul 
14292eb4f62SJeeja KP static int bxt_load_base_firmware(struct sst_dsp *ctx)
14392eb4f62SJeeja KP {
144bf242d19SVinod Koul 	struct firmware stripped_fw;
14592eb4f62SJeeja KP 	struct skl_sst *skl = ctx->thread_context;
14692eb4f62SJeeja KP 	int ret;
14792eb4f62SJeeja KP 
148fdfa82eeSVinod Koul 	ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
14992eb4f62SJeeja KP 	if (ret < 0) {
15092eb4f62SJeeja KP 		dev_err(ctx->dev, "Request firmware failed %d\n", ret);
15192eb4f62SJeeja KP 		goto sst_load_base_firmware_failed;
15292eb4f62SJeeja KP 	}
15392eb4f62SJeeja KP 
154bf242d19SVinod Koul 	/* check for extended manifest */
155bf242d19SVinod Koul 	if (ctx->fw == NULL)
156bf242d19SVinod Koul 		goto sst_load_base_firmware_failed;
157bf242d19SVinod Koul 
1583467a64dSVinod Koul 	ret = snd_skl_parse_uuids(ctx, BXT_ADSP_FW_BIN_HDR_OFFSET);
1593467a64dSVinod Koul 	if (ret < 0)
1603467a64dSVinod Koul 		goto sst_load_base_firmware_failed;
161bf242d19SVinod Koul 
162bf242d19SVinod Koul 	stripped_fw.data = ctx->fw->data;
163bf242d19SVinod Koul 	stripped_fw.size = ctx->fw->size;
164bf242d19SVinod Koul 	skl_dsp_strip_extended_manifest(&stripped_fw);
165bf242d19SVinod Koul 
166bf242d19SVinod Koul 	ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
16792eb4f62SJeeja KP 	/* Retry Enabling core and ROM load. Retry seemed to help */
16892eb4f62SJeeja KP 	if (ret < 0) {
169bf242d19SVinod Koul 		ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
17092eb4f62SJeeja KP 		if (ret < 0) {
1712023576dSSenthilnathan Veppur 			dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
1722023576dSSenthilnathan Veppur 			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
1732023576dSSenthilnathan Veppur 			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
1742023576dSSenthilnathan Veppur 
17592eb4f62SJeeja KP 			dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
17692eb4f62SJeeja KP 			goto sst_load_base_firmware_failed;
17792eb4f62SJeeja KP 		}
17892eb4f62SJeeja KP 	}
17992eb4f62SJeeja KP 
18092eb4f62SJeeja KP 	ret = sst_transfer_fw_host_dma(ctx);
18192eb4f62SJeeja KP 	if (ret < 0) {
18292eb4f62SJeeja KP 		dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
18392eb4f62SJeeja KP 		dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
18492eb4f62SJeeja KP 			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
18592eb4f62SJeeja KP 			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
18692eb4f62SJeeja KP 
187052f103cSJayachandran B 		skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
18892eb4f62SJeeja KP 	} else {
18992eb4f62SJeeja KP 		dev_dbg(ctx->dev, "Firmware download successful\n");
19092eb4f62SJeeja KP 		ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
19192eb4f62SJeeja KP 					msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
19292eb4f62SJeeja KP 		if (ret == 0) {
19392eb4f62SJeeja KP 			dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
194052f103cSJayachandran B 			skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
19592eb4f62SJeeja KP 			ret = -EIO;
19692eb4f62SJeeja KP 		} else {
19792eb4f62SJeeja KP 			skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
19892eb4f62SJeeja KP 			ret = 0;
1991665c177SJayachandran B 			skl->fw_loaded = true;
20092eb4f62SJeeja KP 		}
20192eb4f62SJeeja KP 	}
20292eb4f62SJeeja KP 
20392eb4f62SJeeja KP sst_load_base_firmware_failed:
204fdfa82eeSVinod Koul 	release_firmware(ctx->fw);
20592eb4f62SJeeja KP 	return ret;
20692eb4f62SJeeja KP }
20792eb4f62SJeeja KP 
208052f103cSJayachandran B static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
20992eb4f62SJeeja KP {
21092eb4f62SJeeja KP 	struct skl_sst *skl = ctx->thread_context;
21192eb4f62SJeeja KP 	int ret;
21292eb4f62SJeeja KP 
21392eb4f62SJeeja KP 	skl->boot_complete = false;
21492eb4f62SJeeja KP 
2151665c177SJayachandran B 	if (skl->fw_loaded == false) {
2161665c177SJayachandran B 		dev_dbg(ctx->dev, "Re-loading fw\n");
2171665c177SJayachandran B 		ret = bxt_load_base_firmware(ctx);
2181665c177SJayachandran B 		if (ret < 0)
2191665c177SJayachandran B 			dev_err(ctx->dev, "reload fw failed: %d\n", ret);
2201665c177SJayachandran B 		return ret;
2211665c177SJayachandran B 	}
2221665c177SJayachandran B 
223052f103cSJayachandran B 	ret = skl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
22492eb4f62SJeeja KP 	if (ret < 0) {
22592eb4f62SJeeja KP 		dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret);
22692eb4f62SJeeja KP 		return ret;
22792eb4f62SJeeja KP 	}
22892eb4f62SJeeja KP 
22992eb4f62SJeeja KP 	/* enable interrupt */
23092eb4f62SJeeja KP 	skl_ipc_int_enable(ctx);
23192eb4f62SJeeja KP 	skl_ipc_op_int_enable(ctx);
23292eb4f62SJeeja KP 
23392eb4f62SJeeja KP 	ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
23492eb4f62SJeeja KP 					msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
23592eb4f62SJeeja KP 	if (ret == 0) {
23692eb4f62SJeeja KP 		dev_err(ctx->dev, "ipc: error DSP boot timeout\n");
23792eb4f62SJeeja KP 		dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
23892eb4f62SJeeja KP 			sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
23992eb4f62SJeeja KP 			sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
24092eb4f62SJeeja KP 		return -EIO;
24192eb4f62SJeeja KP 	}
24292eb4f62SJeeja KP 
24392eb4f62SJeeja KP 	skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
24492eb4f62SJeeja KP 	return 0;
24592eb4f62SJeeja KP }
24692eb4f62SJeeja KP 
247052f103cSJayachandran B static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
24892eb4f62SJeeja KP {
24992eb4f62SJeeja KP 	struct skl_ipc_dxstate_info dx;
25092eb4f62SJeeja KP 	struct skl_sst *skl = ctx->thread_context;
25192eb4f62SJeeja KP 	int ret = 0;
25292eb4f62SJeeja KP 
25392eb4f62SJeeja KP 	if (!is_skl_dsp_running(ctx))
25492eb4f62SJeeja KP 		return ret;
25592eb4f62SJeeja KP 
25692eb4f62SJeeja KP 	dx.core_mask = SKL_DSP_CORE0_MASK;
25792eb4f62SJeeja KP 	dx.dx_mask = SKL_IPC_D3_MASK;
25892eb4f62SJeeja KP 
25992eb4f62SJeeja KP 	ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
26092eb4f62SJeeja KP 				SKL_BASE_FW_MODULE_ID, &dx);
26192eb4f62SJeeja KP 	if (ret < 0) {
26292eb4f62SJeeja KP 		dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret);
26392eb4f62SJeeja KP 		return ret;
26492eb4f62SJeeja KP 	}
26592eb4f62SJeeja KP 
266052f103cSJayachandran B 	ret = skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
26792eb4f62SJeeja KP 	if (ret < 0) {
26892eb4f62SJeeja KP 		dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret);
26992eb4f62SJeeja KP 		ret = -EIO;
27092eb4f62SJeeja KP 	}
27192eb4f62SJeeja KP 
27292eb4f62SJeeja KP 	skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
27392eb4f62SJeeja KP 	return 0;
27492eb4f62SJeeja KP }
27592eb4f62SJeeja KP 
27692eb4f62SJeeja KP static struct skl_dsp_fw_ops bxt_fw_ops = {
27792eb4f62SJeeja KP 	.set_state_D0 = bxt_set_dsp_D0,
27892eb4f62SJeeja KP 	.set_state_D3 = bxt_set_dsp_D3,
27992eb4f62SJeeja KP 	.load_fw = bxt_load_base_firmware,
28092eb4f62SJeeja KP 	.get_fw_errcode = bxt_get_errorcode,
28192eb4f62SJeeja KP };
28292eb4f62SJeeja KP 
28392eb4f62SJeeja KP static struct sst_ops skl_ops = {
28492eb4f62SJeeja KP 	.irq_handler = skl_dsp_sst_interrupt,
28592eb4f62SJeeja KP 	.write = sst_shim32_write,
28692eb4f62SJeeja KP 	.read = sst_shim32_read,
28792eb4f62SJeeja KP 	.ram_read = sst_memcpy_fromio_32,
28892eb4f62SJeeja KP 	.ram_write = sst_memcpy_toio_32,
28992eb4f62SJeeja KP 	.free = skl_dsp_free,
29092eb4f62SJeeja KP };
29192eb4f62SJeeja KP 
29292eb4f62SJeeja KP static struct sst_dsp_device skl_dev = {
29392eb4f62SJeeja KP 	.thread = skl_dsp_irq_thread_handler,
29492eb4f62SJeeja KP 	.ops = &skl_ops,
29592eb4f62SJeeja KP };
29692eb4f62SJeeja KP 
29792eb4f62SJeeja KP int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
29892eb4f62SJeeja KP 			const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
29992eb4f62SJeeja KP 			struct skl_sst **dsp)
30092eb4f62SJeeja KP {
30192eb4f62SJeeja KP 	struct skl_sst *skl;
30292eb4f62SJeeja KP 	struct sst_dsp *sst;
30392eb4f62SJeeja KP 	int ret;
30492eb4f62SJeeja KP 
30592eb4f62SJeeja KP 	skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
30692eb4f62SJeeja KP 	if (skl == NULL)
30792eb4f62SJeeja KP 		return -ENOMEM;
30892eb4f62SJeeja KP 
30992eb4f62SJeeja KP 	skl->dev = dev;
31092eb4f62SJeeja KP 	skl_dev.thread_context = skl;
3113467a64dSVinod Koul 	INIT_LIST_HEAD(&skl->uuid_list);
31292eb4f62SJeeja KP 
31392eb4f62SJeeja KP 	skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
31492eb4f62SJeeja KP 	if (!skl->dsp) {
31592eb4f62SJeeja KP 		dev_err(skl->dev, "skl_dsp_ctx_init failed\n");
31692eb4f62SJeeja KP 		return -ENODEV;
31792eb4f62SJeeja KP 	}
31892eb4f62SJeeja KP 
31992eb4f62SJeeja KP 	sst = skl->dsp;
32092eb4f62SJeeja KP 	sst->fw_name = fw_name;
32192eb4f62SJeeja KP 	sst->dsp_ops = dsp_ops;
32292eb4f62SJeeja KP 	sst->fw_ops = bxt_fw_ops;
32392eb4f62SJeeja KP 	sst->addr.lpe = mmio_base;
32492eb4f62SJeeja KP 	sst->addr.shim = mmio_base;
32592eb4f62SJeeja KP 
32692eb4f62SJeeja KP 	sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
32792eb4f62SJeeja KP 			SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
32892eb4f62SJeeja KP 
32992eb4f62SJeeja KP 	ret = skl_ipc_init(dev, skl);
33092eb4f62SJeeja KP 	if (ret)
33192eb4f62SJeeja KP 		return ret;
33292eb4f62SJeeja KP 
333052f103cSJayachandran B 	skl->cores.count = 2;
33492eb4f62SJeeja KP 	skl->boot_complete = false;
33592eb4f62SJeeja KP 	init_waitqueue_head(&skl->boot_wait);
33692eb4f62SJeeja KP 
33792eb4f62SJeeja KP 	ret = sst->fw_ops.load_fw(sst);
33892eb4f62SJeeja KP 	if (ret < 0) {
33992eb4f62SJeeja KP 		dev_err(dev, "Load base fw failed: %x", ret);
34092eb4f62SJeeja KP 		return ret;
34192eb4f62SJeeja KP 	}
34292eb4f62SJeeja KP 
343052f103cSJayachandran B 	skl_dsp_init_core_state(sst);
344052f103cSJayachandran B 
34592eb4f62SJeeja KP 	if (dsp)
34692eb4f62SJeeja KP 		*dsp = skl;
34792eb4f62SJeeja KP 
34892eb4f62SJeeja KP 	return 0;
34992eb4f62SJeeja KP }
35092eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
35192eb4f62SJeeja KP 
35292eb4f62SJeeja KP 
35392eb4f62SJeeja KP void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
35492eb4f62SJeeja KP {
3553467a64dSVinod Koul 	skl_freeup_uuid_list(ctx);
35692eb4f62SJeeja KP 	skl_ipc_free(&ctx->ipc);
35792eb4f62SJeeja KP 	ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
35892eb4f62SJeeja KP 
35992eb4f62SJeeja KP 	if (ctx->dsp->addr.lpe)
36092eb4f62SJeeja KP 		iounmap(ctx->dsp->addr.lpe);
36192eb4f62SJeeja KP 
36292eb4f62SJeeja KP 	ctx->dsp->ops->free(ctx->dsp);
36392eb4f62SJeeja KP }
36492eb4f62SJeeja KP EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
36592eb4f62SJeeja KP 
36692eb4f62SJeeja KP MODULE_LICENSE("GPL v2");
36792eb4f62SJeeja KP MODULE_DESCRIPTION("Intel Broxton IPC driver");
368