1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (C) 2020 Intel Corporation. 4 // 5 // Intel KeemBay Platform driver. 6 // 7 8 #include <linux/bitrev.h> 9 #include <linux/clk.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <sound/dmaengine_pcm.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 #include "kmb_platform.h" 20 21 #define PERIODS_MIN 2 22 #define PERIODS_MAX 48 23 #define PERIOD_BYTES_MIN 4096 24 #define BUFFER_BYTES_MAX (PERIODS_MAX * PERIOD_BYTES_MIN) 25 #define TDM_OPERATION 5 26 #define I2S_OPERATION 0 27 #define DATA_WIDTH_CONFIG_BIT 6 28 #define TDM_CHANNEL_CONFIG_BIT 3 29 30 static const struct snd_pcm_hardware kmb_pcm_hardware = { 31 .info = SNDRV_PCM_INFO_INTERLEAVED | 32 SNDRV_PCM_INFO_MMAP | 33 SNDRV_PCM_INFO_MMAP_VALID | 34 SNDRV_PCM_INFO_BATCH | 35 SNDRV_PCM_INFO_BLOCK_TRANSFER, 36 .rates = SNDRV_PCM_RATE_8000 | 37 SNDRV_PCM_RATE_16000 | 38 SNDRV_PCM_RATE_48000, 39 .rate_min = 8000, 40 .rate_max = 48000, 41 .formats = SNDRV_PCM_FMTBIT_S16_LE | 42 SNDRV_PCM_FMTBIT_S24_LE | 43 SNDRV_PCM_FMTBIT_S32_LE | 44 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 45 .channels_min = 2, 46 .channels_max = 2, 47 .buffer_bytes_max = BUFFER_BYTES_MAX, 48 .period_bytes_min = PERIOD_BYTES_MIN, 49 .period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN, 50 .periods_min = PERIODS_MIN, 51 .periods_max = PERIODS_MAX, 52 .fifo_size = 16, 53 }; 54 55 /* 56 * Convert to ADV7511 HDMI hardware format. 57 * ADV7511 HDMI chip need parity bit replaced by block start bit and 58 * with the preamble bits left out. 59 * ALSA IEC958 subframe format: 60 * bit 0-3 = preamble (0x8 = block start) 61 * 4-7 = AUX (=0) 62 * 8-27 = audio data (without AUX if 24bit sample) 63 * 28 = validity 64 * 29 = user data 65 * 30 = channel status 66 * 31 = parity 67 * 68 * ADV7511 IEC958 subframe format: 69 * bit 0-23 = audio data 70 * 24 = validity 71 * 25 = user data 72 * 26 = channel status 73 * 27 = block start 74 * 28-31 = 0 75 * MSB to LSB bit reverse by software as hardware not supporting it. 76 */ 77 static void hdmi_reformat_iec958(struct snd_pcm_runtime *runtime, 78 struct kmb_i2s_info *kmb_i2s, 79 unsigned int tx_ptr) 80 { 81 u32(*buf)[2] = (void *)runtime->dma_area; 82 unsigned long temp; 83 u32 i, j, sample; 84 85 for (i = 0; i < kmb_i2s->fifo_th; i++) { 86 j = 0; 87 do { 88 temp = buf[tx_ptr][j]; 89 /* Replace parity with block start*/ 90 assign_bit(31, &temp, (BIT(3) & temp)); 91 sample = bitrev32(temp); 92 buf[tx_ptr][j] = sample << 4; 93 j++; 94 } while (j < 2); 95 tx_ptr++; 96 } 97 } 98 99 static unsigned int kmb_pcm_tx_fn(struct kmb_i2s_info *kmb_i2s, 100 struct snd_pcm_runtime *runtime, 101 unsigned int tx_ptr, bool *period_elapsed) 102 { 103 unsigned int period_pos = tx_ptr % runtime->period_size; 104 void __iomem *i2s_base = kmb_i2s->i2s_base; 105 void *buf = runtime->dma_area; 106 int i; 107 108 /* KMB i2s uses two separate L/R FIFO */ 109 for (i = 0; i < kmb_i2s->fifo_th; i++) { 110 if (kmb_i2s->config.data_width == 16) { 111 writel(((u16(*)[2])buf)[tx_ptr][0], i2s_base + LRBR_LTHR(0)); 112 writel(((u16(*)[2])buf)[tx_ptr][1], i2s_base + RRBR_RTHR(0)); 113 } else { 114 if (kmb_i2s->iec958_fmt) 115 hdmi_reformat_iec958(runtime, kmb_i2s, tx_ptr); 116 writel(((u32(*)[2])buf)[tx_ptr][0], i2s_base + LRBR_LTHR(0)); 117 writel(((u32(*)[2])buf)[tx_ptr][1], i2s_base + RRBR_RTHR(0)); 118 } 119 120 period_pos++; 121 122 if (++tx_ptr >= runtime->buffer_size) 123 tx_ptr = 0; 124 } 125 126 *period_elapsed = period_pos >= runtime->period_size; 127 128 return tx_ptr; 129 } 130 131 static unsigned int kmb_pcm_rx_fn(struct kmb_i2s_info *kmb_i2s, 132 struct snd_pcm_runtime *runtime, 133 unsigned int rx_ptr, bool *period_elapsed) 134 { 135 unsigned int period_pos = rx_ptr % runtime->period_size; 136 void __iomem *i2s_base = kmb_i2s->i2s_base; 137 int chan = kmb_i2s->config.chan_nr; 138 void *buf = runtime->dma_area; 139 int i, j; 140 141 /* KMB i2s uses two separate L/R FIFO */ 142 for (i = 0; i < kmb_i2s->fifo_th; i++) { 143 for (j = 0; j < chan / 2; j++) { 144 if (kmb_i2s->config.data_width == 16) { 145 ((u16 *)buf)[rx_ptr * chan + (j * 2)] = 146 readl(i2s_base + LRBR_LTHR(j)); 147 ((u16 *)buf)[rx_ptr * chan + ((j * 2) + 1)] = 148 readl(i2s_base + RRBR_RTHR(j)); 149 } else { 150 ((u32 *)buf)[rx_ptr * chan + (j * 2)] = 151 readl(i2s_base + LRBR_LTHR(j)); 152 ((u32 *)buf)[rx_ptr * chan + ((j * 2) + 1)] = 153 readl(i2s_base + RRBR_RTHR(j)); 154 } 155 } 156 period_pos++; 157 158 if (++rx_ptr >= runtime->buffer_size) 159 rx_ptr = 0; 160 } 161 162 *period_elapsed = period_pos >= runtime->period_size; 163 164 return rx_ptr; 165 } 166 167 static inline void kmb_i2s_disable_channels(struct kmb_i2s_info *kmb_i2s, 168 u32 stream) 169 { 170 u32 i; 171 172 /* Disable all channels regardless of configuration*/ 173 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 174 for (i = 0; i < MAX_ISR; i++) 175 writel(0, kmb_i2s->i2s_base + TER(i)); 176 } else { 177 for (i = 0; i < MAX_ISR; i++) 178 writel(0, kmb_i2s->i2s_base + RER(i)); 179 } 180 } 181 182 static inline void kmb_i2s_clear_irqs(struct kmb_i2s_info *kmb_i2s, u32 stream) 183 { 184 struct i2s_clk_config_data *config = &kmb_i2s->config; 185 u32 i; 186 187 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 188 for (i = 0; i < config->chan_nr / 2; i++) 189 readl(kmb_i2s->i2s_base + TOR(i)); 190 } else { 191 for (i = 0; i < config->chan_nr / 2; i++) 192 readl(kmb_i2s->i2s_base + ROR(i)); 193 } 194 } 195 196 static inline void kmb_i2s_irq_trigger(struct kmb_i2s_info *kmb_i2s, 197 u32 stream, int chan_nr, bool trigger) 198 { 199 u32 i, irq; 200 u32 flag; 201 202 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 203 flag = TX_INT_FLAG; 204 else 205 flag = RX_INT_FLAG; 206 207 for (i = 0; i < chan_nr / 2; i++) { 208 irq = readl(kmb_i2s->i2s_base + IMR(i)); 209 210 if (trigger) 211 irq = irq & ~flag; 212 else 213 irq = irq | flag; 214 215 writel(irq, kmb_i2s->i2s_base + IMR(i)); 216 } 217 } 218 219 static void kmb_pcm_operation(struct kmb_i2s_info *kmb_i2s, bool playback) 220 { 221 struct snd_pcm_substream *substream; 222 bool period_elapsed; 223 unsigned int new_ptr; 224 unsigned int ptr; 225 226 if (playback) 227 substream = kmb_i2s->tx_substream; 228 else 229 substream = kmb_i2s->rx_substream; 230 231 if (!substream || !snd_pcm_running(substream)) 232 return; 233 234 if (playback) { 235 ptr = kmb_i2s->tx_ptr; 236 new_ptr = kmb_pcm_tx_fn(kmb_i2s, substream->runtime, 237 ptr, &period_elapsed); 238 cmpxchg(&kmb_i2s->tx_ptr, ptr, new_ptr); 239 } else { 240 ptr = kmb_i2s->rx_ptr; 241 new_ptr = kmb_pcm_rx_fn(kmb_i2s, substream->runtime, 242 ptr, &period_elapsed); 243 cmpxchg(&kmb_i2s->rx_ptr, ptr, new_ptr); 244 } 245 246 if (period_elapsed) 247 snd_pcm_period_elapsed(substream); 248 } 249 250 static int kmb_pcm_open(struct snd_soc_component *component, 251 struct snd_pcm_substream *substream) 252 { 253 struct snd_pcm_runtime *runtime = substream->runtime; 254 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 255 struct kmb_i2s_info *kmb_i2s; 256 257 kmb_i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 258 snd_soc_set_runtime_hwparams(substream, &kmb_pcm_hardware); 259 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 260 runtime->private_data = kmb_i2s; 261 262 return 0; 263 } 264 265 static int kmb_pcm_trigger(struct snd_soc_component *component, 266 struct snd_pcm_substream *substream, int cmd) 267 { 268 struct snd_pcm_runtime *runtime = substream->runtime; 269 struct kmb_i2s_info *kmb_i2s = runtime->private_data; 270 271 switch (cmd) { 272 case SNDRV_PCM_TRIGGER_START: 273 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 274 kmb_i2s->tx_ptr = 0; 275 kmb_i2s->tx_substream = substream; 276 } else { 277 kmb_i2s->rx_ptr = 0; 278 kmb_i2s->rx_substream = substream; 279 } 280 break; 281 case SNDRV_PCM_TRIGGER_STOP: 282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 283 kmb_i2s->tx_substream = NULL; 284 else 285 kmb_i2s->rx_substream = NULL; 286 kmb_i2s->iec958_fmt = false; 287 break; 288 default: 289 return -EINVAL; 290 } 291 292 return 0; 293 } 294 295 static irqreturn_t kmb_i2s_irq_handler(int irq, void *dev_id) 296 { 297 struct kmb_i2s_info *kmb_i2s = dev_id; 298 struct i2s_clk_config_data *config = &kmb_i2s->config; 299 irqreturn_t ret = IRQ_NONE; 300 u32 tx_enabled = 0; 301 u32 isr[4]; 302 int i; 303 304 for (i = 0; i < config->chan_nr / 2; i++) 305 isr[i] = readl(kmb_i2s->i2s_base + ISR(i)); 306 307 kmb_i2s_clear_irqs(kmb_i2s, SNDRV_PCM_STREAM_PLAYBACK); 308 kmb_i2s_clear_irqs(kmb_i2s, SNDRV_PCM_STREAM_CAPTURE); 309 /* Only check TX interrupt if TX is active */ 310 tx_enabled = readl(kmb_i2s->i2s_base + ITER); 311 312 /* 313 * Data available. Retrieve samples from FIFO 314 */ 315 316 /* 317 * 8 channel audio will have isr[0..2] triggered, 318 * reading the specific isr based on the audio configuration, 319 * to avoid reading the buffers too early. 320 */ 321 switch (config->chan_nr) { 322 case 2: 323 if (isr[0] & ISR_RXDA) 324 kmb_pcm_operation(kmb_i2s, false); 325 ret = IRQ_HANDLED; 326 break; 327 case 4: 328 if (isr[1] & ISR_RXDA) 329 kmb_pcm_operation(kmb_i2s, false); 330 ret = IRQ_HANDLED; 331 break; 332 case 8: 333 if (isr[3] & ISR_RXDA) 334 kmb_pcm_operation(kmb_i2s, false); 335 ret = IRQ_HANDLED; 336 break; 337 } 338 339 for (i = 0; i < config->chan_nr / 2; i++) { 340 /* 341 * Check if TX fifo is empty. If empty fill FIFO with samples 342 */ 343 if ((isr[i] & ISR_TXFE) && tx_enabled) { 344 kmb_pcm_operation(kmb_i2s, true); 345 ret = IRQ_HANDLED; 346 } 347 348 /* Error Handling: TX */ 349 if (isr[i] & ISR_TXFO) { 350 dev_dbg(kmb_i2s->dev, "TX overrun (ch_id=%d)\n", i); 351 ret = IRQ_HANDLED; 352 } 353 /* Error Handling: RX */ 354 if (isr[i] & ISR_RXFO) { 355 dev_dbg(kmb_i2s->dev, "RX overrun (ch_id=%d)\n", i); 356 ret = IRQ_HANDLED; 357 } 358 } 359 360 return ret; 361 } 362 363 static int kmb_platform_pcm_new(struct snd_soc_component *component, 364 struct snd_soc_pcm_runtime *soc_runtime) 365 { 366 size_t size = kmb_pcm_hardware.buffer_bytes_max; 367 /* Use SNDRV_DMA_TYPE_CONTINUOUS as KMB doesn't use PCI sg buffer */ 368 snd_pcm_set_managed_buffer_all(soc_runtime->pcm, 369 SNDRV_DMA_TYPE_CONTINUOUS, 370 NULL, size, size); 371 return 0; 372 } 373 374 static snd_pcm_uframes_t kmb_pcm_pointer(struct snd_soc_component *component, 375 struct snd_pcm_substream *substream) 376 { 377 struct snd_pcm_runtime *runtime = substream->runtime; 378 struct kmb_i2s_info *kmb_i2s = runtime->private_data; 379 snd_pcm_uframes_t pos; 380 381 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 382 pos = kmb_i2s->tx_ptr; 383 else 384 pos = kmb_i2s->rx_ptr; 385 386 return pos < runtime->buffer_size ? pos : 0; 387 } 388 389 static const struct snd_soc_component_driver kmb_component = { 390 .name = "kmb", 391 .pcm_construct = kmb_platform_pcm_new, 392 .open = kmb_pcm_open, 393 .trigger = kmb_pcm_trigger, 394 .pointer = kmb_pcm_pointer, 395 }; 396 397 static const struct snd_soc_component_driver kmb_component_dma = { 398 .name = "kmb", 399 }; 400 401 static int kmb_probe(struct snd_soc_dai *cpu_dai) 402 { 403 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 404 405 if (kmb_i2s->use_pio) 406 return 0; 407 408 snd_soc_dai_init_dma_data(cpu_dai, &kmb_i2s->play_dma_data, 409 &kmb_i2s->capture_dma_data); 410 411 return 0; 412 } 413 414 static inline void kmb_i2s_enable_dma(struct kmb_i2s_info *kmb_i2s, u32 stream) 415 { 416 u32 dma_reg; 417 418 dma_reg = readl(kmb_i2s->i2s_base + I2S_DMACR); 419 /* Enable DMA handshake for stream */ 420 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 421 dma_reg |= I2S_DMAEN_TXBLOCK; 422 else 423 dma_reg |= I2S_DMAEN_RXBLOCK; 424 425 writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR); 426 } 427 428 static inline void kmb_i2s_disable_dma(struct kmb_i2s_info *kmb_i2s, u32 stream) 429 { 430 u32 dma_reg; 431 432 dma_reg = readl(kmb_i2s->i2s_base + I2S_DMACR); 433 /* Disable DMA handshake for stream */ 434 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 435 dma_reg &= ~I2S_DMAEN_TXBLOCK; 436 writel(1, kmb_i2s->i2s_base + I2S_RTXDMA); 437 } else { 438 dma_reg &= ~I2S_DMAEN_RXBLOCK; 439 writel(1, kmb_i2s->i2s_base + I2S_RRXDMA); 440 } 441 writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR); 442 } 443 444 static void kmb_i2s_start(struct kmb_i2s_info *kmb_i2s, 445 struct snd_pcm_substream *substream) 446 { 447 struct i2s_clk_config_data *config = &kmb_i2s->config; 448 449 /* I2S Programming sequence in Keem_Bay_VPU_DB_v1.1 */ 450 writel(1, kmb_i2s->i2s_base + IER); 451 452 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 453 writel(1, kmb_i2s->i2s_base + ITER); 454 else 455 writel(1, kmb_i2s->i2s_base + IRER); 456 457 if (kmb_i2s->use_pio) 458 kmb_i2s_irq_trigger(kmb_i2s, substream->stream, 459 config->chan_nr, true); 460 else 461 kmb_i2s_enable_dma(kmb_i2s, substream->stream); 462 463 if (kmb_i2s->clock_provider) 464 writel(1, kmb_i2s->i2s_base + CER); 465 else 466 writel(0, kmb_i2s->i2s_base + CER); 467 } 468 469 static void kmb_i2s_stop(struct kmb_i2s_info *kmb_i2s, 470 struct snd_pcm_substream *substream) 471 { 472 /* I2S Programming sequence in Keem_Bay_VPU_DB_v1.1 */ 473 kmb_i2s_clear_irqs(kmb_i2s, substream->stream); 474 475 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 476 writel(0, kmb_i2s->i2s_base + ITER); 477 else 478 writel(0, kmb_i2s->i2s_base + IRER); 479 480 kmb_i2s_irq_trigger(kmb_i2s, substream->stream, 8, false); 481 482 if (!kmb_i2s->active) { 483 writel(0, kmb_i2s->i2s_base + CER); 484 writel(0, kmb_i2s->i2s_base + IER); 485 } 486 } 487 488 static void kmb_disable_clk(void *clk) 489 { 490 clk_disable_unprepare(clk); 491 } 492 493 static int kmb_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 494 { 495 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 496 int ret; 497 498 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 499 case SND_SOC_DAIFMT_CBP_CFP: 500 kmb_i2s->clock_provider = false; 501 ret = 0; 502 break; 503 case SND_SOC_DAIFMT_CBC_CFC: 504 writel(CLOCK_PROVIDER_MODE, kmb_i2s->pss_base + I2S_GEN_CFG_0); 505 506 ret = clk_prepare_enable(kmb_i2s->clk_i2s); 507 if (ret < 0) 508 return ret; 509 510 ret = devm_add_action_or_reset(kmb_i2s->dev, kmb_disable_clk, 511 kmb_i2s->clk_i2s); 512 if (ret) 513 return ret; 514 515 kmb_i2s->clock_provider = true; 516 break; 517 default: 518 return -EINVAL; 519 } 520 521 return ret; 522 } 523 524 static int kmb_dai_trigger(struct snd_pcm_substream *substream, 525 int cmd, struct snd_soc_dai *cpu_dai) 526 { 527 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 528 529 switch (cmd) { 530 case SNDRV_PCM_TRIGGER_START: 531 /* Keep track of i2s activity before turn off 532 * the i2s interface 533 */ 534 kmb_i2s->active++; 535 kmb_i2s_start(kmb_i2s, substream); 536 break; 537 case SNDRV_PCM_TRIGGER_STOP: 538 kmb_i2s->active--; 539 if (kmb_i2s->use_pio) 540 kmb_i2s_stop(kmb_i2s, substream); 541 break; 542 default: 543 return -EINVAL; 544 } 545 546 return 0; 547 } 548 549 static void kmb_i2s_config(struct kmb_i2s_info *kmb_i2s, int stream) 550 { 551 struct i2s_clk_config_data *config = &kmb_i2s->config; 552 u32 ch_reg; 553 554 kmb_i2s_disable_channels(kmb_i2s, stream); 555 556 for (ch_reg = 0; ch_reg < config->chan_nr / 2; ch_reg++) { 557 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 558 writel(kmb_i2s->xfer_resolution, 559 kmb_i2s->i2s_base + TCR(ch_reg)); 560 561 writel(kmb_i2s->fifo_th - 1, 562 kmb_i2s->i2s_base + TFCR(ch_reg)); 563 564 writel(1, kmb_i2s->i2s_base + TER(ch_reg)); 565 } else { 566 writel(kmb_i2s->xfer_resolution, 567 kmb_i2s->i2s_base + RCR(ch_reg)); 568 569 writel(kmb_i2s->fifo_th - 1, 570 kmb_i2s->i2s_base + RFCR(ch_reg)); 571 572 writel(1, kmb_i2s->i2s_base + RER(ch_reg)); 573 } 574 } 575 } 576 577 static int kmb_dai_hw_params(struct snd_pcm_substream *substream, 578 struct snd_pcm_hw_params *hw_params, 579 struct snd_soc_dai *cpu_dai) 580 { 581 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 582 struct i2s_clk_config_data *config = &kmb_i2s->config; 583 u32 write_val; 584 int ret; 585 586 switch (params_format(hw_params)) { 587 case SNDRV_PCM_FORMAT_S16_LE: 588 config->data_width = 16; 589 kmb_i2s->ccr = 0x00; 590 kmb_i2s->xfer_resolution = 0x02; 591 kmb_i2s->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 592 kmb_i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 593 break; 594 case SNDRV_PCM_FORMAT_S24_LE: 595 config->data_width = 32; 596 kmb_i2s->ccr = 0x14; 597 kmb_i2s->xfer_resolution = 0x05; 598 kmb_i2s->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 599 kmb_i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 600 break; 601 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 602 kmb_i2s->iec958_fmt = true; 603 fallthrough; 604 case SNDRV_PCM_FORMAT_S32_LE: 605 config->data_width = 32; 606 kmb_i2s->ccr = 0x10; 607 kmb_i2s->xfer_resolution = 0x05; 608 kmb_i2s->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 609 kmb_i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 610 break; 611 default: 612 dev_err(kmb_i2s->dev, "kmb: unsupported PCM fmt"); 613 return -EINVAL; 614 } 615 616 config->chan_nr = params_channels(hw_params); 617 618 switch (config->chan_nr) { 619 case 8: 620 case 4: 621 /* 622 * Platform is not capable of providing clocks for 623 * multi channel audio 624 */ 625 if (kmb_i2s->clock_provider) 626 return -EINVAL; 627 628 write_val = ((config->chan_nr / 2) << TDM_CHANNEL_CONFIG_BIT) | 629 (config->data_width << DATA_WIDTH_CONFIG_BIT) | 630 TDM_OPERATION; 631 632 writel(write_val, kmb_i2s->pss_base + I2S_GEN_CFG_0); 633 break; 634 case 2: 635 /* 636 * Platform is only capable of providing clocks need for 637 * 2 channel master mode 638 */ 639 if (!(kmb_i2s->clock_provider)) 640 return -EINVAL; 641 642 write_val = ((config->chan_nr / 2) << TDM_CHANNEL_CONFIG_BIT) | 643 (config->data_width << DATA_WIDTH_CONFIG_BIT) | 644 CLOCK_PROVIDER_MODE | I2S_OPERATION; 645 646 writel(write_val, kmb_i2s->pss_base + I2S_GEN_CFG_0); 647 break; 648 default: 649 dev_dbg(kmb_i2s->dev, "channel not supported\n"); 650 return -EINVAL; 651 } 652 653 kmb_i2s_config(kmb_i2s, substream->stream); 654 655 writel(kmb_i2s->ccr, kmb_i2s->i2s_base + CCR); 656 657 config->sample_rate = params_rate(hw_params); 658 659 if (kmb_i2s->clock_provider) { 660 /* Only 2 ch supported in Master mode */ 661 u32 bitclk = config->sample_rate * config->data_width * 2; 662 663 ret = clk_set_rate(kmb_i2s->clk_i2s, bitclk); 664 if (ret) { 665 dev_err(kmb_i2s->dev, 666 "Can't set I2S clock rate: %d\n", ret); 667 return ret; 668 } 669 } 670 671 return 0; 672 } 673 674 static int kmb_dai_prepare(struct snd_pcm_substream *substream, 675 struct snd_soc_dai *cpu_dai) 676 { 677 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 678 679 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 680 writel(1, kmb_i2s->i2s_base + TXFFR); 681 else 682 writel(1, kmb_i2s->i2s_base + RXFFR); 683 684 return 0; 685 } 686 687 static int kmb_dai_startup(struct snd_pcm_substream *substream, 688 struct snd_soc_dai *cpu_dai) 689 { 690 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 691 struct snd_dmaengine_dai_dma_data *dma_data; 692 693 if (kmb_i2s->use_pio) 694 return 0; 695 696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 697 dma_data = &kmb_i2s->play_dma_data; 698 else 699 dma_data = &kmb_i2s->capture_dma_data; 700 701 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); 702 703 return 0; 704 } 705 706 static int kmb_dai_hw_free(struct snd_pcm_substream *substream, 707 struct snd_soc_dai *cpu_dai) 708 { 709 struct kmb_i2s_info *kmb_i2s = snd_soc_dai_get_drvdata(cpu_dai); 710 /* I2S Programming sequence in Keem_Bay_VPU_DB_v1.1 */ 711 if (kmb_i2s->use_pio) 712 kmb_i2s_clear_irqs(kmb_i2s, substream->stream); 713 714 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 715 writel(0, kmb_i2s->i2s_base + ITER); 716 else 717 writel(0, kmb_i2s->i2s_base + IRER); 718 719 if (kmb_i2s->use_pio) 720 kmb_i2s_irq_trigger(kmb_i2s, substream->stream, 8, false); 721 else 722 kmb_i2s_disable_dma(kmb_i2s, substream->stream); 723 724 if (!kmb_i2s->active) { 725 writel(0, kmb_i2s->i2s_base + CER); 726 writel(0, kmb_i2s->i2s_base + IER); 727 } 728 729 return 0; 730 } 731 732 static struct snd_soc_dai_ops kmb_dai_ops = { 733 .startup = kmb_dai_startup, 734 .trigger = kmb_dai_trigger, 735 .hw_params = kmb_dai_hw_params, 736 .hw_free = kmb_dai_hw_free, 737 .prepare = kmb_dai_prepare, 738 .set_fmt = kmb_set_dai_fmt, 739 }; 740 741 static struct snd_soc_dai_driver intel_kmb_hdmi_dai[] = { 742 { 743 .name = "intel_kmb_hdmi_i2s", 744 .playback = { 745 .channels_min = 2, 746 .channels_max = 2, 747 .rates = SNDRV_PCM_RATE_48000, 748 .rate_min = 48000, 749 .rate_max = 48000, 750 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 751 SNDRV_PCM_FMTBIT_S24_LE | 752 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE), 753 }, 754 .ops = &kmb_dai_ops, 755 .probe = kmb_probe, 756 }, 757 }; 758 759 static struct snd_soc_dai_driver intel_kmb_i2s_dai[] = { 760 { 761 .name = "intel_kmb_i2s", 762 .playback = { 763 .channels_min = 2, 764 .channels_max = 2, 765 .rates = SNDRV_PCM_RATE_8000 | 766 SNDRV_PCM_RATE_16000 | 767 SNDRV_PCM_RATE_48000, 768 .rate_min = 8000, 769 .rate_max = 48000, 770 .formats = (SNDRV_PCM_FMTBIT_S32_LE | 771 SNDRV_PCM_FMTBIT_S24_LE | 772 SNDRV_PCM_FMTBIT_S16_LE), 773 }, 774 .capture = { 775 .channels_min = 2, 776 .channels_max = 2, 777 .rates = SNDRV_PCM_RATE_8000 | 778 SNDRV_PCM_RATE_16000 | 779 SNDRV_PCM_RATE_48000, 780 .rate_min = 8000, 781 .rate_max = 48000, 782 .formats = (SNDRV_PCM_FMTBIT_S32_LE | 783 SNDRV_PCM_FMTBIT_S24_LE | 784 SNDRV_PCM_FMTBIT_S16_LE), 785 }, 786 .ops = &kmb_dai_ops, 787 .probe = kmb_probe, 788 }, 789 }; 790 791 static struct snd_soc_dai_driver intel_kmb_tdm_dai[] = { 792 { 793 .name = "intel_kmb_tdm", 794 .capture = { 795 .channels_min = 4, 796 .channels_max = 8, 797 .rates = SNDRV_PCM_RATE_8000 | 798 SNDRV_PCM_RATE_16000 | 799 SNDRV_PCM_RATE_48000, 800 .rate_min = 8000, 801 .rate_max = 48000, 802 .formats = (SNDRV_PCM_FMTBIT_S32_LE | 803 SNDRV_PCM_FMTBIT_S24_LE | 804 SNDRV_PCM_FMTBIT_S16_LE), 805 }, 806 .ops = &kmb_dai_ops, 807 .probe = kmb_probe, 808 }, 809 }; 810 811 static const struct of_device_id kmb_plat_of_match[] = { 812 { .compatible = "intel,keembay-i2s", .data = &intel_kmb_i2s_dai}, 813 { .compatible = "intel,keembay-hdmi-i2s", .data = &intel_kmb_hdmi_dai}, 814 { .compatible = "intel,keembay-tdm", .data = &intel_kmb_tdm_dai}, 815 {} 816 }; 817 818 static int kmb_plat_dai_probe(struct platform_device *pdev) 819 { 820 struct device_node *np = pdev->dev.of_node; 821 struct snd_soc_dai_driver *kmb_i2s_dai; 822 const struct of_device_id *match; 823 struct device *dev = &pdev->dev; 824 struct kmb_i2s_info *kmb_i2s; 825 struct resource *res; 826 int ret, irq; 827 u32 comp1_reg; 828 829 kmb_i2s = devm_kzalloc(dev, sizeof(*kmb_i2s), GFP_KERNEL); 830 if (!kmb_i2s) 831 return -ENOMEM; 832 833 kmb_i2s_dai = devm_kzalloc(dev, sizeof(*kmb_i2s_dai), GFP_KERNEL); 834 if (!kmb_i2s_dai) 835 return -ENOMEM; 836 837 match = of_match_device(kmb_plat_of_match, &pdev->dev); 838 if (!match) { 839 dev_err(&pdev->dev, "Error: No device match found\n"); 840 return -ENODEV; 841 } 842 kmb_i2s_dai = (struct snd_soc_dai_driver *) match->data; 843 844 /* Prepare the related clocks */ 845 kmb_i2s->clk_apb = devm_clk_get(dev, "apb_clk"); 846 if (IS_ERR(kmb_i2s->clk_apb)) { 847 dev_err(dev, "Failed to get apb clock\n"); 848 return PTR_ERR(kmb_i2s->clk_apb); 849 } 850 851 ret = clk_prepare_enable(kmb_i2s->clk_apb); 852 if (ret < 0) 853 return ret; 854 855 ret = devm_add_action_or_reset(dev, kmb_disable_clk, kmb_i2s->clk_apb); 856 if (ret) { 857 dev_err(dev, "Failed to add clk_apb reset action\n"); 858 return ret; 859 } 860 861 kmb_i2s->clk_i2s = devm_clk_get(dev, "osc"); 862 if (IS_ERR(kmb_i2s->clk_i2s)) { 863 dev_err(dev, "Failed to get osc clock\n"); 864 return PTR_ERR(kmb_i2s->clk_i2s); 865 } 866 867 kmb_i2s->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 868 if (IS_ERR(kmb_i2s->i2s_base)) 869 return PTR_ERR(kmb_i2s->i2s_base); 870 871 kmb_i2s->pss_base = devm_platform_ioremap_resource(pdev, 1); 872 if (IS_ERR(kmb_i2s->pss_base)) 873 return PTR_ERR(kmb_i2s->pss_base); 874 875 kmb_i2s->dev = &pdev->dev; 876 877 comp1_reg = readl(kmb_i2s->i2s_base + I2S_COMP_PARAM_1); 878 879 kmb_i2s->fifo_th = (1 << COMP1_FIFO_DEPTH(comp1_reg)) / 2; 880 881 kmb_i2s->use_pio = !(of_property_read_bool(np, "dmas")); 882 883 if (kmb_i2s->use_pio) { 884 irq = platform_get_irq_optional(pdev, 0); 885 if (irq > 0) { 886 ret = devm_request_irq(dev, irq, kmb_i2s_irq_handler, 0, 887 pdev->name, kmb_i2s); 888 if (ret < 0) { 889 dev_err(dev, "failed to request irq\n"); 890 return ret; 891 } 892 } 893 ret = devm_snd_soc_register_component(dev, &kmb_component, 894 kmb_i2s_dai, 1); 895 } else { 896 kmb_i2s->play_dma_data.addr = res->start + I2S_TXDMA; 897 kmb_i2s->capture_dma_data.addr = res->start + I2S_RXDMA; 898 ret = snd_dmaengine_pcm_register(&pdev->dev, 899 NULL, 0); 900 if (ret) { 901 dev_err(&pdev->dev, "could not register dmaengine: %d\n", 902 ret); 903 return ret; 904 } 905 ret = devm_snd_soc_register_component(dev, &kmb_component_dma, 906 kmb_i2s_dai, 1); 907 } 908 909 if (ret) { 910 dev_err(dev, "not able to register dai\n"); 911 return ret; 912 } 913 914 /* To ensure none of the channels are enabled at boot up */ 915 kmb_i2s_disable_channels(kmb_i2s, SNDRV_PCM_STREAM_PLAYBACK); 916 kmb_i2s_disable_channels(kmb_i2s, SNDRV_PCM_STREAM_CAPTURE); 917 918 dev_set_drvdata(dev, kmb_i2s); 919 920 return ret; 921 } 922 923 static struct platform_driver kmb_plat_dai_driver = { 924 .driver = { 925 .name = "kmb-plat-dai", 926 .of_match_table = kmb_plat_of_match, 927 }, 928 .probe = kmb_plat_dai_probe, 929 }; 930 931 module_platform_driver(kmb_plat_dai_driver); 932 933 MODULE_DESCRIPTION("ASoC Intel KeemBay Platform driver"); 934 MODULE_AUTHOR("Sia Jee Heng <jee.heng.sia@intel.com>"); 935 MODULE_AUTHOR("Sit, Michael Wei Hong <michael.wei.hong.sit@intel.com>"); 936 MODULE_LICENSE("GPL v2"); 937 MODULE_ALIAS("platform:kmb_platform"); 938