1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * soc-acpi-intel-tgl-match.c - tables and support for TGL ACPI enumeration. 4 * 5 * Copyright (c) 2019, Intel Corporation. 6 * 7 */ 8 9 #include <sound/soc-acpi.h> 10 #include <sound/soc-acpi-intel-match.h> 11 #include "soc-acpi-intel-sdw-mockup-match.h" 12 13 static const struct snd_soc_acpi_codecs tgl_codecs = { 14 .num_codecs = 1, 15 .codecs = {"MX98357A"} 16 }; 17 18 static const struct snd_soc_acpi_endpoint single_endpoint = { 19 .num = 0, 20 .aggregated = 0, 21 .group_position = 0, 22 .group_id = 0, 23 }; 24 25 static const struct snd_soc_acpi_endpoint spk_l_endpoint = { 26 .num = 0, 27 .aggregated = 1, 28 .group_position = 0, 29 .group_id = 1, 30 }; 31 32 static const struct snd_soc_acpi_endpoint spk_r_endpoint = { 33 .num = 0, 34 .aggregated = 1, 35 .group_position = 1, 36 .group_id = 1, 37 }; 38 39 static const struct snd_soc_acpi_adr_device rt711_0_adr[] = { 40 { 41 .adr = 0x000020025D071100ull, 42 .num_endpoints = 1, 43 .endpoints = &single_endpoint, 44 .name_prefix = "rt711" 45 } 46 }; 47 48 static const struct snd_soc_acpi_adr_device rt711_1_adr[] = { 49 { 50 .adr = 0x000120025D071100ull, 51 .num_endpoints = 1, 52 .endpoints = &single_endpoint, 53 .name_prefix = "rt711" 54 } 55 }; 56 57 static const struct snd_soc_acpi_adr_device rt1308_1_dual_adr[] = { 58 { 59 .adr = 0x000120025D130800ull, 60 .num_endpoints = 1, 61 .endpoints = &spk_l_endpoint, 62 .name_prefix = "rt1308-1" 63 }, 64 { 65 .adr = 0x000122025D130800ull, 66 .num_endpoints = 1, 67 .endpoints = &spk_r_endpoint, 68 .name_prefix = "rt1308-2" 69 } 70 }; 71 72 static const struct snd_soc_acpi_adr_device rt1308_1_single_adr[] = { 73 { 74 .adr = 0x000120025D130800ull, 75 .num_endpoints = 1, 76 .endpoints = &single_endpoint, 77 .name_prefix = "rt1308-1" 78 } 79 }; 80 81 static const struct snd_soc_acpi_adr_device rt1308_2_single_adr[] = { 82 { 83 .adr = 0x000220025D130800ull, 84 .num_endpoints = 1, 85 .endpoints = &single_endpoint, 86 .name_prefix = "rt1308-1" 87 } 88 }; 89 90 static const struct snd_soc_acpi_adr_device rt1308_1_group1_adr[] = { 91 { 92 .adr = 0x000120025D130800ull, 93 .num_endpoints = 1, 94 .endpoints = &spk_l_endpoint, 95 .name_prefix = "rt1308-1" 96 } 97 }; 98 99 static const struct snd_soc_acpi_adr_device rt1308_2_group1_adr[] = { 100 { 101 .adr = 0x000220025D130800ull, 102 .num_endpoints = 1, 103 .endpoints = &spk_r_endpoint, 104 .name_prefix = "rt1308-2" 105 } 106 }; 107 108 static const struct snd_soc_acpi_adr_device rt715_0_adr[] = { 109 { 110 .adr = 0x000021025D071500ull, 111 .num_endpoints = 1, 112 .endpoints = &single_endpoint, 113 .name_prefix = "rt715" 114 } 115 }; 116 117 static const struct snd_soc_acpi_adr_device rt715_3_adr[] = { 118 { 119 .adr = 0x000320025D071500ull, 120 .num_endpoints = 1, 121 .endpoints = &single_endpoint, 122 .name_prefix = "rt715" 123 } 124 }; 125 126 static const struct snd_soc_acpi_adr_device mx8373_1_adr[] = { 127 { 128 .adr = 0x000123019F837300ull, 129 .num_endpoints = 1, 130 .endpoints = &spk_l_endpoint, 131 .name_prefix = "Right" 132 }, 133 { 134 .adr = 0x000127019F837300ull, 135 .num_endpoints = 1, 136 .endpoints = &spk_r_endpoint, 137 .name_prefix = "Left" 138 } 139 }; 140 141 static const struct snd_soc_acpi_adr_device rt5682_0_adr[] = { 142 { 143 .adr = 0x000021025D568200ull, 144 .num_endpoints = 1, 145 .endpoints = &single_endpoint, 146 .name_prefix = "rt5682" 147 } 148 }; 149 150 static const struct snd_soc_acpi_adr_device rt711_sdca_0_adr[] = { 151 { 152 .adr = 0x000030025D071101ull, 153 .num_endpoints = 1, 154 .endpoints = &single_endpoint, 155 .name_prefix = "rt711" 156 } 157 }; 158 159 static const struct snd_soc_acpi_adr_device rt1316_1_single_adr[] = { 160 { 161 .adr = 0x000131025D131601ull, 162 .num_endpoints = 1, 163 .endpoints = &single_endpoint, 164 .name_prefix = "rt1316-1" 165 } 166 }; 167 168 static const struct snd_soc_acpi_adr_device rt1316_1_group1_adr[] = { 169 { 170 .adr = 0x000131025D131601ull, /* unique ID is set for some reason */ 171 .num_endpoints = 1, 172 .endpoints = &spk_l_endpoint, 173 .name_prefix = "rt1316-1" 174 } 175 }; 176 177 static const struct snd_soc_acpi_adr_device rt1316_2_group1_adr[] = { 178 { 179 .adr = 0x000230025D131601ull, 180 .num_endpoints = 1, 181 .endpoints = &spk_r_endpoint, 182 .name_prefix = "rt1316-2" 183 } 184 }; 185 186 static const struct snd_soc_acpi_adr_device rt714_3_adr[] = { 187 { 188 .adr = 0x000330025D071401ull, 189 .num_endpoints = 1, 190 .endpoints = &single_endpoint, 191 .name_prefix = "rt714" 192 } 193 }; 194 195 static const struct snd_soc_acpi_link_adr tgl_rvp[] = { 196 { 197 .mask = BIT(0), 198 .num_adr = ARRAY_SIZE(rt711_0_adr), 199 .adr_d = rt711_0_adr, 200 }, 201 { 202 .mask = BIT(1), 203 .num_adr = ARRAY_SIZE(rt1308_1_dual_adr), 204 .adr_d = rt1308_1_dual_adr, 205 }, 206 {} 207 }; 208 209 static const struct snd_soc_acpi_link_adr tgl_rvp_headset_only[] = { 210 { 211 .mask = BIT(0), 212 .num_adr = ARRAY_SIZE(rt711_0_adr), 213 .adr_d = rt711_0_adr, 214 }, 215 {} 216 }; 217 218 static const struct snd_soc_acpi_link_adr tgl_hp[] = { 219 { 220 .mask = BIT(0), 221 .num_adr = ARRAY_SIZE(rt711_0_adr), 222 .adr_d = rt711_0_adr, 223 }, 224 { 225 .mask = BIT(1), 226 .num_adr = ARRAY_SIZE(rt1308_1_single_adr), 227 .adr_d = rt1308_1_single_adr, 228 }, 229 {} 230 }; 231 232 static const struct snd_soc_acpi_link_adr tgl_chromebook_base[] = { 233 { 234 .mask = BIT(0), 235 .num_adr = ARRAY_SIZE(rt5682_0_adr), 236 .adr_d = rt5682_0_adr, 237 }, 238 { 239 .mask = BIT(1), 240 .num_adr = ARRAY_SIZE(mx8373_1_adr), 241 .adr_d = mx8373_1_adr, 242 }, 243 {} 244 }; 245 246 static const struct snd_soc_acpi_link_adr tgl_3_in_1_default[] = { 247 { 248 .mask = BIT(0), 249 .num_adr = ARRAY_SIZE(rt711_0_adr), 250 .adr_d = rt711_0_adr, 251 }, 252 { 253 .mask = BIT(1), 254 .num_adr = ARRAY_SIZE(rt1308_1_group1_adr), 255 .adr_d = rt1308_1_group1_adr, 256 }, 257 { 258 .mask = BIT(2), 259 .num_adr = ARRAY_SIZE(rt1308_2_group1_adr), 260 .adr_d = rt1308_2_group1_adr, 261 }, 262 { 263 .mask = BIT(3), 264 .num_adr = ARRAY_SIZE(rt715_3_adr), 265 .adr_d = rt715_3_adr, 266 }, 267 {} 268 }; 269 270 static const struct snd_soc_acpi_link_adr tgl_3_in_1_mono_amp[] = { 271 { 272 .mask = BIT(0), 273 .num_adr = ARRAY_SIZE(rt711_0_adr), 274 .adr_d = rt711_0_adr, 275 }, 276 { 277 .mask = BIT(1), 278 .num_adr = ARRAY_SIZE(rt1308_1_single_adr), 279 .adr_d = rt1308_1_single_adr, 280 }, 281 { 282 .mask = BIT(3), 283 .num_adr = ARRAY_SIZE(rt715_3_adr), 284 .adr_d = rt715_3_adr, 285 }, 286 {} 287 }; 288 289 static const struct snd_soc_acpi_link_adr tgl_sdw_rt711_link1_rt1308_link2_rt715_link0[] = { 290 { 291 .mask = BIT(1), 292 .num_adr = ARRAY_SIZE(rt711_1_adr), 293 .adr_d = rt711_1_adr, 294 }, 295 { 296 .mask = BIT(2), 297 .num_adr = ARRAY_SIZE(rt1308_2_single_adr), 298 .adr_d = rt1308_2_single_adr, 299 }, 300 { 301 .mask = BIT(0), 302 .num_adr = ARRAY_SIZE(rt715_0_adr), 303 .adr_d = rt715_0_adr, 304 }, 305 {} 306 }; 307 308 static const struct snd_soc_acpi_link_adr tgl_3_in_1_sdca[] = { 309 { 310 .mask = BIT(0), 311 .num_adr = ARRAY_SIZE(rt711_sdca_0_adr), 312 .adr_d = rt711_sdca_0_adr, 313 }, 314 { 315 .mask = BIT(1), 316 .num_adr = ARRAY_SIZE(rt1316_1_group1_adr), 317 .adr_d = rt1316_1_group1_adr, 318 }, 319 { 320 .mask = BIT(2), 321 .num_adr = ARRAY_SIZE(rt1316_2_group1_adr), 322 .adr_d = rt1316_2_group1_adr, 323 }, 324 { 325 .mask = BIT(3), 326 .num_adr = ARRAY_SIZE(rt714_3_adr), 327 .adr_d = rt714_3_adr, 328 }, 329 {} 330 }; 331 332 static const struct snd_soc_acpi_link_adr tgl_3_in_1_sdca_mono[] = { 333 { 334 .mask = BIT(0), 335 .num_adr = ARRAY_SIZE(rt711_sdca_0_adr), 336 .adr_d = rt711_sdca_0_adr, 337 }, 338 { 339 .mask = BIT(1), 340 .num_adr = ARRAY_SIZE(rt1316_1_single_adr), 341 .adr_d = rt1316_1_single_adr, 342 }, 343 { 344 .mask = BIT(3), 345 .num_adr = ARRAY_SIZE(rt714_3_adr), 346 .adr_d = rt714_3_adr, 347 }, 348 {} 349 }; 350 351 static const struct snd_soc_acpi_codecs tgl_max98373_amp = { 352 .num_codecs = 1, 353 .codecs = {"MX98373"} 354 }; 355 356 static const struct snd_soc_acpi_codecs tgl_rt1011_amp = { 357 .num_codecs = 1, 358 .codecs = {"10EC1011"} 359 }; 360 361 static const struct snd_soc_acpi_codecs tgl_rt5682_rt5682s_hp = { 362 .num_codecs = 2, 363 .codecs = {"10EC5682", "RTL5682"}, 364 }; 365 366 struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_machines[] = { 367 { 368 .comp_ids = &tgl_rt5682_rt5682s_hp, 369 .drv_name = "tgl_mx98357_rt5682", 370 .machine_quirk = snd_soc_acpi_codec_list, 371 .quirk_data = &tgl_codecs, 372 .sof_fw_filename = "sof-tgl.ri", 373 .sof_tplg_filename = "sof-tgl-max98357a-rt5682.tplg", 374 }, 375 { 376 .comp_ids = &tgl_rt5682_rt5682s_hp, 377 .drv_name = "tgl_mx98373_rt5682", 378 .machine_quirk = snd_soc_acpi_codec_list, 379 .quirk_data = &tgl_max98373_amp, 380 .sof_fw_filename = "sof-tgl.ri", 381 .sof_tplg_filename = "sof-tgl-max98373-rt5682.tplg", 382 }, 383 { 384 .comp_ids = &tgl_rt5682_rt5682s_hp, 385 .drv_name = "tgl_rt1011_rt5682", 386 .machine_quirk = snd_soc_acpi_codec_list, 387 .quirk_data = &tgl_rt1011_amp, 388 .sof_fw_filename = "sof-tgl.ri", 389 .sof_tplg_filename = "sof-tgl-rt1011-rt5682.tplg", 390 }, 391 { 392 .id = "ESSX8336", 393 .drv_name = "sof-essx8336", 394 .sof_fw_filename = "sof-tgl.ri", 395 .sof_tplg_filename = "sof-tgl-es8336.tplg", 396 }, 397 {}, 398 }; 399 EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_tgl_machines); 400 401 /* this table is used when there is no I2S codec present */ 402 struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[] = { 403 /* mockup tests need to be first */ 404 { 405 .link_mask = GENMASK(3, 0), 406 .links = sdw_mockup_headset_2amps_mic, 407 .drv_name = "sof_sdw", 408 .sof_fw_filename = "sof-tgl.ri", 409 .sof_tplg_filename = "sof-tgl-rt711-rt1308-rt715.tplg", 410 }, 411 { 412 .link_mask = BIT(0) | BIT(1) | BIT(3), 413 .links = sdw_mockup_headset_1amp_mic, 414 .drv_name = "sof_sdw", 415 .sof_fw_filename = "sof-tgl.ri", 416 .sof_tplg_filename = "sof-tgl-rt711-rt1308-mono-rt715.tplg", 417 }, 418 { 419 .link_mask = BIT(0) | BIT(1) | BIT(2), 420 .links = sdw_mockup_mic_headset_1amp, 421 .drv_name = "sof_sdw", 422 .sof_fw_filename = "sof-tgl.ri", 423 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg", 424 }, 425 { 426 .link_mask = 0x7, 427 .links = tgl_sdw_rt711_link1_rt1308_link2_rt715_link0, 428 .drv_name = "sof_sdw", 429 .sof_tplg_filename = "sof-tgl-rt715-rt711-rt1308-mono.tplg", 430 }, 431 { 432 .link_mask = 0xF, /* 4 active links required */ 433 .links = tgl_3_in_1_default, 434 .drv_name = "sof_sdw", 435 .sof_tplg_filename = "sof-tgl-rt711-rt1308-rt715.tplg", 436 }, 437 { 438 /* 439 * link_mask should be 0xB, but all links are enabled by BIOS. 440 * This entry will be selected if there is no rt1308 exposed 441 * on link2 since it will fail to match the above entry. 442 */ 443 .link_mask = 0xF, 444 .links = tgl_3_in_1_mono_amp, 445 .drv_name = "sof_sdw", 446 .sof_tplg_filename = "sof-tgl-rt711-rt1308-mono-rt715.tplg", 447 }, 448 { 449 .link_mask = 0xF, /* 4 active links required */ 450 .links = tgl_3_in_1_sdca, 451 .drv_name = "sof_sdw", 452 .sof_tplg_filename = "sof-tgl-rt711-rt1316-rt714.tplg", 453 }, 454 { 455 /* 456 * link_mask should be 0xB, but all links are enabled by BIOS. 457 * This entry will be selected if there is no rt1316 amplifier exposed 458 * on link2 since it will fail to match the above entry. 459 */ 460 461 .link_mask = 0xF, /* 4 active links required */ 462 .links = tgl_3_in_1_sdca_mono, 463 .drv_name = "sof_sdw", 464 .sof_tplg_filename = "sof-tgl-rt711-l0-rt1316-l1-mono-rt714-l3.tplg", 465 }, 466 467 { 468 .link_mask = 0x3, /* rt711 on link 0 and 1 rt1308 on link 1 */ 469 .links = tgl_hp, 470 .drv_name = "sof_sdw", 471 .sof_tplg_filename = "sof-tgl-rt711-rt1308.tplg", 472 }, 473 { 474 .link_mask = 0x3, /* rt711 on link 0 and 2 rt1308s on link 1 */ 475 .links = tgl_rvp, 476 .drv_name = "sof_sdw", 477 .sof_tplg_filename = "sof-tgl-rt711-rt1308.tplg", 478 }, 479 { 480 .link_mask = 0x3, /* rt5682 on link0 & 2xmax98373 on link 1 */ 481 .links = tgl_chromebook_base, 482 .drv_name = "sof_sdw", 483 .sof_tplg_filename = "sof-tgl-sdw-max98373-rt5682.tplg", 484 }, 485 { 486 .link_mask = 0x1, /* rt711 on link 0 */ 487 .links = tgl_rvp_headset_only, 488 .drv_name = "sof_sdw", 489 .sof_tplg_filename = "sof-tgl-rt711.tplg", 490 }, 491 {}, 492 }; 493 EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_tgl_sdw_machines); 494