1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright(c) 2020 Intel Corporation. All rights reserved. 4 // 5 // Author: Cezary Rojewski <cezary.rojewski@intel.com> 6 // 7 8 #include <linux/devcoredump.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/firmware.h> 11 #include <linux/pci.h> 12 #include <linux/pxa2xx_ssp.h> 13 #include "core.h" 14 #include "messages.h" 15 #include "registers.h" 16 17 static bool catpt_dma_filter(struct dma_chan *chan, void *param) 18 { 19 return param == chan->device->dev; 20 } 21 22 /* 23 * Either engine 0 or 1 can be used for image loading. 24 * Align with Windows driver equivalent and stick to engine 1. 25 */ 26 #define CATPT_DMA_DEVID 1 27 #define CATPT_DMA_DSP_ADDR_MASK GENMASK(31, 20) 28 29 struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev) 30 { 31 struct dma_slave_config config; 32 struct dma_chan *chan; 33 dma_cap_mask_t mask; 34 int ret; 35 36 dma_cap_zero(mask); 37 dma_cap_set(DMA_MEMCPY, mask); 38 39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); 40 if (!chan) { 41 dev_err(cdev->dev, "request channel failed\n"); 42 return ERR_PTR(-ENODEV); 43 } 44 45 memset(&config, 0, sizeof(config)); 46 config.direction = DMA_MEM_TO_DEV; 47 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 48 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 49 config.src_maxburst = 16; 50 config.dst_maxburst = 16; 51 52 ret = dmaengine_slave_config(chan, &config); 53 if (ret) { 54 dev_err(cdev->dev, "slave config failed: %d\n", ret); 55 dma_release_channel(chan); 56 return ERR_PTR(ret); 57 } 58 59 return chan; 60 } 61 62 static int catpt_dma_memcpy(struct catpt_dev *cdev, struct dma_chan *chan, 63 dma_addr_t dst_addr, dma_addr_t src_addr, 64 size_t size) 65 { 66 struct dma_async_tx_descriptor *desc; 67 enum dma_status status; 68 69 desc = dmaengine_prep_dma_memcpy(chan, dst_addr, src_addr, size, 70 DMA_CTRL_ACK); 71 if (!desc) { 72 dev_err(cdev->dev, "prep dma memcpy failed\n"); 73 return -EIO; 74 } 75 76 /* enable demand mode for dma channel */ 77 catpt_updatel_shim(cdev, HMDC, 78 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), 79 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id)); 80 dmaengine_submit(desc); 81 status = dma_wait_for_async_tx(desc); 82 /* regardless of status, disable access to HOST memory in demand mode */ 83 catpt_updatel_shim(cdev, HMDC, 84 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), 0); 85 86 return (status == DMA_COMPLETE) ? 0 : -EPROTO; 87 } 88 89 int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan, 90 dma_addr_t dst_addr, dma_addr_t src_addr, 91 size_t size) 92 { 93 return catpt_dma_memcpy(cdev, chan, dst_addr | CATPT_DMA_DSP_ADDR_MASK, 94 src_addr, size); 95 } 96 97 int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan, 98 dma_addr_t dst_addr, dma_addr_t src_addr, 99 size_t size) 100 { 101 return catpt_dma_memcpy(cdev, chan, dst_addr, 102 src_addr | CATPT_DMA_DSP_ADDR_MASK, size); 103 } 104 105 int catpt_dmac_probe(struct catpt_dev *cdev) 106 { 107 struct dw_dma_chip *dmac; 108 int ret; 109 110 dmac = devm_kzalloc(cdev->dev, sizeof(*dmac), GFP_KERNEL); 111 if (!dmac) 112 return -ENOMEM; 113 114 dmac->regs = cdev->lpe_ba + cdev->spec->host_dma_offset[CATPT_DMA_DEVID]; 115 dmac->dev = cdev->dev; 116 dmac->irq = cdev->irq; 117 118 ret = dma_coerce_mask_and_coherent(cdev->dev, DMA_BIT_MASK(31)); 119 if (ret) 120 return ret; 121 /* 122 * Caller is responsible for putting device in D0 to allow 123 * for I/O and memory access before probing DW. 124 */ 125 ret = dw_dma_probe(dmac); 126 if (ret) 127 return ret; 128 129 cdev->dmac = dmac; 130 return 0; 131 } 132 133 void catpt_dmac_remove(struct catpt_dev *cdev) 134 { 135 /* 136 * As do_dma_remove() juggles with pm_runtime_get_xxx() and 137 * pm_runtime_put_xxx() while both ADSP and DW 'devices' are part of 138 * the same module, caller makes sure pm_runtime_disable() is invoked 139 * before removing DW to prevent postmortem resume and suspend. 140 */ 141 dw_dma_remove(cdev->dmac); 142 } 143 144 static void catpt_dsp_set_srampge(struct catpt_dev *cdev, struct resource *sram, 145 unsigned long mask, unsigned long new) 146 { 147 unsigned long old; 148 u32 off = sram->start; 149 u32 b = __ffs(mask); 150 151 old = catpt_readl_pci(cdev, VDRTCTL0) & mask; 152 dev_dbg(cdev->dev, "SRAMPGE [0x%08lx] 0x%08lx -> 0x%08lx", 153 mask, old, new); 154 155 if (old == new) 156 return; 157 158 catpt_updatel_pci(cdev, VDRTCTL0, mask, new); 159 /* wait for SRAM power gating to propagate */ 160 udelay(60); 161 162 /* 163 * Dummy read as the very first access after block enable 164 * to prevent byte loss in future operations. 165 */ 166 for_each_clear_bit_from(b, &new, fls_long(mask)) { 167 u8 buf[4]; 168 169 /* newly enabled: new bit=0 while old bit=1 */ 170 if (test_bit(b, &old)) { 171 dev_dbg(cdev->dev, "sanitize block %ld: off 0x%08x\n", 172 b - __ffs(mask), off); 173 memcpy_fromio(buf, cdev->lpe_ba + off, sizeof(buf)); 174 } 175 off += CATPT_MEMBLOCK_SIZE; 176 } 177 } 178 179 void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram, 180 unsigned long mask) 181 { 182 struct resource *res; 183 unsigned long new = 0; 184 185 /* flag all busy blocks */ 186 for (res = sram->child; res; res = res->sibling) { 187 u32 h, l; 188 189 h = (res->end - sram->start) / CATPT_MEMBLOCK_SIZE; 190 l = (res->start - sram->start) / CATPT_MEMBLOCK_SIZE; 191 new |= GENMASK(h, l); 192 } 193 194 /* offset value given mask's start and invert it as ON=b0 */ 195 new = ~(new << __ffs(mask)) & mask; 196 197 /* disable core clock gating */ 198 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); 199 200 catpt_dsp_set_srampge(cdev, sram, mask, new); 201 202 /* enable core clock gating */ 203 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 204 CATPT_VDRTCTL2_DCLCGE); 205 } 206 207 int catpt_dsp_stall(struct catpt_dev *cdev, bool stall) 208 { 209 u32 reg, val; 210 211 val = stall ? CATPT_CS_STALL : 0; 212 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); 213 214 return catpt_readl_poll_shim(cdev, CS1, 215 reg, (reg & CATPT_CS_STALL) == val, 216 500, 10000); 217 } 218 219 static int catpt_dsp_reset(struct catpt_dev *cdev, bool reset) 220 { 221 u32 reg, val; 222 223 val = reset ? CATPT_CS_RST : 0; 224 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); 225 226 return catpt_readl_poll_shim(cdev, CS1, 227 reg, (reg & CATPT_CS_RST) == val, 228 500, 10000); 229 } 230 231 void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) 232 { 233 u32 val; 234 235 val = enable ? LPT_VDRTCTL0_APLLSE : 0; 236 catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val); 237 } 238 239 void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) 240 { 241 u32 val; 242 243 val = enable ? WPT_VDRTCTL2_APLLSE : 0; 244 catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val); 245 } 246 247 static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti) 248 { 249 u32 mask, reg, val; 250 int ret; 251 252 mutex_lock(&cdev->clk_mutex); 253 254 val = lp ? CATPT_CS_LPCS : 0; 255 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; 256 dev_dbg(cdev->dev, "LPCS [0x%08lx] 0x%08x -> 0x%08x", 257 CATPT_CS_LPCS, reg, val); 258 259 if (reg == val) { 260 mutex_unlock(&cdev->clk_mutex); 261 return 0; 262 } 263 264 if (waiti) { 265 /* wait for DSP to signal WAIT state */ 266 ret = catpt_readl_poll_shim(cdev, ISD, 267 reg, (reg & CATPT_ISD_DCPWM), 268 500, 10000); 269 if (ret) { 270 dev_err(cdev->dev, "await WAITI timeout\n"); 271 mutex_unlock(&cdev->clk_mutex); 272 return ret; 273 } 274 } 275 276 ret = catpt_readl_poll_shim(cdev, CLKCTL, 277 reg, !(reg & CATPT_CLKCTL_CFCIP), 278 500, 10000); 279 if (ret) 280 dev_warn(cdev->dev, "clock change still in progress\n"); 281 282 /* default to DSP core & audio fabric high clock */ 283 val |= CATPT_CS_DCS_HIGH; 284 mask = CATPT_CS_LPCS | CATPT_CS_DCS; 285 catpt_updatel_shim(cdev, CS1, mask, val); 286 287 ret = catpt_readl_poll_shim(cdev, CLKCTL, 288 reg, !(reg & CATPT_CLKCTL_CFCIP), 289 500, 10000); 290 if (ret) 291 dev_warn(cdev->dev, "clock change still in progress\n"); 292 293 /* update PLL accordingly */ 294 cdev->spec->pll_shutdown(cdev, lp); 295 296 mutex_unlock(&cdev->clk_mutex); 297 return 0; 298 } 299 300 int catpt_dsp_update_lpclock(struct catpt_dev *cdev) 301 { 302 struct catpt_stream_runtime *stream; 303 304 list_for_each_entry(stream, &cdev->stream_list, node) 305 if (stream->prepared) 306 return catpt_dsp_select_lpclock(cdev, false, true); 307 308 return catpt_dsp_select_lpclock(cdev, true, true); 309 } 310 311 /* bring registers to their defaults as HW won't reset itself */ 312 static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev) 313 { 314 int i; 315 316 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); 317 catpt_writel_shim(cdev, ISC, CATPT_ISC_DEFAULT); 318 catpt_writel_shim(cdev, ISD, CATPT_ISD_DEFAULT); 319 catpt_writel_shim(cdev, IMC, CATPT_IMC_DEFAULT); 320 catpt_writel_shim(cdev, IMD, CATPT_IMD_DEFAULT); 321 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); 322 catpt_writel_shim(cdev, IPCD, CATPT_IPCD_DEFAULT); 323 catpt_writel_shim(cdev, CLKCTL, CATPT_CLKCTL_DEFAULT); 324 catpt_writel_shim(cdev, CS2, CATPT_CS2_DEFAULT); 325 catpt_writel_shim(cdev, LTRC, CATPT_LTRC_DEFAULT); 326 catpt_writel_shim(cdev, HMDC, CATPT_HMDC_DEFAULT); 327 328 for (i = 0; i < CATPT_SSP_COUNT; i++) { 329 catpt_writel_ssp(cdev, i, SSCR0, CATPT_SSC0_DEFAULT); 330 catpt_writel_ssp(cdev, i, SSCR1, CATPT_SSC1_DEFAULT); 331 catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT); 332 catpt_writel_ssp(cdev, i, SSITR, CATPT_SSIT_DEFAULT); 333 catpt_writel_ssp(cdev, i, SSDR, CATPT_SSD_DEFAULT); 334 catpt_writel_ssp(cdev, i, SSTO, CATPT_SSTO_DEFAULT); 335 catpt_writel_ssp(cdev, i, SSPSP, CATPT_SSPSP_DEFAULT); 336 catpt_writel_ssp(cdev, i, SSTSA, CATPT_SSTSA_DEFAULT); 337 catpt_writel_ssp(cdev, i, SSRSA, CATPT_SSRSA_DEFAULT); 338 catpt_writel_ssp(cdev, i, SSTSS, CATPT_SSTSS_DEFAULT); 339 catpt_writel_ssp(cdev, i, SSCR2, CATPT_SSCR2_DEFAULT); 340 catpt_writel_ssp(cdev, i, SSPSP2, CATPT_SSPSP2_DEFAULT); 341 } 342 } 343 344 int lpt_dsp_power_down(struct catpt_dev *cdev) 345 { 346 catpt_dsp_reset(cdev, true); 347 348 /* set 24Mhz clock for both SSPs */ 349 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), 350 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); 351 catpt_dsp_select_lpclock(cdev, true, false); 352 353 /* DRAM power gating all */ 354 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 355 cdev->spec->dram_mask); 356 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 357 cdev->spec->iram_mask); 358 359 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot); 360 /* give hw time to drop off */ 361 udelay(50); 362 363 return 0; 364 } 365 366 int lpt_dsp_power_up(struct catpt_dev *cdev) 367 { 368 /* SRAM power gating none */ 369 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0); 370 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0); 371 372 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0); 373 /* give hw time to wake up */ 374 udelay(100); 375 376 catpt_dsp_select_lpclock(cdev, false, false); 377 catpt_updatel_shim(cdev, CS1, 378 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), 379 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); 380 /* stagger DSP reset after clock selection */ 381 udelay(50); 382 383 catpt_dsp_reset(cdev, false); 384 /* generate int deassert msg to fix inversed int logic */ 385 catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0); 386 387 return 0; 388 } 389 390 int wpt_dsp_power_down(struct catpt_dev *cdev) 391 { 392 u32 mask, val; 393 394 /* disable core clock gating */ 395 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); 396 397 catpt_dsp_reset(cdev, true); 398 /* set 24Mhz clock for both SSPs */ 399 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), 400 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); 401 catpt_dsp_select_lpclock(cdev, true, false); 402 /* disable MCLK */ 403 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, 0); 404 405 catpt_dsp_set_regs_defaults(cdev); 406 407 /* switch clock gating */ 408 mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE); 409 val = mask & (~CATPT_VDRTCTL2_DTCGE); 410 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); 411 /* enable DTCGE separatelly */ 412 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE, 413 CATPT_VDRTCTL2_DTCGE); 414 415 /* SRAM power gating all */ 416 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 417 cdev->spec->dram_mask); 418 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 419 cdev->spec->iram_mask); 420 mask = WPT_VDRTCTL0_D3SRAMPGD | WPT_VDRTCTL0_D3PGD; 421 catpt_updatel_pci(cdev, VDRTCTL0, mask, WPT_VDRTCTL0_D3PGD); 422 423 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot); 424 /* give hw time to drop off */ 425 udelay(50); 426 427 /* enable core clock gating */ 428 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 429 CATPT_VDRTCTL2_DCLCGE); 430 udelay(50); 431 432 return 0; 433 } 434 435 int wpt_dsp_power_up(struct catpt_dev *cdev) 436 { 437 u32 mask, val; 438 439 /* disable core clock gating */ 440 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); 441 442 /* switch clock gating */ 443 mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE); 444 val = mask & (~CATPT_VDRTCTL2_DTCGE); 445 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); 446 447 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0); 448 449 /* SRAM power gating none */ 450 mask = WPT_VDRTCTL0_D3SRAMPGD | WPT_VDRTCTL0_D3PGD; 451 catpt_updatel_pci(cdev, VDRTCTL0, mask, mask); 452 catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0); 453 catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0); 454 455 catpt_dsp_set_regs_defaults(cdev); 456 457 /* restore MCLK */ 458 catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, CATPT_CLKCTL_SMOS); 459 catpt_dsp_select_lpclock(cdev, false, false); 460 /* set 24Mhz clock for both SSPs */ 461 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), 462 CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); 463 catpt_dsp_reset(cdev, false); 464 465 /* enable core clock gating */ 466 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 467 CATPT_VDRTCTL2_DCLCGE); 468 469 /* generate int deassert msg to fix inversed int logic */ 470 catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0); 471 472 return 0; 473 } 474 475 #define CATPT_DUMP_MAGIC 0xcd42 476 #define CATPT_DUMP_SECTION_ID_FILE 0x00 477 #define CATPT_DUMP_SECTION_ID_IRAM 0x01 478 #define CATPT_DUMP_SECTION_ID_DRAM 0x02 479 #define CATPT_DUMP_SECTION_ID_REGS 0x03 480 #define CATPT_DUMP_HASH_SIZE 20 481 482 struct catpt_dump_section_hdr { 483 u16 magic; 484 u8 core_id; 485 u8 section_id; 486 u32 size; 487 }; 488 489 int catpt_coredump(struct catpt_dev *cdev) 490 { 491 struct catpt_dump_section_hdr *hdr; 492 size_t dump_size, regs_size; 493 u8 *dump, *pos; 494 const char *eof; 495 char *info; 496 int i; 497 498 regs_size = CATPT_SHIM_REGS_SIZE; 499 regs_size += CATPT_DMA_COUNT * CATPT_DMA_REGS_SIZE; 500 regs_size += CATPT_SSP_COUNT * CATPT_SSP_REGS_SIZE; 501 dump_size = resource_size(&cdev->dram); 502 dump_size += resource_size(&cdev->iram); 503 dump_size += regs_size; 504 /* account for header of each section and hash chunk */ 505 dump_size += 4 * sizeof(*hdr) + CATPT_DUMP_HASH_SIZE; 506 507 dump = vzalloc(dump_size); 508 if (!dump) 509 return -ENOMEM; 510 511 pos = dump; 512 513 hdr = (struct catpt_dump_section_hdr *)pos; 514 hdr->magic = CATPT_DUMP_MAGIC; 515 hdr->core_id = cdev->spec->core_id; 516 hdr->section_id = CATPT_DUMP_SECTION_ID_FILE; 517 hdr->size = dump_size - sizeof(*hdr); 518 pos += sizeof(*hdr); 519 520 info = cdev->ipc.config.fw_info; 521 eof = info + FW_INFO_SIZE_MAX; 522 /* navigate to fifth info segment (fw hash) */ 523 for (i = 0; i < 4 && info < eof; i++, info++) { 524 /* info segments are separated by space each */ 525 info = strnchr(info, eof - info, ' '); 526 if (!info) 527 break; 528 } 529 530 if (i == 4 && info) 531 memcpy(pos, info, min_t(u32, eof - info, CATPT_DUMP_HASH_SIZE)); 532 pos += CATPT_DUMP_HASH_SIZE; 533 534 hdr = (struct catpt_dump_section_hdr *)pos; 535 hdr->magic = CATPT_DUMP_MAGIC; 536 hdr->core_id = cdev->spec->core_id; 537 hdr->section_id = CATPT_DUMP_SECTION_ID_IRAM; 538 hdr->size = resource_size(&cdev->iram); 539 pos += sizeof(*hdr); 540 541 memcpy_fromio(pos, cdev->lpe_ba + cdev->iram.start, hdr->size); 542 pos += hdr->size; 543 544 hdr = (struct catpt_dump_section_hdr *)pos; 545 hdr->magic = CATPT_DUMP_MAGIC; 546 hdr->core_id = cdev->spec->core_id; 547 hdr->section_id = CATPT_DUMP_SECTION_ID_DRAM; 548 hdr->size = resource_size(&cdev->dram); 549 pos += sizeof(*hdr); 550 551 memcpy_fromio(pos, cdev->lpe_ba + cdev->dram.start, hdr->size); 552 pos += hdr->size; 553 554 hdr = (struct catpt_dump_section_hdr *)pos; 555 hdr->magic = CATPT_DUMP_MAGIC; 556 hdr->core_id = cdev->spec->core_id; 557 hdr->section_id = CATPT_DUMP_SECTION_ID_REGS; 558 hdr->size = regs_size; 559 pos += sizeof(*hdr); 560 561 memcpy_fromio(pos, catpt_shim_addr(cdev), CATPT_SHIM_REGS_SIZE); 562 pos += CATPT_SHIM_REGS_SIZE; 563 564 for (i = 0; i < CATPT_SSP_COUNT; i++) { 565 memcpy_fromio(pos, catpt_ssp_addr(cdev, i), 566 CATPT_SSP_REGS_SIZE); 567 pos += CATPT_SSP_REGS_SIZE; 568 } 569 for (i = 0; i < CATPT_DMA_COUNT; i++) { 570 memcpy_fromio(pos, catpt_dma_addr(cdev, i), 571 CATPT_DMA_REGS_SIZE); 572 pos += CATPT_DMA_REGS_SIZE; 573 } 574 575 dev_coredumpv(cdev->dev, dump, dump_size, GFP_KERNEL); 576 577 return 0; 578 } 579