1 /* 2 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms 3 * Cherrytrail and Braswell, with RT5672 codec. 4 * 5 * Copyright (C) 2014 Intel Corp 6 * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com> 7 * Mengdong Lin <mengdong.lin@intel.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/clk.h> 23 #include <asm/cpu_device_id.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/jack.h> 28 #include "../../codecs/rt5670.h" 29 #include "../atom/sst-atom-controls.h" 30 #include "../common/sst-acpi.h" 31 32 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */ 33 #define CHT_PLAT_CLK_3_HZ 19200000 34 #define CHT_CODEC_DAI "rt5670-aif1" 35 36 struct cht_mc_private { 37 struct snd_soc_jack headset; 38 char codec_name[16]; 39 struct clk *mclk; 40 }; 41 42 /* Headset jack detection DAPM pins */ 43 static struct snd_soc_jack_pin cht_bsw_headset_pins[] = { 44 { 45 .pin = "Headset Mic", 46 .mask = SND_JACK_MICROPHONE, 47 }, 48 { 49 .pin = "Headphone", 50 .mask = SND_JACK_HEADPHONE, 51 }, 52 }; 53 54 static inline struct snd_soc_dai *cht_get_codec_dai(struct snd_soc_card *card) 55 { 56 struct snd_soc_pcm_runtime *rtd; 57 58 list_for_each_entry(rtd, &card->rtd_list, list) { 59 if (!strncmp(rtd->codec_dai->name, CHT_CODEC_DAI, 60 strlen(CHT_CODEC_DAI))) 61 return rtd->codec_dai; 62 } 63 return NULL; 64 } 65 66 static int platform_clock_control(struct snd_soc_dapm_widget *w, 67 struct snd_kcontrol *k, int event) 68 { 69 struct snd_soc_dapm_context *dapm = w->dapm; 70 struct snd_soc_card *card = dapm->card; 71 struct snd_soc_dai *codec_dai; 72 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 73 int ret; 74 75 codec_dai = cht_get_codec_dai(card); 76 if (!codec_dai) { 77 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); 78 return -EIO; 79 } 80 81 if (SND_SOC_DAPM_EVENT_ON(event)) { 82 if (ctx->mclk) { 83 ret = clk_prepare_enable(ctx->mclk); 84 if (ret < 0) { 85 dev_err(card->dev, 86 "could not configure MCLK state"); 87 return ret; 88 } 89 } 90 91 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 92 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK, 93 CHT_PLAT_CLK_3_HZ, 48000 * 512); 94 if (ret < 0) { 95 dev_err(card->dev, "can't set codec pll: %d\n", ret); 96 return ret; 97 } 98 99 /* set codec sysclk source to PLL */ 100 ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1, 101 48000 * 512, SND_SOC_CLOCK_IN); 102 if (ret < 0) { 103 dev_err(card->dev, "can't set codec sysclk: %d\n", ret); 104 return ret; 105 } 106 } else { 107 /* Set codec sysclk source to its internal clock because codec 108 * PLL will be off when idle and MCLK will also be off by ACPI 109 * when codec is runtime suspended. Codec needs clock for jack 110 * detection and button press. 111 */ 112 snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_RCCLK, 113 48000 * 512, SND_SOC_CLOCK_IN); 114 115 if (ctx->mclk) 116 clk_disable_unprepare(ctx->mclk); 117 } 118 return 0; 119 } 120 121 static const struct snd_soc_dapm_widget cht_dapm_widgets[] = { 122 SND_SOC_DAPM_HP("Headphone", NULL), 123 SND_SOC_DAPM_MIC("Headset Mic", NULL), 124 SND_SOC_DAPM_MIC("Int Mic", NULL), 125 SND_SOC_DAPM_SPK("Ext Spk", NULL), 126 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0, 127 platform_clock_control, SND_SOC_DAPM_PRE_PMU | 128 SND_SOC_DAPM_POST_PMD), 129 }; 130 131 static const struct snd_soc_dapm_route cht_audio_map[] = { 132 {"IN1P", NULL, "Headset Mic"}, 133 {"IN1N", NULL, "Headset Mic"}, 134 {"DMIC L1", NULL, "Int Mic"}, 135 {"DMIC R1", NULL, "Int Mic"}, 136 {"Headphone", NULL, "HPOL"}, 137 {"Headphone", NULL, "HPOR"}, 138 {"Ext Spk", NULL, "SPOLP"}, 139 {"Ext Spk", NULL, "SPOLN"}, 140 {"Ext Spk", NULL, "SPORP"}, 141 {"Ext Spk", NULL, "SPORN"}, 142 {"AIF1 Playback", NULL, "ssp2 Tx"}, 143 {"ssp2 Tx", NULL, "codec_out0"}, 144 {"ssp2 Tx", NULL, "codec_out1"}, 145 {"codec_in0", NULL, "ssp2 Rx"}, 146 {"codec_in1", NULL, "ssp2 Rx"}, 147 {"ssp2 Rx", NULL, "AIF1 Capture"}, 148 {"Headphone", NULL, "Platform Clock"}, 149 {"Headset Mic", NULL, "Platform Clock"}, 150 {"Int Mic", NULL, "Platform Clock"}, 151 {"Ext Spk", NULL, "Platform Clock"}, 152 }; 153 154 static const struct snd_kcontrol_new cht_mc_controls[] = { 155 SOC_DAPM_PIN_SWITCH("Headphone"), 156 SOC_DAPM_PIN_SWITCH("Headset Mic"), 157 SOC_DAPM_PIN_SWITCH("Int Mic"), 158 SOC_DAPM_PIN_SWITCH("Ext Spk"), 159 }; 160 161 static int cht_aif1_hw_params(struct snd_pcm_substream *substream, 162 struct snd_pcm_hw_params *params) 163 { 164 struct snd_soc_pcm_runtime *rtd = substream->private_data; 165 struct snd_soc_dai *codec_dai = rtd->codec_dai; 166 int ret; 167 168 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 169 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK, 170 CHT_PLAT_CLK_3_HZ, params_rate(params) * 512); 171 if (ret < 0) { 172 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); 173 return ret; 174 } 175 176 /* set codec sysclk source to PLL */ 177 ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1, 178 params_rate(params) * 512, 179 SND_SOC_CLOCK_IN); 180 if (ret < 0) { 181 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); 182 return ret; 183 } 184 return 0; 185 } 186 187 static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 188 { 189 int ret; 190 struct snd_soc_dai *codec_dai = runtime->codec_dai; 191 struct snd_soc_codec *codec = codec_dai->codec; 192 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); 193 194 /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */ 195 ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xF, 0xF, 4, 24); 196 if (ret < 0) { 197 dev_err(runtime->dev, "can't set codec TDM slot %d\n", ret); 198 return ret; 199 } 200 201 /* Select codec ASRC clock source to track I2S1 clock, because codec 202 * is in slave mode and 100fs I2S format (BCLK = 100 * LRCLK) cannot 203 * be supported by RT5672. Otherwise, ASRC will be disabled and cause 204 * noise. 205 */ 206 rt5670_sel_asrc_clk_src(codec, 207 RT5670_DA_STEREO_FILTER 208 | RT5670_DA_MONO_L_FILTER 209 | RT5670_DA_MONO_R_FILTER 210 | RT5670_AD_STEREO_FILTER 211 | RT5670_AD_MONO_L_FILTER 212 | RT5670_AD_MONO_R_FILTER, 213 RT5670_CLK_SEL_I2S1_ASRC); 214 215 ret = snd_soc_card_jack_new(runtime->card, "Headset", 216 SND_JACK_HEADSET | SND_JACK_BTN_0 | 217 SND_JACK_BTN_1 | SND_JACK_BTN_2, 218 &ctx->headset, 219 cht_bsw_headset_pins, 220 ARRAY_SIZE(cht_bsw_headset_pins)); 221 if (ret) 222 return ret; 223 224 rt5670_set_jack_detect(codec, &ctx->headset); 225 if (ctx->mclk) { 226 /* 227 * The firmware might enable the clock at 228 * boot (this information may or may not 229 * be reflected in the enable clock register). 230 * To change the rate we must disable the clock 231 * first to cover these cases. Due to common 232 * clock framework restrictions that do not allow 233 * to disable a clock that has not been enabled, 234 * we need to enable the clock first. 235 */ 236 ret = clk_prepare_enable(ctx->mclk); 237 if (!ret) 238 clk_disable_unprepare(ctx->mclk); 239 240 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); 241 242 if (ret) { 243 dev_err(runtime->dev, "unable to set MCLK rate\n"); 244 return ret; 245 } 246 } 247 return 0; 248 } 249 250 static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd, 251 struct snd_pcm_hw_params *params) 252 { 253 struct snd_interval *rate = hw_param_interval(params, 254 SNDRV_PCM_HW_PARAM_RATE); 255 struct snd_interval *channels = hw_param_interval(params, 256 SNDRV_PCM_HW_PARAM_CHANNELS); 257 258 /* The DSP will covert the FE rate to 48k, stereo, 24bits */ 259 rate->min = rate->max = 48000; 260 channels->min = channels->max = 2; 261 262 /* set SSP2 to 24-bit */ 263 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE); 264 return 0; 265 } 266 267 static int cht_aif1_startup(struct snd_pcm_substream *substream) 268 { 269 return snd_pcm_hw_constraint_single(substream->runtime, 270 SNDRV_PCM_HW_PARAM_RATE, 48000); 271 } 272 273 static const struct snd_soc_ops cht_aif1_ops = { 274 .startup = cht_aif1_startup, 275 }; 276 277 static const struct snd_soc_ops cht_be_ssp2_ops = { 278 .hw_params = cht_aif1_hw_params, 279 }; 280 281 static struct snd_soc_dai_link cht_dailink[] = { 282 /* Front End DAI links */ 283 [MERR_DPCM_AUDIO] = { 284 .name = "Audio Port", 285 .stream_name = "Audio", 286 .cpu_dai_name = "media-cpu-dai", 287 .codec_dai_name = "snd-soc-dummy-dai", 288 .codec_name = "snd-soc-dummy", 289 .platform_name = "sst-mfld-platform", 290 .nonatomic = true, 291 .dynamic = 1, 292 .dpcm_playback = 1, 293 .dpcm_capture = 1, 294 .ops = &cht_aif1_ops, 295 }, 296 [MERR_DPCM_DEEP_BUFFER] = { 297 .name = "Deep-Buffer Audio Port", 298 .stream_name = "Deep-Buffer Audio", 299 .cpu_dai_name = "deepbuffer-cpu-dai", 300 .codec_dai_name = "snd-soc-dummy-dai", 301 .codec_name = "snd-soc-dummy", 302 .platform_name = "sst-mfld-platform", 303 .nonatomic = true, 304 .dynamic = 1, 305 .dpcm_playback = 1, 306 .ops = &cht_aif1_ops, 307 }, 308 [MERR_DPCM_COMPR] = { 309 .name = "Compressed Port", 310 .stream_name = "Compress", 311 .cpu_dai_name = "compress-cpu-dai", 312 .codec_dai_name = "snd-soc-dummy-dai", 313 .codec_name = "snd-soc-dummy", 314 .platform_name = "sst-mfld-platform", 315 }, 316 317 /* Back End DAI links */ 318 { 319 /* SSP2 - Codec */ 320 .name = "SSP2-Codec", 321 .id = 1, 322 .cpu_dai_name = "ssp2-port", 323 .platform_name = "sst-mfld-platform", 324 .no_pcm = 1, 325 .nonatomic = true, 326 .codec_dai_name = "rt5670-aif1", 327 .codec_name = "i2c-10EC5670:00", 328 .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF 329 | SND_SOC_DAIFMT_CBS_CFS, 330 .init = cht_codec_init, 331 .be_hw_params_fixup = cht_codec_fixup, 332 .dpcm_playback = 1, 333 .dpcm_capture = 1, 334 .ops = &cht_be_ssp2_ops, 335 }, 336 }; 337 338 static int cht_suspend_pre(struct snd_soc_card *card) 339 { 340 struct snd_soc_component *component; 341 342 list_for_each_entry(component, &card->component_dev_list, card_list) { 343 if (!strcmp(component->name, "i2c-10EC5670:00")) { 344 struct snd_soc_codec *codec = snd_soc_component_to_codec(component); 345 346 dev_dbg(codec->dev, "disabling jack detect before going to suspend.\n"); 347 rt5670_jack_suspend(codec); 348 break; 349 } 350 } 351 return 0; 352 } 353 354 static int cht_resume_post(struct snd_soc_card *card) 355 { 356 struct snd_soc_component *component; 357 358 list_for_each_entry(component, &card->component_dev_list, card_list) { 359 if (!strcmp(component->name, "i2c-10EC5670:00")) { 360 struct snd_soc_codec *codec = snd_soc_component_to_codec(component); 361 362 dev_dbg(codec->dev, "enabling jack detect for resume.\n"); 363 rt5670_jack_resume(codec); 364 break; 365 } 366 } 367 368 return 0; 369 } 370 371 /* SoC card */ 372 static struct snd_soc_card snd_soc_card_cht = { 373 .name = "cherrytrailcraudio", 374 .owner = THIS_MODULE, 375 .dai_link = cht_dailink, 376 .num_links = ARRAY_SIZE(cht_dailink), 377 .dapm_widgets = cht_dapm_widgets, 378 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets), 379 .dapm_routes = cht_audio_map, 380 .num_dapm_routes = ARRAY_SIZE(cht_audio_map), 381 .controls = cht_mc_controls, 382 .num_controls = ARRAY_SIZE(cht_mc_controls), 383 .suspend_pre = cht_suspend_pre, 384 .resume_post = cht_resume_post, 385 }; 386 387 static bool is_valleyview(void) 388 { 389 static const struct x86_cpu_id cpu_ids[] = { 390 { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ 391 {} 392 }; 393 394 if (!x86_match_cpu(cpu_ids)) 395 return false; 396 return true; 397 } 398 399 #define RT5672_I2C_DEFAULT "i2c-10EC5670:00" 400 401 static int snd_cht_mc_probe(struct platform_device *pdev) 402 { 403 int ret_val = 0; 404 struct cht_mc_private *drv; 405 struct sst_acpi_mach *mach = pdev->dev.platform_data; 406 const char *i2c_name; 407 int i; 408 409 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC); 410 if (!drv) 411 return -ENOMEM; 412 413 strcpy(drv->codec_name, RT5672_I2C_DEFAULT); 414 415 /* fixup codec name based on HID */ 416 if (mach) { 417 i2c_name = sst_acpi_find_name_from_hid(mach->id); 418 if (i2c_name) { 419 snprintf(drv->codec_name, sizeof(drv->codec_name), 420 "i2c-%s", i2c_name); 421 for (i = 0; i < ARRAY_SIZE(cht_dailink); i++) { 422 if (!strcmp(cht_dailink[i].codec_name, 423 RT5672_I2C_DEFAULT)) { 424 cht_dailink[i].codec_name = 425 drv->codec_name; 426 break; 427 } 428 } 429 } 430 } 431 432 if (is_valleyview()) { 433 drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); 434 if (IS_ERR(drv->mclk)) { 435 dev_err(&pdev->dev, 436 "Failed to get MCLK from pmc_plt_clk_3: %ld\n", 437 PTR_ERR(drv->mclk)); 438 return PTR_ERR(drv->mclk); 439 } 440 } 441 snd_soc_card_set_drvdata(&snd_soc_card_cht, drv); 442 443 /* register the soc card */ 444 snd_soc_card_cht.dev = &pdev->dev; 445 ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht); 446 if (ret_val) { 447 dev_err(&pdev->dev, 448 "snd_soc_register_card failed %d\n", ret_val); 449 return ret_val; 450 } 451 platform_set_drvdata(pdev, &snd_soc_card_cht); 452 return ret_val; 453 } 454 455 static struct platform_driver snd_cht_mc_driver = { 456 .driver = { 457 .name = "cht-bsw-rt5672", 458 }, 459 .probe = snd_cht_mc_probe, 460 }; 461 462 module_platform_driver(snd_cht_mc_driver); 463 464 MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver"); 465 MODULE_AUTHOR("Subhransu S. Prusty, Mengdong Lin"); 466 MODULE_LICENSE("GPL v2"); 467 MODULE_ALIAS("platform:cht-bsw-rt5672"); 468