1 /* 2 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms 3 * Cherrytrail and Braswell, with RT5672 codec. 4 * 5 * Copyright (C) 2014 Intel Corp 6 * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com> 7 * Mengdong Lin <mengdong.lin@intel.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include <linux/input.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/clk.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/jack.h> 28 #include <sound/soc-acpi.h> 29 #include "../../codecs/rt5670.h" 30 #include "../atom/sst-atom-controls.h" 31 32 33 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */ 34 #define CHT_PLAT_CLK_3_HZ 19200000 35 #define CHT_CODEC_DAI "rt5670-aif1" 36 37 struct cht_mc_private { 38 struct snd_soc_jack headset; 39 char codec_name[SND_ACPI_I2C_ID_LEN]; 40 struct clk *mclk; 41 }; 42 43 /* Headset jack detection DAPM pins */ 44 static struct snd_soc_jack_pin cht_bsw_headset_pins[] = { 45 { 46 .pin = "Headset Mic", 47 .mask = SND_JACK_MICROPHONE, 48 }, 49 { 50 .pin = "Headphone", 51 .mask = SND_JACK_HEADPHONE, 52 }, 53 }; 54 55 static int platform_clock_control(struct snd_soc_dapm_widget *w, 56 struct snd_kcontrol *k, int event) 57 { 58 struct snd_soc_dapm_context *dapm = w->dapm; 59 struct snd_soc_card *card = dapm->card; 60 struct snd_soc_dai *codec_dai; 61 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 62 int ret; 63 64 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI); 65 if (!codec_dai) { 66 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); 67 return -EIO; 68 } 69 70 if (SND_SOC_DAPM_EVENT_ON(event)) { 71 if (ctx->mclk) { 72 ret = clk_prepare_enable(ctx->mclk); 73 if (ret < 0) { 74 dev_err(card->dev, 75 "could not configure MCLK state"); 76 return ret; 77 } 78 } 79 80 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 81 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK, 82 CHT_PLAT_CLK_3_HZ, 48000 * 512); 83 if (ret < 0) { 84 dev_err(card->dev, "can't set codec pll: %d\n", ret); 85 return ret; 86 } 87 88 /* set codec sysclk source to PLL */ 89 ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1, 90 48000 * 512, SND_SOC_CLOCK_IN); 91 if (ret < 0) { 92 dev_err(card->dev, "can't set codec sysclk: %d\n", ret); 93 return ret; 94 } 95 } else { 96 /* Set codec sysclk source to its internal clock because codec 97 * PLL will be off when idle and MCLK will also be off by ACPI 98 * when codec is runtime suspended. Codec needs clock for jack 99 * detection and button press. 100 */ 101 snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_RCCLK, 102 48000 * 512, SND_SOC_CLOCK_IN); 103 104 if (ctx->mclk) 105 clk_disable_unprepare(ctx->mclk); 106 } 107 return 0; 108 } 109 110 static const struct snd_soc_dapm_widget cht_dapm_widgets[] = { 111 SND_SOC_DAPM_HP("Headphone", NULL), 112 SND_SOC_DAPM_MIC("Headset Mic", NULL), 113 SND_SOC_DAPM_MIC("Int Mic", NULL), 114 SND_SOC_DAPM_SPK("Ext Spk", NULL), 115 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0, 116 platform_clock_control, SND_SOC_DAPM_PRE_PMU | 117 SND_SOC_DAPM_POST_PMD), 118 }; 119 120 static const struct snd_soc_dapm_route cht_audio_map[] = { 121 {"IN1P", NULL, "Headset Mic"}, 122 {"IN1N", NULL, "Headset Mic"}, 123 {"DMIC L1", NULL, "Int Mic"}, 124 {"DMIC R1", NULL, "Int Mic"}, 125 {"Headphone", NULL, "HPOL"}, 126 {"Headphone", NULL, "HPOR"}, 127 {"Ext Spk", NULL, "SPOLP"}, 128 {"Ext Spk", NULL, "SPOLN"}, 129 {"Ext Spk", NULL, "SPORP"}, 130 {"Ext Spk", NULL, "SPORN"}, 131 {"AIF1 Playback", NULL, "ssp2 Tx"}, 132 {"ssp2 Tx", NULL, "codec_out0"}, 133 {"ssp2 Tx", NULL, "codec_out1"}, 134 {"codec_in0", NULL, "ssp2 Rx"}, 135 {"codec_in1", NULL, "ssp2 Rx"}, 136 {"ssp2 Rx", NULL, "AIF1 Capture"}, 137 {"Headphone", NULL, "Platform Clock"}, 138 {"Headset Mic", NULL, "Platform Clock"}, 139 {"Int Mic", NULL, "Platform Clock"}, 140 {"Ext Spk", NULL, "Platform Clock"}, 141 }; 142 143 static const struct snd_kcontrol_new cht_mc_controls[] = { 144 SOC_DAPM_PIN_SWITCH("Headphone"), 145 SOC_DAPM_PIN_SWITCH("Headset Mic"), 146 SOC_DAPM_PIN_SWITCH("Int Mic"), 147 SOC_DAPM_PIN_SWITCH("Ext Spk"), 148 }; 149 150 static int cht_aif1_hw_params(struct snd_pcm_substream *substream, 151 struct snd_pcm_hw_params *params) 152 { 153 struct snd_soc_pcm_runtime *rtd = substream->private_data; 154 struct snd_soc_dai *codec_dai = rtd->codec_dai; 155 int ret; 156 157 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 158 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK, 159 CHT_PLAT_CLK_3_HZ, params_rate(params) * 512); 160 if (ret < 0) { 161 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); 162 return ret; 163 } 164 165 /* set codec sysclk source to PLL */ 166 ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1, 167 params_rate(params) * 512, 168 SND_SOC_CLOCK_IN); 169 if (ret < 0) { 170 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); 171 return ret; 172 } 173 return 0; 174 } 175 176 static const struct acpi_gpio_params headset_gpios = { 0, 0, false }; 177 178 static const struct acpi_gpio_mapping cht_rt5672_gpios[] = { 179 { "headset-gpios", &headset_gpios, 1 }, 180 {}, 181 }; 182 183 static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 184 { 185 int ret; 186 struct snd_soc_dai *codec_dai = runtime->codec_dai; 187 struct snd_soc_component *component = codec_dai->component; 188 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); 189 190 if (devm_acpi_dev_add_driver_gpios(component->dev, cht_rt5672_gpios)) 191 dev_warn(runtime->dev, "Unable to add GPIO mapping table\n"); 192 193 /* Select codec ASRC clock source to track I2S1 clock, because codec 194 * is in slave mode and 100fs I2S format (BCLK = 100 * LRCLK) cannot 195 * be supported by RT5672. Otherwise, ASRC will be disabled and cause 196 * noise. 197 */ 198 rt5670_sel_asrc_clk_src(component, 199 RT5670_DA_STEREO_FILTER 200 | RT5670_DA_MONO_L_FILTER 201 | RT5670_DA_MONO_R_FILTER 202 | RT5670_AD_STEREO_FILTER 203 | RT5670_AD_MONO_L_FILTER 204 | RT5670_AD_MONO_R_FILTER, 205 RT5670_CLK_SEL_I2S1_ASRC); 206 207 ret = snd_soc_card_jack_new(runtime->card, "Headset", 208 SND_JACK_HEADSET | SND_JACK_BTN_0 | 209 SND_JACK_BTN_1 | SND_JACK_BTN_2, 210 &ctx->headset, 211 cht_bsw_headset_pins, 212 ARRAY_SIZE(cht_bsw_headset_pins)); 213 if (ret) 214 return ret; 215 216 snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); 217 snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_1, KEY_VOLUMEUP); 218 snd_jack_set_key(ctx->headset.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN); 219 220 rt5670_set_jack_detect(component, &ctx->headset); 221 if (ctx->mclk) { 222 /* 223 * The firmware might enable the clock at 224 * boot (this information may or may not 225 * be reflected in the enable clock register). 226 * To change the rate we must disable the clock 227 * first to cover these cases. Due to common 228 * clock framework restrictions that do not allow 229 * to disable a clock that has not been enabled, 230 * we need to enable the clock first. 231 */ 232 ret = clk_prepare_enable(ctx->mclk); 233 if (!ret) 234 clk_disable_unprepare(ctx->mclk); 235 236 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); 237 238 if (ret) { 239 dev_err(runtime->dev, "unable to set MCLK rate\n"); 240 return ret; 241 } 242 } 243 return 0; 244 } 245 246 static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd, 247 struct snd_pcm_hw_params *params) 248 { 249 struct snd_interval *rate = hw_param_interval(params, 250 SNDRV_PCM_HW_PARAM_RATE); 251 struct snd_interval *channels = hw_param_interval(params, 252 SNDRV_PCM_HW_PARAM_CHANNELS); 253 int ret; 254 255 /* The DSP will covert the FE rate to 48k, stereo, 24bits */ 256 rate->min = rate->max = 48000; 257 channels->min = channels->max = 2; 258 259 /* set SSP2 to 24-bit */ 260 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE); 261 262 /* 263 * Default mode for SSP configuration is TDM 4 slot 264 */ 265 ret = snd_soc_dai_set_fmt(rtd->codec_dai, 266 SND_SOC_DAIFMT_DSP_B | 267 SND_SOC_DAIFMT_IB_NF | 268 SND_SOC_DAIFMT_CBS_CFS); 269 if (ret < 0) { 270 dev_err(rtd->dev, "can't set format to TDM %d\n", ret); 271 return ret; 272 } 273 274 /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */ 275 ret = snd_soc_dai_set_tdm_slot(rtd->codec_dai, 0xF, 0xF, 4, 24); 276 if (ret < 0) { 277 dev_err(rtd->dev, "can't set codec TDM slot %d\n", ret); 278 return ret; 279 } 280 281 return 0; 282 } 283 284 static int cht_aif1_startup(struct snd_pcm_substream *substream) 285 { 286 return snd_pcm_hw_constraint_single(substream->runtime, 287 SNDRV_PCM_HW_PARAM_RATE, 48000); 288 } 289 290 static const struct snd_soc_ops cht_aif1_ops = { 291 .startup = cht_aif1_startup, 292 }; 293 294 static const struct snd_soc_ops cht_be_ssp2_ops = { 295 .hw_params = cht_aif1_hw_params, 296 }; 297 298 SND_SOC_DAILINK_DEF(dummy, 299 DAILINK_COMP_ARRAY(COMP_DUMMY())); 300 301 SND_SOC_DAILINK_DEF(media, 302 DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai"))); 303 304 SND_SOC_DAILINK_DEF(deepbuffer, 305 DAILINK_COMP_ARRAY(COMP_CPU("deepbuffer-cpu-dai"))); 306 307 SND_SOC_DAILINK_DEF(ssp2_port, 308 DAILINK_COMP_ARRAY(COMP_CPU("ssp2-port"))); 309 SND_SOC_DAILINK_DEF(ssp2_codec, 310 DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5670:00", 311 "rt5670-aif1"))); 312 313 SND_SOC_DAILINK_DEF(platform, 314 DAILINK_COMP_ARRAY(COMP_PLATFORM("sst-mfld-platform"))); 315 316 static struct snd_soc_dai_link cht_dailink[] = { 317 /* Front End DAI links */ 318 [MERR_DPCM_AUDIO] = { 319 .name = "Audio Port", 320 .stream_name = "Audio", 321 .nonatomic = true, 322 .dynamic = 1, 323 .dpcm_playback = 1, 324 .dpcm_capture = 1, 325 .ops = &cht_aif1_ops, 326 SND_SOC_DAILINK_REG(media, dummy, platform), 327 }, 328 [MERR_DPCM_DEEP_BUFFER] = { 329 .name = "Deep-Buffer Audio Port", 330 .stream_name = "Deep-Buffer Audio", 331 .nonatomic = true, 332 .dynamic = 1, 333 .dpcm_playback = 1, 334 .ops = &cht_aif1_ops, 335 SND_SOC_DAILINK_REG(deepbuffer, dummy, platform), 336 }, 337 338 /* Back End DAI links */ 339 { 340 /* SSP2 - Codec */ 341 .name = "SSP2-Codec", 342 .id = 0, 343 .no_pcm = 1, 344 .nonatomic = true, 345 .init = cht_codec_init, 346 .be_hw_params_fixup = cht_codec_fixup, 347 .dpcm_playback = 1, 348 .dpcm_capture = 1, 349 .ops = &cht_be_ssp2_ops, 350 SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform), 351 }, 352 }; 353 354 static int cht_suspend_pre(struct snd_soc_card *card) 355 { 356 struct snd_soc_component *component; 357 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 358 359 for_each_card_components(card, component) { 360 if (!strncmp(component->name, 361 ctx->codec_name, sizeof(ctx->codec_name))) { 362 363 dev_dbg(component->dev, "disabling jack detect before going to suspend.\n"); 364 rt5670_jack_suspend(component); 365 break; 366 } 367 } 368 return 0; 369 } 370 371 static int cht_resume_post(struct snd_soc_card *card) 372 { 373 struct snd_soc_component *component; 374 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 375 376 for_each_card_components(card, component) { 377 if (!strncmp(component->name, 378 ctx->codec_name, sizeof(ctx->codec_name))) { 379 380 dev_dbg(component->dev, "enabling jack detect for resume.\n"); 381 rt5670_jack_resume(component); 382 break; 383 } 384 } 385 386 return 0; 387 } 388 389 /* SoC card */ 390 static struct snd_soc_card snd_soc_card_cht = { 391 .name = "cht-bsw-rt5672", 392 .owner = THIS_MODULE, 393 .dai_link = cht_dailink, 394 .num_links = ARRAY_SIZE(cht_dailink), 395 .dapm_widgets = cht_dapm_widgets, 396 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets), 397 .dapm_routes = cht_audio_map, 398 .num_dapm_routes = ARRAY_SIZE(cht_audio_map), 399 .controls = cht_mc_controls, 400 .num_controls = ARRAY_SIZE(cht_mc_controls), 401 .suspend_pre = cht_suspend_pre, 402 .resume_post = cht_resume_post, 403 }; 404 405 #define RT5672_I2C_DEFAULT "i2c-10EC5670:00" 406 407 static int snd_cht_mc_probe(struct platform_device *pdev) 408 { 409 int ret_val = 0; 410 struct cht_mc_private *drv; 411 struct snd_soc_acpi_mach *mach = pdev->dev.platform_data; 412 const char *platform_name; 413 struct acpi_device *adev; 414 int i; 415 416 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); 417 if (!drv) 418 return -ENOMEM; 419 420 strcpy(drv->codec_name, RT5672_I2C_DEFAULT); 421 422 /* fixup codec name based on HID */ 423 adev = acpi_dev_get_first_match_dev(mach->id, NULL, -1); 424 if (adev) { 425 snprintf(drv->codec_name, sizeof(drv->codec_name), 426 "i2c-%s", acpi_dev_name(adev)); 427 put_device(&adev->dev); 428 for (i = 0; i < ARRAY_SIZE(cht_dailink); i++) { 429 if (!strcmp(cht_dailink[i].codecs->name, 430 RT5672_I2C_DEFAULT)) { 431 cht_dailink[i].codecs->name = drv->codec_name; 432 break; 433 } 434 } 435 } 436 437 /* override plaform name, if required */ 438 platform_name = mach->mach_params.platform; 439 440 ret_val = snd_soc_fixup_dai_links_platform_name(&snd_soc_card_cht, 441 platform_name); 442 if (ret_val) 443 return ret_val; 444 445 drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); 446 if (IS_ERR(drv->mclk)) { 447 dev_err(&pdev->dev, 448 "Failed to get MCLK from pmc_plt_clk_3: %ld\n", 449 PTR_ERR(drv->mclk)); 450 return PTR_ERR(drv->mclk); 451 } 452 snd_soc_card_set_drvdata(&snd_soc_card_cht, drv); 453 454 /* register the soc card */ 455 snd_soc_card_cht.dev = &pdev->dev; 456 ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht); 457 if (ret_val) { 458 dev_err(&pdev->dev, 459 "snd_soc_register_card failed %d\n", ret_val); 460 return ret_val; 461 } 462 platform_set_drvdata(pdev, &snd_soc_card_cht); 463 return ret_val; 464 } 465 466 static struct platform_driver snd_cht_mc_driver = { 467 .driver = { 468 .name = "cht-bsw-rt5672", 469 }, 470 .probe = snd_cht_mc_probe, 471 }; 472 473 module_platform_driver(snd_cht_mc_driver); 474 475 MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver"); 476 MODULE_AUTHOR("Subhransu S. Prusty, Mengdong Lin"); 477 MODULE_LICENSE("GPL v2"); 478 MODULE_ALIAS("platform:cht-bsw-rt5672"); 479