1 /* 2 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms 3 * Cherrytrail and Braswell, with RT5672 codec. 4 * 5 * Copyright (C) 2014 Intel Corp 6 * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com> 7 * Mengdong Lin <mengdong.lin@intel.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/clk.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/jack.h> 27 #include "../../codecs/rt5670.h" 28 #include "../atom/sst-atom-controls.h" 29 #include "../common/sst-acpi.h" 30 31 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */ 32 #define CHT_PLAT_CLK_3_HZ 19200000 33 #define CHT_CODEC_DAI "rt5670-aif1" 34 35 struct cht_mc_private { 36 struct snd_soc_jack headset; 37 char codec_name[16]; 38 struct clk *mclk; 39 }; 40 41 /* Headset jack detection DAPM pins */ 42 static struct snd_soc_jack_pin cht_bsw_headset_pins[] = { 43 { 44 .pin = "Headset Mic", 45 .mask = SND_JACK_MICROPHONE, 46 }, 47 { 48 .pin = "Headphone", 49 .mask = SND_JACK_HEADPHONE, 50 }, 51 }; 52 53 static int platform_clock_control(struct snd_soc_dapm_widget *w, 54 struct snd_kcontrol *k, int event) 55 { 56 struct snd_soc_dapm_context *dapm = w->dapm; 57 struct snd_soc_card *card = dapm->card; 58 struct snd_soc_dai *codec_dai; 59 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 60 int ret; 61 62 codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI); 63 if (!codec_dai) { 64 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); 65 return -EIO; 66 } 67 68 if (SND_SOC_DAPM_EVENT_ON(event)) { 69 if (ctx->mclk) { 70 ret = clk_prepare_enable(ctx->mclk); 71 if (ret < 0) { 72 dev_err(card->dev, 73 "could not configure MCLK state"); 74 return ret; 75 } 76 } 77 78 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 79 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK, 80 CHT_PLAT_CLK_3_HZ, 48000 * 512); 81 if (ret < 0) { 82 dev_err(card->dev, "can't set codec pll: %d\n", ret); 83 return ret; 84 } 85 86 /* set codec sysclk source to PLL */ 87 ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1, 88 48000 * 512, SND_SOC_CLOCK_IN); 89 if (ret < 0) { 90 dev_err(card->dev, "can't set codec sysclk: %d\n", ret); 91 return ret; 92 } 93 } else { 94 /* Set codec sysclk source to its internal clock because codec 95 * PLL will be off when idle and MCLK will also be off by ACPI 96 * when codec is runtime suspended. Codec needs clock for jack 97 * detection and button press. 98 */ 99 snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_RCCLK, 100 48000 * 512, SND_SOC_CLOCK_IN); 101 102 if (ctx->mclk) 103 clk_disable_unprepare(ctx->mclk); 104 } 105 return 0; 106 } 107 108 static const struct snd_soc_dapm_widget cht_dapm_widgets[] = { 109 SND_SOC_DAPM_HP("Headphone", NULL), 110 SND_SOC_DAPM_MIC("Headset Mic", NULL), 111 SND_SOC_DAPM_MIC("Int Mic", NULL), 112 SND_SOC_DAPM_SPK("Ext Spk", NULL), 113 SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0, 114 platform_clock_control, SND_SOC_DAPM_PRE_PMU | 115 SND_SOC_DAPM_POST_PMD), 116 }; 117 118 static const struct snd_soc_dapm_route cht_audio_map[] = { 119 {"IN1P", NULL, "Headset Mic"}, 120 {"IN1N", NULL, "Headset Mic"}, 121 {"DMIC L1", NULL, "Int Mic"}, 122 {"DMIC R1", NULL, "Int Mic"}, 123 {"Headphone", NULL, "HPOL"}, 124 {"Headphone", NULL, "HPOR"}, 125 {"Ext Spk", NULL, "SPOLP"}, 126 {"Ext Spk", NULL, "SPOLN"}, 127 {"Ext Spk", NULL, "SPORP"}, 128 {"Ext Spk", NULL, "SPORN"}, 129 {"AIF1 Playback", NULL, "ssp2 Tx"}, 130 {"ssp2 Tx", NULL, "codec_out0"}, 131 {"ssp2 Tx", NULL, "codec_out1"}, 132 {"codec_in0", NULL, "ssp2 Rx"}, 133 {"codec_in1", NULL, "ssp2 Rx"}, 134 {"ssp2 Rx", NULL, "AIF1 Capture"}, 135 {"Headphone", NULL, "Platform Clock"}, 136 {"Headset Mic", NULL, "Platform Clock"}, 137 {"Int Mic", NULL, "Platform Clock"}, 138 {"Ext Spk", NULL, "Platform Clock"}, 139 }; 140 141 static const struct snd_kcontrol_new cht_mc_controls[] = { 142 SOC_DAPM_PIN_SWITCH("Headphone"), 143 SOC_DAPM_PIN_SWITCH("Headset Mic"), 144 SOC_DAPM_PIN_SWITCH("Int Mic"), 145 SOC_DAPM_PIN_SWITCH("Ext Spk"), 146 }; 147 148 static int cht_aif1_hw_params(struct snd_pcm_substream *substream, 149 struct snd_pcm_hw_params *params) 150 { 151 struct snd_soc_pcm_runtime *rtd = substream->private_data; 152 struct snd_soc_dai *codec_dai = rtd->codec_dai; 153 int ret; 154 155 /* set codec PLL source to the 19.2MHz platform clock (MCLK) */ 156 ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK, 157 CHT_PLAT_CLK_3_HZ, params_rate(params) * 512); 158 if (ret < 0) { 159 dev_err(rtd->dev, "can't set codec pll: %d\n", ret); 160 return ret; 161 } 162 163 /* set codec sysclk source to PLL */ 164 ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1, 165 params_rate(params) * 512, 166 SND_SOC_CLOCK_IN); 167 if (ret < 0) { 168 dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret); 169 return ret; 170 } 171 return 0; 172 } 173 174 static const struct acpi_gpio_params headset_gpios = { 0, 0, false }; 175 176 static const struct acpi_gpio_mapping cht_rt5672_gpios[] = { 177 { "headset-gpios", &headset_gpios, 1 }, 178 {}, 179 }; 180 181 static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) 182 { 183 int ret; 184 struct snd_soc_dai *codec_dai = runtime->codec_dai; 185 struct snd_soc_codec *codec = codec_dai->codec; 186 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); 187 188 if (devm_acpi_dev_add_driver_gpios(codec->dev, cht_rt5672_gpios)) 189 dev_warn(runtime->dev, "Unable to add GPIO mapping table\n"); 190 191 /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */ 192 ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xF, 0xF, 4, 24); 193 if (ret < 0) { 194 dev_err(runtime->dev, "can't set codec TDM slot %d\n", ret); 195 return ret; 196 } 197 198 /* Select codec ASRC clock source to track I2S1 clock, because codec 199 * is in slave mode and 100fs I2S format (BCLK = 100 * LRCLK) cannot 200 * be supported by RT5672. Otherwise, ASRC will be disabled and cause 201 * noise. 202 */ 203 rt5670_sel_asrc_clk_src(codec, 204 RT5670_DA_STEREO_FILTER 205 | RT5670_DA_MONO_L_FILTER 206 | RT5670_DA_MONO_R_FILTER 207 | RT5670_AD_STEREO_FILTER 208 | RT5670_AD_MONO_L_FILTER 209 | RT5670_AD_MONO_R_FILTER, 210 RT5670_CLK_SEL_I2S1_ASRC); 211 212 ret = snd_soc_card_jack_new(runtime->card, "Headset", 213 SND_JACK_HEADSET | SND_JACK_BTN_0 | 214 SND_JACK_BTN_1 | SND_JACK_BTN_2, 215 &ctx->headset, 216 cht_bsw_headset_pins, 217 ARRAY_SIZE(cht_bsw_headset_pins)); 218 if (ret) 219 return ret; 220 221 rt5670_set_jack_detect(codec, &ctx->headset); 222 if (ctx->mclk) { 223 /* 224 * The firmware might enable the clock at 225 * boot (this information may or may not 226 * be reflected in the enable clock register). 227 * To change the rate we must disable the clock 228 * first to cover these cases. Due to common 229 * clock framework restrictions that do not allow 230 * to disable a clock that has not been enabled, 231 * we need to enable the clock first. 232 */ 233 ret = clk_prepare_enable(ctx->mclk); 234 if (!ret) 235 clk_disable_unprepare(ctx->mclk); 236 237 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); 238 239 if (ret) { 240 dev_err(runtime->dev, "unable to set MCLK rate\n"); 241 return ret; 242 } 243 } 244 return 0; 245 } 246 247 static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd, 248 struct snd_pcm_hw_params *params) 249 { 250 struct snd_interval *rate = hw_param_interval(params, 251 SNDRV_PCM_HW_PARAM_RATE); 252 struct snd_interval *channels = hw_param_interval(params, 253 SNDRV_PCM_HW_PARAM_CHANNELS); 254 255 /* The DSP will covert the FE rate to 48k, stereo, 24bits */ 256 rate->min = rate->max = 48000; 257 channels->min = channels->max = 2; 258 259 /* set SSP2 to 24-bit */ 260 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE); 261 return 0; 262 } 263 264 static int cht_aif1_startup(struct snd_pcm_substream *substream) 265 { 266 return snd_pcm_hw_constraint_single(substream->runtime, 267 SNDRV_PCM_HW_PARAM_RATE, 48000); 268 } 269 270 static const struct snd_soc_ops cht_aif1_ops = { 271 .startup = cht_aif1_startup, 272 }; 273 274 static const struct snd_soc_ops cht_be_ssp2_ops = { 275 .hw_params = cht_aif1_hw_params, 276 }; 277 278 static struct snd_soc_dai_link cht_dailink[] = { 279 /* Front End DAI links */ 280 [MERR_DPCM_AUDIO] = { 281 .name = "Audio Port", 282 .stream_name = "Audio", 283 .cpu_dai_name = "media-cpu-dai", 284 .codec_dai_name = "snd-soc-dummy-dai", 285 .codec_name = "snd-soc-dummy", 286 .platform_name = "sst-mfld-platform", 287 .nonatomic = true, 288 .dynamic = 1, 289 .dpcm_playback = 1, 290 .dpcm_capture = 1, 291 .ops = &cht_aif1_ops, 292 }, 293 [MERR_DPCM_DEEP_BUFFER] = { 294 .name = "Deep-Buffer Audio Port", 295 .stream_name = "Deep-Buffer Audio", 296 .cpu_dai_name = "deepbuffer-cpu-dai", 297 .codec_dai_name = "snd-soc-dummy-dai", 298 .codec_name = "snd-soc-dummy", 299 .platform_name = "sst-mfld-platform", 300 .nonatomic = true, 301 .dynamic = 1, 302 .dpcm_playback = 1, 303 .ops = &cht_aif1_ops, 304 }, 305 306 /* Back End DAI links */ 307 { 308 /* SSP2 - Codec */ 309 .name = "SSP2-Codec", 310 .id = 0, 311 .cpu_dai_name = "ssp2-port", 312 .platform_name = "sst-mfld-platform", 313 .no_pcm = 1, 314 .nonatomic = true, 315 .codec_dai_name = "rt5670-aif1", 316 .codec_name = "i2c-10EC5670:00", 317 .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF 318 | SND_SOC_DAIFMT_CBS_CFS, 319 .init = cht_codec_init, 320 .be_hw_params_fixup = cht_codec_fixup, 321 .dpcm_playback = 1, 322 .dpcm_capture = 1, 323 .ops = &cht_be_ssp2_ops, 324 }, 325 }; 326 327 static int cht_suspend_pre(struct snd_soc_card *card) 328 { 329 struct snd_soc_component *component; 330 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 331 332 list_for_each_entry(component, &card->component_dev_list, card_list) { 333 if (!strncmp(component->name, 334 ctx->codec_name, sizeof(ctx->codec_name))) { 335 struct snd_soc_codec *codec = snd_soc_component_to_codec(component); 336 337 dev_dbg(codec->dev, "disabling jack detect before going to suspend.\n"); 338 rt5670_jack_suspend(codec); 339 break; 340 } 341 } 342 return 0; 343 } 344 345 static int cht_resume_post(struct snd_soc_card *card) 346 { 347 struct snd_soc_component *component; 348 struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card); 349 350 list_for_each_entry(component, &card->component_dev_list, card_list) { 351 if (!strncmp(component->name, 352 ctx->codec_name, sizeof(ctx->codec_name))) { 353 struct snd_soc_codec *codec = snd_soc_component_to_codec(component); 354 355 dev_dbg(codec->dev, "enabling jack detect for resume.\n"); 356 rt5670_jack_resume(codec); 357 break; 358 } 359 } 360 361 return 0; 362 } 363 364 /* SoC card */ 365 static struct snd_soc_card snd_soc_card_cht = { 366 .name = "cht-bsw-rt5672", 367 .owner = THIS_MODULE, 368 .dai_link = cht_dailink, 369 .num_links = ARRAY_SIZE(cht_dailink), 370 .dapm_widgets = cht_dapm_widgets, 371 .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets), 372 .dapm_routes = cht_audio_map, 373 .num_dapm_routes = ARRAY_SIZE(cht_audio_map), 374 .controls = cht_mc_controls, 375 .num_controls = ARRAY_SIZE(cht_mc_controls), 376 .suspend_pre = cht_suspend_pre, 377 .resume_post = cht_resume_post, 378 }; 379 380 #define RT5672_I2C_DEFAULT "i2c-10EC5670:00" 381 382 static int snd_cht_mc_probe(struct platform_device *pdev) 383 { 384 int ret_val = 0; 385 struct cht_mc_private *drv; 386 struct sst_acpi_mach *mach = pdev->dev.platform_data; 387 const char *i2c_name; 388 int i; 389 390 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC); 391 if (!drv) 392 return -ENOMEM; 393 394 strcpy(drv->codec_name, RT5672_I2C_DEFAULT); 395 396 /* fixup codec name based on HID */ 397 if (mach) { 398 i2c_name = sst_acpi_find_name_from_hid(mach->id); 399 if (i2c_name) { 400 snprintf(drv->codec_name, sizeof(drv->codec_name), 401 "i2c-%s", i2c_name); 402 for (i = 0; i < ARRAY_SIZE(cht_dailink); i++) { 403 if (!strcmp(cht_dailink[i].codec_name, 404 RT5672_I2C_DEFAULT)) { 405 cht_dailink[i].codec_name = 406 drv->codec_name; 407 break; 408 } 409 } 410 } 411 } 412 413 drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); 414 if (IS_ERR(drv->mclk)) { 415 dev_err(&pdev->dev, 416 "Failed to get MCLK from pmc_plt_clk_3: %ld\n", 417 PTR_ERR(drv->mclk)); 418 return PTR_ERR(drv->mclk); 419 } 420 snd_soc_card_set_drvdata(&snd_soc_card_cht, drv); 421 422 /* register the soc card */ 423 snd_soc_card_cht.dev = &pdev->dev; 424 ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht); 425 if (ret_val) { 426 dev_err(&pdev->dev, 427 "snd_soc_register_card failed %d\n", ret_val); 428 return ret_val; 429 } 430 platform_set_drvdata(pdev, &snd_soc_card_cht); 431 return ret_val; 432 } 433 434 static struct platform_driver snd_cht_mc_driver = { 435 .driver = { 436 .name = "cht-bsw-rt5672", 437 }, 438 .probe = snd_cht_mc_probe, 439 }; 440 441 module_platform_driver(snd_cht_mc_driver); 442 443 MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver"); 444 MODULE_AUTHOR("Subhransu S. Prusty, Mengdong Lin"); 445 MODULE_LICENSE("GPL v2"); 446 MODULE_ALIAS("platform:cht-bsw-rt5672"); 447