1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 // 8 // Special thanks to: 9 // Krzysztof Hejmowski <krzysztof.hejmowski@intel.com> 10 // Michal Sienkiewicz <michal.sienkiewicz@intel.com> 11 // Filip Proborszcz 12 // 13 // for sharing Intel AudioDSP expertise and helping shape the very 14 // foundation of this driver 15 // 16 17 #include <linux/pci.h> 18 #include <sound/hdaudio.h> 19 #include "avs.h" 20 21 static void 22 avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value) 23 { 24 struct pci_dev *pci = to_pci_dev(bus->dev); 25 u32 data; 26 27 pci_read_config_dword(pci, reg, &data); 28 data &= ~mask; 29 data |= (value & mask); 30 pci_write_config_dword(pci, reg, data); 31 } 32 33 void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable) 34 { 35 u32 value; 36 37 value = enable ? 0 : AZX_PGCTL_LSRMD_MASK; 38 avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL, 39 AZX_PGCTL_LSRMD_MASK, value); 40 } 41 42 static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable) 43 { 44 u32 value; 45 46 value = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 47 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, value); 48 } 49 50 void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable) 51 { 52 avs_hdac_clock_gating_enable(&adev->base.core, enable); 53 } 54 55 void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable) 56 { 57 u32 value; 58 59 value = enable ? AZX_VS_EM2_L1SEN : 0; 60 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value); 61 } 62