1 /* 2 * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration. 3 * 4 * Copyright (c) 2013, Intel Corporation. 5 * 6 * Authors: Ramesh Babu K V <Ramesh.Babu@intel.com> 7 * Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * 19 */ 20 21 #include <linux/module.h> 22 #include <linux/fs.h> 23 #include <linux/interrupt.h> 24 #include <linux/slab.h> 25 #include <linux/io.h> 26 #include <linux/miscdevice.h> 27 #include <linux/platform_device.h> 28 #include <linux/firmware.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/pm_qos.h> 31 #include <linux/dmi.h> 32 #include <linux/acpi.h> 33 #include <asm/platform_sst_audio.h> 34 #include <sound/core.h> 35 #include <sound/soc.h> 36 #include <sound/compress_driver.h> 37 #include <acpi/acbuffer.h> 38 #include <acpi/platform/acenv.h> 39 #include <acpi/platform/aclinux.h> 40 #include <acpi/actypes.h> 41 #include <acpi/acpi_bus.h> 42 #include <asm/cpu_device_id.h> 43 #include <asm/iosf_mbi.h> 44 #include "../sst-mfld-platform.h" 45 #include "../../common/sst-dsp.h" 46 #include "../../common/sst-acpi.h" 47 #include "sst.h" 48 49 /* LPE viewpoint addresses */ 50 #define SST_BYT_IRAM_PHY_START 0xff2c0000 51 #define SST_BYT_IRAM_PHY_END 0xff2d4000 52 #define SST_BYT_DRAM_PHY_START 0xff300000 53 #define SST_BYT_DRAM_PHY_END 0xff320000 54 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */ 55 #define SST_BYT_IMR_VIRT_END 0xc01fffff 56 #define SST_BYT_SHIM_PHY_ADDR 0xff340000 57 #define SST_BYT_MBOX_PHY_ADDR 0xff344000 58 #define SST_BYT_DMA0_PHY_ADDR 0xff298000 59 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000 60 #define SST_BYT_SSP0_PHY_ADDR 0xff2a0000 61 #define SST_BYT_SSP2_PHY_ADDR 0xff2a2000 62 63 #define BYT_FW_MOD_TABLE_OFFSET 0x80000 64 #define BYT_FW_MOD_TABLE_SIZE 0x100 65 #define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE) 66 67 static const struct sst_info byt_fwparse_info = { 68 .use_elf = false, 69 .max_streams = 25, 70 .iram_start = SST_BYT_IRAM_PHY_START, 71 .iram_end = SST_BYT_IRAM_PHY_END, 72 .iram_use = true, 73 .dram_start = SST_BYT_DRAM_PHY_START, 74 .dram_end = SST_BYT_DRAM_PHY_END, 75 .dram_use = true, 76 .imr_start = SST_BYT_IMR_VIRT_START, 77 .imr_end = SST_BYT_IMR_VIRT_END, 78 .imr_use = true, 79 .mailbox_start = SST_BYT_MBOX_PHY_ADDR, 80 .num_probes = 0, 81 .lpe_viewpt_rqd = true, 82 }; 83 84 static const struct sst_ipc_info byt_ipc_info = { 85 .ipc_offset = 0, 86 .mbox_recv_off = 0x400, 87 }; 88 89 static const struct sst_lib_dnld_info byt_lib_dnld_info = { 90 .mod_base = SST_BYT_IMR_VIRT_START, 91 .mod_end = SST_BYT_IMR_VIRT_END, 92 .mod_table_offset = BYT_FW_MOD_TABLE_OFFSET, 93 .mod_table_size = BYT_FW_MOD_TABLE_SIZE, 94 .mod_ddr_dnld = false, 95 }; 96 97 static const struct sst_res_info byt_rvp_res_info = { 98 .shim_offset = 0x140000, 99 .shim_size = 0x000100, 100 .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR, 101 .ssp0_offset = 0xa0000, 102 .ssp0_size = 0x1000, 103 .dma0_offset = 0x98000, 104 .dma0_size = 0x4000, 105 .dma1_offset = 0x9c000, 106 .dma1_size = 0x4000, 107 .iram_offset = 0x0c0000, 108 .iram_size = 0x14000, 109 .dram_offset = 0x100000, 110 .dram_size = 0x28000, 111 .mbox_offset = 0x144000, 112 .mbox_size = 0x1000, 113 .acpi_lpe_res_index = 0, 114 .acpi_ddr_index = 2, 115 .acpi_ipc_irq_index = 5, 116 }; 117 118 /* BYTCR has different BIOS from BYT */ 119 static const struct sst_res_info bytcr_res_info = { 120 .shim_offset = 0x140000, 121 .shim_size = 0x000100, 122 .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR, 123 .ssp0_offset = 0xa0000, 124 .ssp0_size = 0x1000, 125 .dma0_offset = 0x98000, 126 .dma0_size = 0x4000, 127 .dma1_offset = 0x9c000, 128 .dma1_size = 0x4000, 129 .iram_offset = 0x0c0000, 130 .iram_size = 0x14000, 131 .dram_offset = 0x100000, 132 .dram_size = 0x28000, 133 .mbox_offset = 0x144000, 134 .mbox_size = 0x1000, 135 .acpi_lpe_res_index = 0, 136 .acpi_ddr_index = 2, 137 .acpi_ipc_irq_index = 0 138 }; 139 140 static struct sst_platform_info byt_rvp_platform_data = { 141 .probe_data = &byt_fwparse_info, 142 .ipc_info = &byt_ipc_info, 143 .lib_info = &byt_lib_dnld_info, 144 .res_info = &byt_rvp_res_info, 145 .platform = "sst-mfld-platform", 146 }; 147 148 /* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail, 149 * so pdata is same as Baytrail. 150 */ 151 static struct sst_platform_info chv_platform_data = { 152 .probe_data = &byt_fwparse_info, 153 .ipc_info = &byt_ipc_info, 154 .lib_info = &byt_lib_dnld_info, 155 .res_info = &byt_rvp_res_info, 156 .platform = "sst-mfld-platform", 157 }; 158 159 static int sst_platform_get_resources(struct intel_sst_drv *ctx) 160 { 161 struct resource *rsrc; 162 struct platform_device *pdev = to_platform_device(ctx->dev); 163 164 /* All ACPI resource request here */ 165 /* Get Shim addr */ 166 rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 167 ctx->pdata->res_info->acpi_lpe_res_index); 168 if (!rsrc) { 169 dev_err(ctx->dev, "Invalid SHIM base from IFWI\n"); 170 return -EIO; 171 } 172 dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start, 173 (unsigned int)resource_size(rsrc)); 174 175 ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset; 176 ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1; 177 dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base); 178 ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base, 179 ctx->pdata->res_info->iram_size); 180 if (!ctx->iram) { 181 dev_err(ctx->dev, "unable to map IRAM\n"); 182 return -EIO; 183 } 184 185 ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset; 186 ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1; 187 dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base); 188 ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base, 189 ctx->pdata->res_info->dram_size); 190 if (!ctx->dram) { 191 dev_err(ctx->dev, "unable to map DRAM\n"); 192 return -EIO; 193 } 194 195 ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset; 196 dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add); 197 ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add, 198 ctx->pdata->res_info->shim_size); 199 if (!ctx->shim) { 200 dev_err(ctx->dev, "unable to map SHIM\n"); 201 return -EIO; 202 } 203 204 /* reassign physical address to LPE viewpoint address */ 205 ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr; 206 207 /* Get mailbox addr */ 208 ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset; 209 dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add); 210 ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add, 211 ctx->pdata->res_info->mbox_size); 212 if (!ctx->mailbox) { 213 dev_err(ctx->dev, "unable to map mailbox\n"); 214 return -EIO; 215 } 216 217 /* reassign physical address to LPE viewpoint address */ 218 ctx->mailbox_add = ctx->info.mailbox_start; 219 220 rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 221 ctx->pdata->res_info->acpi_ddr_index); 222 if (!rsrc) { 223 dev_err(ctx->dev, "Invalid DDR base from IFWI\n"); 224 return -EIO; 225 } 226 ctx->ddr_base = rsrc->start; 227 ctx->ddr_end = rsrc->end; 228 dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base); 229 ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base, 230 resource_size(rsrc)); 231 if (!ctx->ddr) { 232 dev_err(ctx->dev, "unable to map DDR\n"); 233 return -EIO; 234 } 235 236 /* Find the IRQ */ 237 ctx->irq_num = platform_get_irq(pdev, 238 ctx->pdata->res_info->acpi_ipc_irq_index); 239 return 0; 240 } 241 242 243 static int is_byt_cr(struct device *dev, bool *bytcr) 244 { 245 int status = 0; 246 247 if (IS_ENABLED(CONFIG_IOSF_MBI)) { 248 static const struct x86_cpu_id cpu_ids[] = { 249 { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ 250 {} 251 }; 252 u32 bios_status; 253 254 if (!x86_match_cpu(cpu_ids) || !iosf_mbi_available()) { 255 /* bail silently */ 256 return status; 257 } 258 259 status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */ 260 MBI_REG_READ, /* 0x10 */ 261 0x006, /* BIOS_CONFIG */ 262 &bios_status); 263 264 if (status) { 265 dev_err(dev, "could not read PUNIT BIOS_CONFIG\n"); 266 } else { 267 /* bits 26:27 mirror PMIC options */ 268 bios_status = (bios_status >> 26) & 3; 269 270 if ((bios_status == 1) || (bios_status == 3)) 271 *bytcr = true; 272 else 273 dev_info(dev, "BYT-CR not detected\n"); 274 } 275 } else { 276 dev_info(dev, "IOSF_MBI not enabled, no BYT-CR detection\n"); 277 } 278 return status; 279 } 280 281 282 static int sst_acpi_probe(struct platform_device *pdev) 283 { 284 struct device *dev = &pdev->dev; 285 int ret = 0; 286 struct intel_sst_drv *ctx; 287 const struct acpi_device_id *id; 288 struct sst_acpi_mach *mach; 289 struct platform_device *mdev; 290 struct platform_device *plat_dev; 291 struct sst_platform_info *pdata; 292 unsigned int dev_id; 293 bool bytcr = false; 294 295 id = acpi_match_device(dev->driver->acpi_match_table, dev); 296 if (!id) 297 return -ENODEV; 298 dev_dbg(dev, "for %s\n", id->id); 299 300 mach = (struct sst_acpi_mach *)id->driver_data; 301 mach = sst_acpi_find_machine(mach); 302 if (mach == NULL) { 303 dev_err(dev, "No matching machine driver found\n"); 304 return -ENODEV; 305 } 306 307 pdata = mach->pdata; 308 309 ret = kstrtouint(id->id, 16, &dev_id); 310 if (ret < 0) { 311 dev_err(dev, "Unique device id conversion error: %d\n", ret); 312 return ret; 313 } 314 315 dev_dbg(dev, "ACPI device id: %x\n", dev_id); 316 317 ret = sst_alloc_drv_context(&ctx, dev, dev_id); 318 if (ret < 0) 319 return ret; 320 321 ret = is_byt_cr(dev, &bytcr); 322 if (!((ret < 0) || (bytcr == false))) { 323 dev_info(dev, "Detected Baytrail-CR platform\n"); 324 325 /* override resource info */ 326 byt_rvp_platform_data.res_info = &bytcr_res_info; 327 } 328 329 plat_dev = platform_device_register_data(dev, pdata->platform, -1, 330 NULL, 0); 331 if (IS_ERR(plat_dev)) { 332 dev_err(dev, "Failed to create machine device: %s\n", 333 pdata->platform); 334 return PTR_ERR(plat_dev); 335 } 336 337 /* 338 * Create platform device for sst machine driver, 339 * pass machine info as pdata 340 */ 341 mdev = platform_device_register_data(dev, mach->drv_name, -1, 342 (const void *)mach, sizeof(*mach)); 343 if (IS_ERR(mdev)) { 344 dev_err(dev, "Failed to create machine device: %s\n", 345 mach->drv_name); 346 return PTR_ERR(mdev); 347 } 348 349 /* Fill sst platform data */ 350 ctx->pdata = pdata; 351 strcpy(ctx->firmware_name, mach->fw_filename); 352 353 ret = sst_platform_get_resources(ctx); 354 if (ret) 355 return ret; 356 357 ret = sst_context_init(ctx); 358 if (ret < 0) 359 return ret; 360 361 sst_configure_runtime_pm(ctx); 362 platform_set_drvdata(pdev, ctx); 363 return ret; 364 } 365 366 /** 367 * intel_sst_remove - remove function 368 * 369 * @pdev: platform device structure 370 * 371 * This function is called by OS when a device is unloaded 372 * This frees the interrupt etc 373 */ 374 static int sst_acpi_remove(struct platform_device *pdev) 375 { 376 struct intel_sst_drv *ctx; 377 378 ctx = platform_get_drvdata(pdev); 379 sst_context_cleanup(ctx); 380 platform_set_drvdata(pdev, NULL); 381 return 0; 382 } 383 384 static unsigned long cht_machine_id; 385 386 #define CHT_SURFACE_MACH 1 387 #define BYT_THINKPAD_10 2 388 389 static int cht_surface_quirk_cb(const struct dmi_system_id *id) 390 { 391 cht_machine_id = CHT_SURFACE_MACH; 392 return 1; 393 } 394 395 static int byt_thinkpad10_quirk_cb(const struct dmi_system_id *id) 396 { 397 cht_machine_id = BYT_THINKPAD_10; 398 return 1; 399 } 400 401 402 static const struct dmi_system_id byt_table[] = { 403 { 404 .callback = byt_thinkpad10_quirk_cb, 405 .matches = { 406 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 407 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 10"), 408 }, 409 }, 410 { 411 .callback = byt_thinkpad10_quirk_cb, 412 .matches = { 413 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 414 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Tablet B"), 415 }, 416 }, 417 { 418 .callback = byt_thinkpad10_quirk_cb, 419 .matches = { 420 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 421 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Miix 2 10"), 422 }, 423 }, 424 { } 425 }; 426 427 static const struct dmi_system_id cht_table[] = { 428 { 429 .callback = cht_surface_quirk_cb, 430 .matches = { 431 DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"), 432 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), 433 }, 434 }, 435 { } 436 }; 437 438 439 static struct sst_acpi_mach cht_surface_mach = { 440 .id = "10EC5640", 441 .drv_name = "cht-bsw-rt5645", 442 .fw_filename = "intel/fw_sst_22a8.bin", 443 .board = "cht-bsw", 444 .pdata = &chv_platform_data, 445 }; 446 447 static struct sst_acpi_mach byt_thinkpad_10 = { 448 .id = "10EC5640", 449 .drv_name = "cht-bsw-rt5672", 450 .fw_filename = "intel/fw_sst_0f28.bin", 451 .board = "cht-bsw", 452 .pdata = &byt_rvp_platform_data, 453 }; 454 455 static struct sst_acpi_mach *cht_quirk(void *arg) 456 { 457 struct sst_acpi_mach *mach = arg; 458 459 dmi_check_system(cht_table); 460 461 if (cht_machine_id == CHT_SURFACE_MACH) 462 return &cht_surface_mach; 463 else 464 return mach; 465 } 466 467 static struct sst_acpi_mach *byt_quirk(void *arg) 468 { 469 struct sst_acpi_mach *mach = arg; 470 471 dmi_check_system(byt_table); 472 473 if (cht_machine_id == BYT_THINKPAD_10) 474 return &byt_thinkpad_10; 475 else 476 return mach; 477 } 478 479 480 static struct sst_acpi_mach sst_acpi_bytcr[] = { 481 { 482 .id = "10EC5640", 483 .drv_name = "bytcr_rt5640", 484 .fw_filename = "intel/fw_sst_0f28.bin", 485 .board = "bytcr_rt5640", 486 .machine_quirk = byt_quirk, 487 .pdata = &byt_rvp_platform_data, 488 }, 489 { 490 .id = "10EC5642", 491 .drv_name = "bytcr_rt5640", 492 .fw_filename = "intel/fw_sst_0f28.bin", 493 .board = "bytcr_rt5640", 494 .pdata = &byt_rvp_platform_data 495 }, 496 { 497 .id = "INTCCFFD", 498 .drv_name = "bytcr_rt5640", 499 .fw_filename = "intel/fw_sst_0f28.bin", 500 .board = "bytcr_rt5640", 501 .pdata = &byt_rvp_platform_data 502 }, 503 { 504 .id = "10EC5651", 505 .drv_name = "bytcr_rt5651", 506 .fw_filename = "intel/fw_sst_0f28.bin", 507 .board = "bytcr_rt5651", 508 .pdata = &byt_rvp_platform_data 509 }, 510 { 511 .id = "DLGS7212", 512 .drv_name = "bytcht_da7213", 513 .fw_filename = "intel/fw_sst_0f28.bin", 514 .board = "bytcht_da7213", 515 .pdata = &byt_rvp_platform_data 516 }, 517 { 518 .id = "DLGS7213", 519 .drv_name = "bytcht_da7213", 520 .fw_filename = "intel/fw_sst_0f28.bin", 521 .board = "bytcht_da7213", 522 .pdata = &byt_rvp_platform_data 523 }, 524 /* some Baytrail platforms rely on RT5645, use CHT machine driver */ 525 { 526 .id = "10EC5645", 527 .drv_name = "cht-bsw-rt5645", 528 .fw_filename = "intel/fw_sst_0f28.bin", 529 .board = "cht-bsw", 530 .pdata = &byt_rvp_platform_data 531 }, 532 { 533 .id = "10EC5648", 534 .drv_name = "cht-bsw-rt5645", 535 .fw_filename = "intel/fw_sst_0f28.bin", 536 .board = "cht-bsw", 537 .pdata = &byt_rvp_platform_data 538 }, 539 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH) 540 /* 541 * This is always last in the table so that it is selected only when 542 * enabled explicitly and there is no codec-related information in SSDT 543 */ 544 { 545 .id = "80860F28", 546 .drv_name = "bytcht_nocodec", 547 .fw_filename = "intel/fw_sst_0f28.bin", 548 .board = "bytcht_nocodec", 549 .pdata = &byt_rvp_platform_data 550 }, 551 #endif 552 {}, 553 }; 554 555 /* Cherryview-based platforms: CherryTrail and Braswell */ 556 static struct sst_acpi_mach sst_acpi_chv[] = { 557 { 558 .id = "10EC5670", 559 .drv_name = "cht-bsw-rt5672", 560 .fw_filename = "intel/fw_sst_22a8.bin", 561 .board = "cht-bsw", 562 .pdata = &chv_platform_data 563 }, 564 { 565 .id = "10EC5672", 566 .drv_name = "cht-bsw-rt5672", 567 .fw_filename = "intel/fw_sst_22a8.bin", 568 .board = "cht-bsw", 569 .pdata = &chv_platform_data 570 }, 571 { 572 .id = "10EC5645", 573 .drv_name = "cht-bsw-rt5645", 574 .fw_filename = "intel/fw_sst_22a8.bin", 575 .board = "cht-bsw", 576 .pdata = &chv_platform_data 577 }, 578 { 579 .id = "10EC5650", 580 .drv_name = "cht-bsw-rt5645", 581 .fw_filename = "intel/fw_sst_22a8.bin", 582 .board = "cht-bsw", 583 .pdata = &chv_platform_data 584 }, 585 { 586 .id = "10EC3270", 587 .drv_name = "cht-bsw-rt5645", 588 .fw_filename = "intel/fw_sst_22a8.bin", 589 .board = "cht-bsw", 590 .pdata = &chv_platform_data 591 }, 592 593 { 594 .id = "193C9890", 595 .drv_name = "cht-bsw-max98090", 596 .fw_filename = "intel/fw_sst_22a8.bin", 597 .board = "cht-bsw", 598 .pdata = &chv_platform_data 599 }, 600 { 601 .id = "DLGS7212", 602 .drv_name = "bytcht_da7213", 603 .fw_filename = "intel/fw_sst_22a8.bin", 604 .board = "bytcht_da7213", 605 .pdata = &chv_platform_data 606 }, 607 { 608 .id = "DLGS7213", 609 .drv_name = "bytcht_da7213", 610 .fw_filename = "intel/fw_sst_22a8.bin", 611 .board = "bytcht_da7213", 612 .pdata = &chv_platform_data 613 }, 614 { 615 .id = "ESSX8316", 616 .drv_name = "bytcht_es8316", 617 .fw_filename = "intel/fw_sst_22a8.bin", 618 .board = "bytcht_es8316", 619 .pdata = &chv_platform_data 620 }, 621 /* some CHT-T platforms rely on RT5640, use Baytrail machine driver */ 622 { 623 .id = "10EC5640", 624 .drv_name = "bytcr_rt5640", 625 .fw_filename = "intel/fw_sst_22a8.bin", 626 .board = "bytcr_rt5640", 627 .machine_quirk = cht_quirk, 628 .pdata = &chv_platform_data 629 }, 630 { 631 .id = "10EC3276", 632 .drv_name = "bytcr_rt5640", 633 .fw_filename = "intel/fw_sst_22a8.bin", 634 .board = "bytcr_rt5640", 635 .pdata = &chv_platform_data 636 }, 637 /* some CHT-T platforms rely on RT5651, use Baytrail machine driver */ 638 { 639 .id = "10EC5651", 640 .drv_name = "bytcr_rt5651", 641 .fw_filename = "intel/fw_sst_22a8.bin", 642 .board = "bytcr_rt5651", 643 .pdata = &chv_platform_data 644 }, 645 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH) 646 /* 647 * This is always last in the table so that it is selected only when 648 * enabled explicitly and there is no codec-related information in SSDT 649 */ 650 { 651 .id = "808622A8", 652 .drv_name = "bytcht_nocodec", 653 .fw_filename = "intel/fw_sst_22a8.bin", 654 .board = "bytcht_nocodec", 655 .pdata = &chv_platform_data 656 }, 657 #endif 658 {}, 659 }; 660 661 static const struct acpi_device_id sst_acpi_ids[] = { 662 { "80860F28", (unsigned long)&sst_acpi_bytcr}, 663 { "808622A8", (unsigned long) &sst_acpi_chv}, 664 { }, 665 }; 666 667 MODULE_DEVICE_TABLE(acpi, sst_acpi_ids); 668 669 static struct platform_driver sst_acpi_driver = { 670 .driver = { 671 .name = "intel_sst_acpi", 672 .acpi_match_table = ACPI_PTR(sst_acpi_ids), 673 .pm = &intel_sst_pm, 674 }, 675 .probe = sst_acpi_probe, 676 .remove = sst_acpi_remove, 677 }; 678 679 module_platform_driver(sst_acpi_driver); 680 681 MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver"); 682 MODULE_AUTHOR("Ramesh Babu K V"); 683 MODULE_AUTHOR("Omair Mohammed Abdullah"); 684 MODULE_LICENSE("GPL v2"); 685 MODULE_ALIAS("sst"); 686