1 /* 2 * linux/sound/soc/hisilicon/hi6210-i2s.h 3 * 4 * Copyright (C) 2015 Linaro, Ltd 5 * Author: Andy Green <andy.green@linaro.org> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 * Note at least on 6220, S2 == BT, S1 == Digital FM Radio IF 20 */ 21 22 #ifndef _HI6210_I2S_H 23 #define _HI6210_I2S_H 24 25 #define HII2S_SW_RST_N 0 26 27 #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT 28 28 #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK 3 29 #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT 26 30 #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK 3 31 #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT 24 32 #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK 3 33 #define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT 20 34 #define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK 3 35 #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT 18 36 #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK 3 37 #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT 16 38 #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK 3 39 40 #define HII2S_SW_RST_N__SW_RST_N BIT(0) 41 42 enum hi6210_bits { 43 HII2S_BITS_16, 44 HII2S_BITS_18, 45 HII2S_BITS_20, 46 HII2S_BITS_24, 47 }; 48 49 50 #define HII2S_IF_CLK_EN_CFG 4 51 52 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25) 53 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24) 54 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20) 55 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16) 56 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15) 57 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14) 58 #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13) 59 #define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN BIT(12) 60 #define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN BIT(10) 61 #define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN BIT(9) 62 #define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN BIT(8) 63 #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN BIT(7) 64 #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN BIT(6) 65 #define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN BIT(5) 66 #define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN BIT(4) 67 #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN BIT(3) 68 #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN BIT(2) 69 #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN BIT(1) 70 #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN BIT(0) 71 72 #define HII2S_DIG_FILTER_CLK_EN_CFG 8 73 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN BIT(30) 74 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN BIT(28) 75 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN BIT(25) 76 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN BIT(24) 77 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN BIT(22) 78 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN BIT(20) 79 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN BIT(17) 80 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN BIT(16) 81 82 #define HII2S_FS_CFG 0xc 83 84 #define HII2S_FS_CFG__FS_S2_SHIFT 28 85 #define HII2S_FS_CFG__FS_S2_MASK 7 86 #define HII2S_FS_CFG__FS_S1_SHIFT 24 87 #define HII2S_FS_CFG__FS_S1_MASK 7 88 #define HII2S_FS_CFG__FS_ADCLR_SHIFT 20 89 #define HII2S_FS_CFG__FS_ADCLR_MASK 7 90 #define HII2S_FS_CFG__FS_DACLR_SHIFT 16 91 #define HII2S_FS_CFG__FS_DACLR_MASK 7 92 #define HII2S_FS_CFG__FS_ST_DL_R_SHIFT 8 93 #define HII2S_FS_CFG__FS_ST_DL_R_MASK 7 94 #define HII2S_FS_CFG__FS_ST_DL_L_SHIFT 4 95 #define HII2S_FS_CFG__FS_ST_DL_L_MASK 7 96 #define HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT 0 97 #define HII2S_FS_CFG__FS_VOICE_DLINK_MASK 7 98 99 enum hi6210_i2s_rates { 100 HII2S_FS_RATE_8KHZ = 0, 101 HII2S_FS_RATE_16KHZ = 1, 102 HII2S_FS_RATE_32KHZ = 2, 103 HII2S_FS_RATE_48KHZ = 4, 104 HII2S_FS_RATE_96KHZ = 5, 105 HII2S_FS_RATE_192KHZ = 6, 106 }; 107 108 #define HII2S_I2S_CFG 0x10 109 110 #define HII2S_I2S_CFG__S2_IF_TX_EN BIT(31) 111 #define HII2S_I2S_CFG__S2_IF_RX_EN BIT(30) 112 #define HII2S_I2S_CFG__S2_FRAME_MODE BIT(29) 113 #define HII2S_I2S_CFG__S2_MST_SLV BIT(28) 114 #define HII2S_I2S_CFG__S2_LRCK_MODE BIT(27) 115 #define HII2S_I2S_CFG__S2_CHNNL_MODE BIT(26) 116 #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT 24 117 #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK 3 118 #define HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT 22 119 #define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK 3 120 #define HII2S_I2S_CFG__S2_TX_CLK_SEL BIT(21) 121 #define HII2S_I2S_CFG__S2_RX_CLK_SEL BIT(20) 122 #define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT BIT(19) 123 #define HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT 16 124 #define HII2S_I2S_CFG__S2_FUNC_MODE_MASK 7 125 #define HII2S_I2S_CFG__S1_IF_TX_EN BIT(15) 126 #define HII2S_I2S_CFG__S1_IF_RX_EN BIT(14) 127 #define HII2S_I2S_CFG__S1_FRAME_MODE BIT(13) 128 #define HII2S_I2S_CFG__S1_MST_SLV BIT(12) 129 #define HII2S_I2S_CFG__S1_LRCK_MODE BIT(11) 130 #define HII2S_I2S_CFG__S1_CHNNL_MODE BIT(10) 131 #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT 8 132 #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK 3 133 #define HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT 6 134 #define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK 3 135 #define HII2S_I2S_CFG__S1_TX_CLK_SEL BIT(5) 136 #define HII2S_I2S_CFG__S1_RX_CLK_SEL BIT(4) 137 #define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT BIT(3) 138 #define HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT 0 139 #define HII2S_I2S_CFG__S1_FUNC_MODE_MASK 7 140 141 enum hi6210_i2s_formats { 142 HII2S_FORMAT_I2S, 143 HII2S_FORMAT_PCM_STD, 144 HII2S_FORMAT_PCM_USER, 145 HII2S_FORMAT_LEFT_JUST, 146 HII2S_FORMAT_RIGHT_JUST, 147 }; 148 149 #define HII2S_DIG_FILTER_MODULE_CFG 0x14 150 151 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT 28 152 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK 3 153 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE BIT(27) 154 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE BIT(26) 155 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE BIT(25) 156 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE BIT(24) 157 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT 20 158 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK 3 159 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE BIT(19) 160 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE BIT(18) 161 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE BIT(17) 162 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE BIT(16) 163 #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER BIT(9) 164 #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER BIT(8) 165 #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT 4 166 #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK 7 167 #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT 0 168 #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK 7 169 170 enum hi6210_gains { 171 HII2S_GAIN_100PC, 172 HII2S_GAIN_50PC, 173 HII2S_GAIN_25PC, 174 }; 175 176 #define HII2S_MUX_TOP_MODULE_CFG 0x18 177 178 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT 14 179 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK 3 180 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE BIT(13) 181 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE BIT(12) 182 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT 10 183 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK 3 184 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE BIT(9) 185 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE BIT(8) 186 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY BIT(6) 187 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT 4 188 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK 3 189 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY BIT(3) 190 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT 0 191 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK 7 192 193 enum hi6210_s2_src_mode { 194 HII2S_S2_SRC_MODE_3, 195 HII2S_S2_SRC_MODE_12, 196 HII2S_S2_SRC_MODE_6, 197 HII2S_S2_SRC_MODE_2, 198 }; 199 200 enum hi6210_voice_dlink_src_mode { 201 HII2S_VOICE_DL_SRC_MODE_12 = 1, 202 HII2S_VOICE_DL_SRC_MODE_6, 203 HII2S_VOICE_DL_SRC_MODE_2, 204 HII2S_VOICE_DL_SRC_MODE_3, 205 }; 206 207 #define HII2S_ADC_PGA_CFG 0x1c 208 #define HII2S_S1_INPUT_PGA_CFG 0x20 209 #define HII2S_S2_INPUT_PGA_CFG 0x24 210 #define HII2S_ST_DL_PGA_CFG 0x28 211 #define HII2S_VOICE_SIDETONE_DLINK_PGA_CFG 0x2c 212 #define HII2S_APB_AFIFO_CFG_1 0x30 213 #define HII2S_APB_AFIFO_CFG_2 0x34 214 #define HII2S_ST_DL_FIFO_TH_CFG 0x38 215 216 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT 24 217 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK 0x1f 218 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT 16 219 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK 0x1f 220 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT 8 221 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK 0x1f 222 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT 0 223 #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK 0x1f 224 225 #define HII2S_STEREO_UPLINK_FIFO_TH_CFG 0x3c 226 #define HII2S_VOICE_UPLINK_FIFO_TH_CFG 0x40 227 #define HII2S_CODEC_IRQ_MASK 0x44 228 #define HII2S_CODEC_IRQ 0x48 229 #define HII2S_DACL_AGC_CFG_1 0x4c 230 #define HII2S_DACL_AGC_CFG_2 0x50 231 #define HII2S_DACR_AGC_CFG_1 0x54 232 #define HII2S_DACR_AGC_CFG_2 0x58 233 #define HII2S_DMIC_SIF_CFG 0x5c 234 #define HII2S_MISC_CFG 0x60 235 236 #define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL BIT(17) 237 #define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL BIT(16) 238 #define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL BIT(14) 239 #define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL BIT(13) 240 #define HII2S_MISC_CFG__S3_DIN_TEST_SEL BIT(12) 241 #define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL BIT(8) 242 #define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL BIT(7) 243 #define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL BIT(6) 244 #define HII2S_MISC_CFG__ST_DL_TEST_SEL BIT(4) 245 #define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL BIT(3) 246 #define HII2S_MISC_CFG__S2_DOUT_TEST_SEL BIT(2) 247 #define HII2S_MISC_CFG__S1_DOUT_TEST_SEL BIT(1) 248 #define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL BIT(0) 249 250 #define HII2S_S2_SRC_CFG 0x64 251 #define HII2S_MEM_CFG 0x68 252 #define HII2S_THIRDMD_PCM_PGA_CFG 0x6c 253 #define HII2S_THIRD_MODEM_FIFO_TH 0x70 254 #define HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT 0x74 255 #define HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT 0x78 256 #define HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT 0x7c 257 #define HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT 0x80 258 #define HII2S_ANTI_FREQ_JITTER_EN 0x84 259 #define HII2S_CLK_SEL 0x88 260 261 /* 0 = BT owns the i2s */ 262 #define HII2S_CLK_SEL__I2S_BT_FM_SEL BIT(0) 263 /* 0 = internal source, 1 = ext */ 264 #define HII2S_CLK_SEL__EXT_12_288MHZ_SEL BIT(1) 265 266 267 #define HII2S_THIRDMD_DLINK_CHANNEL 0xe8 268 #define HII2S_THIRDMD_ULINK_CHANNEL 0xec 269 #define HII2S_VOICE_DLINK_CHANNEL 0xf0 270 271 /* shovel data in here for playback */ 272 #define HII2S_ST_DL_CHANNEL 0xf4 273 #define HII2S_STEREO_UPLINK_CHANNEL 0xf8 274 #define HII2S_VOICE_UPLINK_CHANNEL 0xfc 275 276 #endif/* _HI6210_I2S_H */ 277